A Novel High-Breakdown-Voltage SOI MESFET by Modified Charge Distribution

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 5, MAY 2012 1255

A Novel High-Breakdown-Voltage SOI MESFETby Modified Charge Distribution

Amirhossein Aminbeidokhti, Ali A. Orouji, Member, IEEE, Soude Rahmaninezhad, and Masoomeh Ghasemian

Abstract—In this paper, a novel silicon-on-insulator (SOI)metal–semiconductor field-effect transistor (MESFET) with modi-fied charge distribution is presented. Changing charge distributionleads to lower electric field crowding and increased breakdownvoltage (VBR). For modifying charge distribution, a metal region(MR) is utilized in buried oxide of the SOI MESFET. In orderto achieve the best results, the MR location and dimensions areoptimized carefully. DC and radio frequency characteristics ofthe SOI MESFET with MR (MR-SOI MESFET) are analyzed by2-D numerical simulation and compared with conventional SOIMESFET (C-SOI MESFET) characteristics. The simulated resultsshow that the MR has excellent effect on the VBR of the device.The VBR of the MR-SOI MESFET structure improves by 116%compared with that of the C-SOI MESFET structure. Althoughdrain current of the proposed structure reduces slightly, 126%improvement in maximum output power density of the device isachieved due to high enhancement of the VBR. Also, the MRleads to the enhancement of maximum oscillation frequency andmaximum available gain of the MR-SOI MESFET structure. Asa result, the MR-SOI MESFET structure has superior electricalperformances in comparison with the similar device based on theconventional structure.

Index Terms—Metal–semiconductor field-effect transistor(MESFET), modified charge distribution, silicon on insulator(SOI), superior electrical performances.

I. INTRODUCTION

NOWADAYS, silicon-on-insulator (SOI) technologyattracts much attention in high-speed and low-power-

consumption applications. SOI structures have important ad-vantages such as low junction capacitance, latch-up immunity,and improved device isolation because of utilizing the buriedoxide (BOX) [1]. Metal–semiconductor field-effect transistor(MESFET) is a very promising candidate for high-power appli-cations in military communications, telecommunication cellu-lar base stations, satellites, aerospace, and data storage [2]–[4].SOI MESFETs are taken into consideration for high-power andhigh-speed applications. Furthermore, they have the advantageof being compatible with mainstream CMOS processing. TheSOI CMOS is a low-cost technology that can be used for radiofrequency (RF) integrated circuits because of its ability tomerge RF circuits and digital logic on a single chip [5]–[7].

Manuscript received July 11, 2011; revised January 22, 2012; acceptedJanuary 26, 2012. Date of publication March 15, 2012; date of current versionApril 25, 2012. The review of this paper was arranged by Editor G. Jeong.

The authors are with the Department of Electrical Engineering, SemnanUniversity, Semnan 35196-45399, Iran (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2012.2186580

In SOI technology, SOI metal–oxide–semiconductor field-effect transistor (MOSFET) is commonly investigated andtaken into consideration, while the SOI MESFET can be a bet-ter option in ultra-large-scale integration technology. The keyadvantage of the SOI MESFET is higher mobility of the carriersin the channel region in comparison with that of the SOIMOSFET. As the carriers placed in the inversion layer of aSOI MOSFET structure have a wave function that extends intothe oxide, their mobility, which is also referred to as surfacemobility, is lower than half of the bulk material mobility. Sincethe depletion region of the SOI MESFET structure separatesthe carriers from the surface, their mobility is near to that of thebulk material. Higher mobility leads to higher transconductance(gm), current, and frequency parameters of the device [8]. Also,the absence of gate-oxide connection in the SOI MESFETstructure causes the device to be able to tolerate high voltages,i.e., breakdown voltage (VBR) of the SOI MESFET structureis at least three times larger than that of the SOI MOSFETstructure [5], [6], [8]. Furthermore, the metal-gate connectionleads the device to have a better control on the channel regionwhich is important for high-speed applications. Thus, the SOIMESFET structure can be taken into consideration as a devicewith excellent RF characteristics and can be employed for high-power applications.

On account of the recent progresses in analyzing and improv-ing the SOI MESFET characteristics, a number of important in-vestigations for the SOI MESFET structure have been reported[9]–[13]. The charge distribution plays an important role indetermining device characteristics [14]–[17]. The key idea ofthis paper is to modify charge distribution of the channel regionin order to lower the electric field of the device and improvethe VBR. For changing the charge distribution, a metal region(MR) is used in the BOX of the proposed structure. Thus, inthis paper, for the first time, we introduce a novel SOI MESFETstructure with an MR (MR-SOI MESFET) in the BOX. Afterutilizing the MR in the structure and optimizing its locationand dimensions, the MR-SOI MESFET characteristics such ashole concentration, electric field distribution, VBR, potentialdistribution, drain current (ID), output power density, unilateralpower gain (U ), maximum available gain (MAG), and currentgain (fT ) are analyzed. The aim of utilizing the MR in the BOXof the proposed structure is to get a high-power and high-speeddevice.

II. MR-MESFET STRUCTURE AND SIMULATION METHOD

Fig. 1(a) and (b) shows the schematic view of the conven-tional SOI MESFET (C-SOI MESFET) and MR-SOI MESFET

0018-9383/$31.00 © 2012 IEEE

1256 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 5, MAY 2012

Fig. 1. Schematic cross sections of SOI MESFET structures. (a) C-SOIMESFET structure. (b) MR-SOI MESFET structure.

structures, respectively. The MR-SOI MESFET is a stack ofa p-type substrate, a BOX, an n-type channel layer, and twon-type cap layers. Compared with the C-SOI MESFET struc-ture, there is an additional MR in the BOX of the MR-SOIMESFET structure. The dimensions of the proposed structureare as follows: The source and drain lengths are 0.5 μm, gatelength LG = 0.6 μm, gate–drain spacing LGD = 0.6 μm, andgate–source spacing LGS = 0.6 μm. Also, the p-type substratelayer thickness is 0.1 μm with doping of 1 × 1013 cm−3, theBOX thickness is 0.4 μm, the n-type active layer is doped at1 × 1017 cm−3 with a thickness of 0.2 μm, and the n-type caplayers have doping level > 1020 cm−3. Nickel was chosen forthe gate Schottky contact with a work function (ϕm) of 5.1 eV.W and H are the width and height of the MR, respectively.S is the MR-channel region spacing, and L is the distancebetween the MR and the device left end. After optimization

Fig. 2. Process flow for the fabrication of the proposed MR-SOI MESFET.

of the MR dimensions and location, which will be mentionedin the following, W = 0.35 μm, H = 0.05 μm, L = 1.9 μm,and S = 0.05 μm are achieved. A temperature of 300 K isemployed by default in the simulations. The C-SOI MESFETparameters are the same to those of the MR-SOI MESFET, butC-SOI MESFET does not have the MR.

We also propose a process flow for the fabrication of the MR-SOI MESFET, which can use the Smart-Cut technique [18]–[20] for the creation of the SOI device and the damasceneapproach in order to add an MR to the BOX layer. Fig. 2 showsthe basic steps of such a process. The starting materials arean n-type 〈100〉-oriented silicon wafer called wafer A and onep-type 〈100〉-oriented silicon wafer named wafer B, which canbe seen in Fig. 2(a). As shown in Fig. 2(b), a thermal oxidecan be grown and structured over at least one of the wafers,which serves as a surface protection layer for wafer handlingduring the subsequent implantation. After that, hydrogen ionsare implanted into wafer A which can be seen in Fig. 2(c).This step induces the formation of a quite deep weakened zone.Then, a via is defined in the oxide layer [Fig. 2(d)] beforedepositing a layer of metal on the oxide [Fig. 2(e)]. As shownin Fig. 2(f), the surface oxide is removed by a CMP processto eliminate the residual defect region over the oxide. In thisstep, a layer of oxide with certain thickness is formed on thedevice, which is shown in Fig. 2(g), in order for the metal tobe located in the BOX of the SOI device. Fig. 2(h) shows thatwafer A is bonded to support B by wafer bonding. The splitting

AMINBEIDOKHTI et al.: NOVEL SOI MESFET BY MODIFIED CHARGE DISTRIBUTION 1257

Fig. 3. Comparison of the drain current versus drain voltage for the experi-mental data and simulation results.

step takes place inside the weakened zone and gives rise to thetransfer of a thin layer from wafer A onto support B which isshown in Fig. 2(i). Finally, Fig. 2(j) shows that a treatment suchas CMP can be performed to remove the rough surface left aftersplitting and a conventional process can be employed to finishthe MR-SOI MESFET fabrication, as shown in Fig. 2(k).

Atlas that is a 2-D simulator from Silvaco [21] with sil-icon (Si) material parameters is used for device simulation.The Atlas is a general device simulator, and it is not re-stricted to SOI layouts. It supports both DC and RF analysesof the device. It is important to note that the simulator iscalibrated with experimental data in the micrometer regime[9] and a pleasant agreement between experimental data andsimulation results is obtained, which is shown in Fig. 3. Inorder to have adequate and precise results, furthermore, thebasic Poisson and drift–diffusion equations and some otherimpressive physical models are utilized simultaneously such asSRH (Shockley–Read–Hall), Auger, Bbt.std, Analytic, Fldmob,Conmob, Incomplete, and Impact Selb. Also, it should be notedthat, in the Atlas simulator, the VBR value is related to thebreakdown electric field which is 3 × 105 V/cm for Si devices.Thus, the voltage at which the electric field is equal to thebreakdown electric field is defined as the VBR of the device.

III. DC RESULTS AND DISCUSSIONS

The hole concentrations of the MR-SOI MESFET andC-SOI MESFET structures along the surface at VD = 5 Vand VG = −3 V are shown in Fig. 4, where VD is the drainvoltage and VG is the gate voltage. The negative bias of the gateleads to the sending out of the electrons around the gate andthe placement of the holes in electron locations. Therefore, alarge number of holes surround the gate. The figure shows thatthe hole concentration of the proposed structure is modified incomparison with that of the conventional structure. The Gausslaw is given by

∂E

∂x=

ρ

εS=q(p− n+ND −NA)

εS(1)

where E is the electric field, ρ is the charge density, εS is thesemiconductor permittivity, p is the hole concentration, n is theelectron concentration, ND is the donor concentration, and NA

Fig. 4. Hole concentration distribution along the surface, at VD = 5 V andVG = −3 V.

is the acceptor concentration. According to the figure and (1),lower hole concentration around the gate of the MR-SOIMESFET structure reduces the electric field crowding of thedevice, and lower electric field crowding around the gate leadsto an increase of the VBR.

The 2-D electric field distributions of the MR-SOI MESFETand C-SOI MESFET structures are shown in Fig. 5(a) and (b),respectively. In the C-SOI MESFET structure, the breakdownoccurs at the gate edge near the drain where there is highelectric field crowding and the device electric field is equal toits critical value. By utilizing the MR in the MR-SOI MESFETstructure and optimizing its position and dimensions, therewould be high electric field crowding near the MR edges. Itreduces the electric field crowding near the gate edge, modifiesthe electric field in the channel, and modulates the surfaceelectric field distribution. Thus, a higher voltage is required forthe electric field of the MR-SOI MESFET structure to reach thecritical amount. Also, a comparison of the channel electric fielddistribution along the surface of the MR-SOI MESFET andC-SOI MESFET structures at VD = 5 V and VG = Vth isshown in Fig. 6. The Vth is the threshold voltage, and it is equalto −3 V for both structures. As expected, it can be seen thatthe electric field of the proposed structure has a lower peak andmore monotonous distribution in comparison with that of theC-SOI MESFET structure. It leads to an improvement of theVBR of the MR-SOI MESFET structure. According to Fig. 7 thatshows the VBR of the MR-SOI MESFET and C-SOI MESFETstructures at VG = Vth, significant enhancement in the VBR ofthe proposed structure can be seen. The VBR improves from9.5 V for the C-SOI MESFET to 20.5 V for the MR-SOIMESFET. Therefore, a 116% increase in the VBR of the pro-posed structure is achieved, and the device can tolerate muchhigher voltages compared with the C-SOI MESFET structure.

The equipotential contours of the C-SOI MESFET andMR-SOI MESFET structures at their VBR are shown in Fig. 8(a)and (b), respectively. The figure shows the extraordinary effectof the MR in distributing the potential lines toward the drain.This means that, by utilizing the MR in the proposed structure,the equipotential contours are evenly spaced in comparison withthat of the C-SOI MESFET structure. In the C-SOI MESFETstructure, the potential is crowded at the gate edge, whichleads to the gathering of high electric field in the Si surfaceunder the gate edge, but in the MR-SOI MESFET structure,


Fig. 5. Two-dimensional distribution of the electric field lines for the(a) C-SOI MESFET and (b) MR-SOI MESFET.

Fig. 6. Electric field distribution from device left end to right end for MR-SOIMESFET and C-SOI MESFET structures, at VD = 5 V and VG = −3 V.

the potential crowding at the gate edge is weakened due to theeffect of the MR. It should be noted that, if the MR location anddimensions vary, the voltage division between the gate and thedrain changes too.

Fig. 7. Three-terminal breakdown characteristics for MR-SOI MESFET andC-SOI MESFET structures, at VG = −3 V.

Fig. 8. Simulated equipotential contours at breakdown voltage for the(a) C-SOI MESFET and (b) MR-SOI MESFET.

The potential distribution from the device left end to right endon the Schottky junction plane of the MR-SOI MESFET andC-SOI MESFET structures at VD = VBR is shown in Fig. 9.The figure shows that there is always a thermal equilibriumbetween the MR and the BOX at the contact point that keeps thepotential constant along its width; the drain voltage is sustained


Fig. 9. Potential distribution along device left end to right end for MR-SOIMESFET and C-SOI MESFET structures, at VD = VBR and VG = −3 V.

Fig. 10. Drain current against drain–source voltage for MR-SOI MESFETand C-SOI MESFET structures.

by the normal gate and the MR together for the proposedstructure.

The simulated ID versus drain–source voltage (VDS) ofthe MR-SOI MESFET and C-SOI MESFET structures undervarious gate biases of −2 to 1 V with steps of 1 V is plotted inFig. 10. It can be seen that the ID of the proposed structureis lower than that of the C-SOI MESFET structure. The IDreduces from 108.5 mA/mm for the conventional structureto 99 mA/mm for the proposed structure, at VDS = 5 V andVG = 0 V. Current path of the SOI MESFET is modulated bythe depletion width under the gate. When a positive voltage isapplied to the drain with respect to the source, electrons flowfrom the source to the drain. Therefore, the source acts as originof the carriers, and the drain acts as the sink. The gate electrodeforms a rectifying junction and controls the net opening of thechannel region by alteration of the depletion width. The deviceis fundamentally a voltage-controlled resistor, and its resistancecan be supervised by changing the width of the depletion regionextending into the channel region [23].

The depletion region widths at the drain and source edges aregiven by

WD =

√2εS(ψbi + VD − VG)

qND(2)

Fig. 11. Variations of the breakdown voltage for the MR-SOI MESFETstructure according to spacing between the MR and device left end, at VG =−3 V.

WS =

√2εS(ψbi − VG)

qND(3)

where ψbi is the built-in potential [23]. In the C-SOI MESFETstructure, by biasing electrodes, a depletion region is created inthe conductive channel, and according to (2) and (3), a decreaseof the gate bias in the negative side and an increase of the drainvoltage in the positive side lead to the enhancement of the de-pletion region width. Finally, the net channel is totally pinchedoff by the depletion width, and the current saturation happens.As the depletion region width increases, the ID decreases more.In the MR-SOI MESFET, the MR which is located in the BOXmakes an extra depletion region around itself. A part of theMR depletion region penetrates into the conductive channeland increases the total depletion region of the channel. Becauseof the spacing between the MR and the conductive channel, asmall part of the MR depletion region appears in the channel,and it cannot affect much the ID of the device. Therefore, theID of the proposed structure is slightly lower compared withthat of the C-SOI MESFET structure.

The theoretical maximum output power density (Pmax) of aclass-A amplifier is given as follows [22]:

Pmax =ID sat(VBR − VKnee)

8(4)

where IDsat is the drain saturation current and VKnee is the kneevoltage. High improvement in the VBR of the proposed structuremakes a significant increase in the output power density. ThePmax values of the MR-SOI MESFET and C-SOI MESFET are0.228 and 0.101 W/mm, respectively. Thus, 126% enhancementin the Pmax of the proposed structure is achieved. Therefore, theproposed structure has much higher power density than that ofthe conventional structure.

IV. MR LOCATION AND DIMENSIONS OPTIMIZATION

In order to achieve the best results, it is important to optimizethe MR location and dimensions. At first, an MR with specificdimensions is considered in the BOX, and by changing its loca-tion, the best place for situating it is achieved. The initial valuesfor W and H are determined as 0.2 and 0.05 μm, respectively.Fig. 11 shows the VBR against the spacing between the MR and


Fig. 12. MR-SOI MESFET drain current variations versus the distance be-tween the MR and device left end, at VD = 5 V and VG = 0 V.

the device left end for various MR–channel spacing, at VG =−3 V. When the MR is much close to the gate edge besidethe drain, the electric field crowding around the MR affectsthat around the gate edge, and further electric field crowdingappears around the gate edge. Therefore, an increase in the gateedge electric field occurs. Also, when the MR is so far awayfrom the gate edge, its effects on reduction of the electric fieldaround the gate edge reduce, and the MR cannot modify andlower the gate electric field. As a result, in order to modify thechannel electric field, lower the electric field crowding at thegate edge, and increase the VBR, the MR should not be so faraway from or much close to the gate edge in both horizontaland vertical directions. Thus, a tradeoff has to be considered.Regarding to the figure, at L = 1.9 μm and S = 0.05 μm, theVBR has the highest value.

Because of the importance of achieving a high-power deviceand also for controlling the output power density, the ID versusthe distance between the MR and device left end for variousMR–channel spacing is shown in Fig. 12. The MR creates adepletion region around itself. When the MR situation is closeto that of the channel region, a part of the MR depletion regionenters the channel and increases the depletion regions locatedin the channel. As the MR location is nearer the channel region,a higher amount of the MR depletion region penetrates thechannel, and it lowers the ID. High VBR and suitable ID atL = 1.9 μm and S = 0.05 μm lead to having the best outputpower density in this location.

After determining the MR best situation, now, let us try tofind its dimensions to achieve excellent results. Fig. 13 showsthe VBR variations according to the MR length. As the MRlength increases, it can modulate more parts of the channelelectric field distribution. Thus, by increasing the MR length,more monotonous electric field and higher VBR are expectedto be achieved. When the MR length is higher than a specialamount, the MR edge beside the drain will be so far away fromthe gate edge near the drain, and the MR effect on reductionof the electric field crowding at the gate edge will be lower.Therefore, the effect of the MR with high lengths on reductionof the electric field at the gate edge reduces, and in high-lengthMR, the VBR would not be as high as that of the MR with lowerlengths. For obtaining the superior results, a tradeoff should beconsidered.

Fig. 13. Breakdown voltage variations for the MR-SOI MESFET structureaccording to the MR length by considering the effects of acceptor concentrationand gate work function, at VG = −3 V.

Fig. 14. MR-SOI MESFET drain current alterations against the MR lengthby considering the effects of acceptor concentration and gate work function, atVD = 5 V and VG = 0 V.

Also, as the MR length increases, the depletion region cre-ated by the MR increases too. Thus, by increasing the MRlength, lower ID is achieved. The ID of the MR-SOI MESFETwith various MR lengths is plotted in Fig. 14.

It should be noted that the gate material affects different char-acteristics of the device. According to the following equation,as the ϕm increases, ψbi increases too:

qψbi = q(ϕm − χS). (5)

It leads to the enlargement of the depletion region around thegate and the shortening of the channel opening which resultsin a decrease in the ID. A bigger depletion region results inlower capacitance and higher frequency parameters such as theMAG, maximum oscillation frequency (fmax), and fT . Also,by increasing the ϕm, the electric field in the channel regionincreases that leads to a decrease of the VBR. Also, the NA

affects significantly the device characteristics. By increasing theNA, the ID increases, while the VBR decreases [23], which canbe seen in Figs. 13 and 14.

Regarding to the VBR and the ID figures against the MRlength and by considering the output power density of the de-vice, W = 0.35 μm is determined as the optimum MR length.


Fig. 15. Simulated unilateral power gain, MAG, and current gain of MR-SOIMESFET and C-SOI MESFET structures at VD = 8 V and VG = 0.4 V.

The effects of MR height variations on the VBR, ID, and outpower density of the MR-SOI MESFET structure were alsoinvestigated, and it can be concluded that the MR height doesnot have serious impacts on the parameters.

V. RF RESULTS AND DISCUSSIONS

The existence of the MR in the BOX of the SOI MESFETstructure also affects the RF characteristics of the device.The unilateral power gain (U ), the MAG, and the fT for theMR-SOI MESFET and C-SOI MESFET structures are shownin Fig. 15. The fmax is extracted from the U . According tothe figure, the fmax increases from 84 GHz for the C-SOIMESFET to 98 GHz for the MR-SOI MESFET, at VD = 8 Vand VG = 0.4 V. The same to the fmax, the MAG of theproposed structure increases too. The figure shows that theMAG of the MR-SOI MESFET structure is higher than that ofthe C-SOI MESFET structure. A slight reduction in the fT ofthe MR-SOI MESFET can be seen compared with that of theC-SOI MESFET structure. The fT lowers from 28 GHz for theconventional structure to 25 GHz for the proposed structure.

The expressions for the fT and fmax are as follows[22]–[24]:

fT =gm

2π(CGS + CGD)(6)

fmax =fT

2

√RDS

RG(7)

where CGS is the gate–source capacitance, CGD is the gate–drain capacitance, RDS is the drain–source resistance, and RG

is the gate resistance. The behavior of the fmax is consider-ably more complicated since its value depends on the deviceresistances. Using the MR in the device structure leads to achange in the CGD. The CGD values of the proposed andconventional structures are shown in Fig. 16. It can be clearlyseen that the CGD of the proposed structure is lower than thatof the conventional structure because the MR capacitance isin series to the CGD and it leads to lower total capacitancebetween the gate and drain. Also, utilizing the MR in the BOXof the proposed structure causes an extra depletion region inthe channel which makes a reduction in the gm of the device.The simulated frequency characteristics show that the fT ofthe proposed structure is lower than that of the conventional

Fig. 16. Comparison of the gate–drain capacitances for the MR-SOI MESFETand C-SOI MESFET at VD = 8 V and f = 10 GHz.

structure. According to (6), it means that, in the proposed struc-ture, the reduction of the gm is bigger than the fall of the CGD.The increase of the fmax is attributed to the large (RDS/RG)ratio of the MR-SOI MESFET structure. The ID of theMR-SOI MESFET is lower compared with that of the C-SOIMESFET structure. It means that the RDS of the proposedstructure is larger than that of the conventional structure. It leadsto an increase of the (RDS/RG) ratio, which occurs to enhancethe fmax. Although the fT of the MR-SOI MESFET structureis a little smaller than that of the C-SOI MESFET structure, ithas no serious impact on its application for RF power.

VI. CONCLUSION

DC and RF characteristics of a novel SOI MESFET withmodified charge distribution have been analyzed by 2-D nu-merical simulation. Modified charge distribution lowers electricfield crowding around the gate and improves breakdown voltage(VBR). In order to modify the charge distribution, an MR islocated in BOX. The MR-SOI MESFET results are comparedwith C-SOI MESFET characteristics. The VBR of the proposedstructure is enhanced significantly by 116% compared withthat of the C-SOI MESFET structure. A small reduction indrain current of the proposed structure occurs, but it has noserious impact on the goal of getting a high-power device.The maximum output power density of the MR-SOI MESFETstructure increases meaningfully by 126% compared with thatof the C-SOI MESFET structure. Also, the maximum oscilla-tion frequency and MAG of the proposed structure improve incomparison with those of the conventional structure. Therefore,the MR-SOI MESFET structure has excellent electrical perfor-mances compared with the C-SOI MESFET structure, and itcan be taken into consideration for high-power and high-speedapplications.

ACKNOWLEDGMENT

The authors would like to thank Mr. A. Abbasi for hisguidance in analyzing the device structure.


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Amirhossein Aminbeidokhti was born in Semnan,Iran, in 1987. He received the B.S. and M.S. degrees(with first-class honors) in electronic engineeringfrom Semnan University, Semnan, in 2009 and 2011,respectively.

He is currently with the Department of ElectricalEngineering, Semnan University. His research inter-ests include modeling, analysis, and characterizationof novel silicon-on-insulator devices, IV- and III–V-based structures, power devices, and nano-CMOS.

Ali A. Orouji (M’05) was born in Neyshabour, Iran,in 1966. He received the B.S. and M.S. degreesin electronic engineering from Iran University ofScience and Technology, Tehran, Iran, in 1989 and1992, respectively, and the Ph.D. degree from theIndian Institute of Technology Delhi, Delhi, India,in 2006.

Since 1992, he has been a Faculty Member withSemnan University, Semnan, Iran. His research in-terests are in modeling of silicon-on-insulator metal–oxide–semiconductor field-effect transistors, novel

device structures, and analog integrated circuit design.

Soude Rahmaninezhad was born in Esfahan, Iran,in 1984. She received the B.S. degree in electronicengineering from the Sepahan Private Higher Educa-tion Institute of Science and Technology, Esfahan, in2009 and the M.S. degree in electronic engineeringfrom Semnan University, Semnan, Iran, in 2012,respectively.

She is currently with the Department of Electri-cal Engineering, Semnan University. Her researchinterests are in modeling and characterization ofnovel structure in silicon-on-insulator metal–oxide–

semiconductor field-effect transistors.

Masoomeh Ghasemian was born in Bojnurd, Iran,in 1982. She received the M.S. degree in electronicengineering from Semnan University, Semnan, Iran,in 2012.

She is currently with the Department of Electri-cal Engineering, Semnan University. Her researchinterests include the modeling and characterizationof novel structure in silicon-on-insulator metal–semiconductor field-effect transistors (MESFETs),silicon carbide MESFETs, and power devices.

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