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Research on Analysis and Physical
SynthesisChung-Kuan Cheng
CSE DepartmentUC San Diegokuan@cs.ucsd.edu
Outlines Analysis (Signal Integrity)
SPICEDiego
RLC Reduction Synthesis (Interconnect Dominant)
Networks on Chip Clock Distribution Floorplanning Datapath
Packaging (High Performance)
Analysis: SPICE Large netlist, e.g. 100M
transistors, 5G Hz Strong Coupling: interconnect
delay, crosstalk, voltage drop, ground bounce
Process Variations Short Channel Devices
Why SPICEDiego is better? SPICEDiego: fast accurate transistor level circuit
simulator Powerful Matrix Solver Engine Transistor devices. Capable of capturing coupling effects. Device Model including Miller’s effect Less Memory Requirement (no LU factorization, dose
not save matrix for transistors) Application
interconnect delay Crosstalk voltage drop, ground bounce simultaneous switching noise
Experimental Results
chip
board
Power Supply
Test Case Board / Packaging / Chip Power Network Fully coupled packaging inductance 60k elements, 5000 nodes. Spice failed
Our tool Less than 10 minutes
Synthesis: Clock Distribution
Process variations causes significant amount of clock skew
Working frequency keeps increasing, skew accounts for large portion of clock period
Mesh is effective to reduce skew There is no theoretical design
guide line for mesh structure
State-of-the-art In Engineering practice, very deep
balanced buffer tree + mesh is widely adopted for global clock distribution IBM Power 4: 64 by 64 grid at the bottom of
an H-tree Intel IA: clock stripe at the bottom of a
buffer tree. “Skew Averaging”: shunt at different levels
“Skew Averaging Factor” determined by simulation. No guideline for routing resource planning known yet
Clock Mesh Example (1) DEC Alpha 21264
Clock Mesh Example (2) IBM Power4
H-tree drives one domain clock mesh 8x8 area buffers
Clock Mesh Example (3) Intel Pentium 4
Tree drives three spines
Our Contributions and On-going Efforts
Contribution: Analytical skew expression using R,C
model Proposed generalized multi-level mesh
network structure for skew reduction Optimal allocation of routing resources
among meshes
On-going Study: More accurate R,L,C delay model Signal propagation on a uniform mesh
Multi-level mesh structure
Skew on mesh Skew expression
)/exp( RkRTT s
Vs11
R1
R
VSNN
VS1N
VSN1
C1
Optimization
Skew function
Multi level skew function
)/exp( RkRTT s
)'exp()'exp( wkTwRkTT s
Awl
eTTeTeTTn
iii
wkn
wkwk nn
1
321
:s.t.
))...))((( :Min 2211
Die size 1cm by 1cm 100nm copper technology Ground Shielded Differential Signal
Wires for Global Clock Distribution
Routing area is normalized to the area of a 16 by 16 mesh with minimal wire width
Clock Design Settings
+ -GND
GND
Delay Surfaces
Robustness Against Supply Voltage Variations
ave worst ave worst0.00 2.10E-11 2.91E-11 2.10E-11 2.91E-111.00 8.38E-12 1.14E-11 8.26E-12 1.43E-112.00 2.71E-12 4.42E-12 6.18E-12 1.11E-113.00 1.89E-12 3.33E-12 4.83E-12 8.73E-124.00 1.45E-12 2.48E-12 3.88E-12 6.96E-125.00 1.16E-12 2.02E-12 3.18E-12 5.64E-12
total areamutli-level mesh single-level mesh
Y Architecture Chip-Package Breakaway
Packaging
Grids of X and Y Architectures
(http://www.xinitiative.org/img/062102forum.pdf)
X-Architecture Y-Architecture
Clock Tree on Square Mesh N-level clock tree:
path length 21% less than H-
tree total wire length 9% less than H
tree, 3% less than X tree
No self-overlapping between parallel wire segments
Chip to Package Breakaway
Manhattan Architecture
Y Architecture
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Row by row ComparisonIndent Two sides
Chip-Package Breakaways
Conclusion Analysis: Signal Integrity Synthesis: Interconnect Dominant Packaging: Performance
Goals: Performance, CostResources: Physical SpaceConstraints: Yield, Signal Integrity
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