MIPS with Pipelining - Weber State Universityfaculty.weber.edu/snaik/ECE3610/14Lec14.pdf · MIPS...

EE 3610 Digital Systems Suketu Naik

MIPS with

Pipelining

EE 3610: Digital Systems

2MIPS: Application

The MIPS is used in

Embedded systems,

Cisco routers

Nintendo 64

Sony PlayStation , Sony PlayStation 2

and Sony PlayStation Portable

Small computing devices

Small consumer electronics and

appliances

Google's Honeycomb (Android 3)

tablet

3MIPS Controller: Sequential

Decode

Execute

Writeback

Memory

__/load_pc and

write reg_file

opcode=beq

or opcode

bne/load_pc

opcode=jr or j

/load_pc opcode≠jr /_

opcode=jw

or sw /_

opcode=sw/mem_

write and load_pc

Fetch:

PC outputs to memory

Instruction is loaded at the end of the state

Decode: Registers accessed

Execute: ALU computes the result

opcode≠sw/_

4MIPS: Five Stages

5MIPS: Five Stages

(1) IF: instruction fetch

(2) ID: instruction decode and register read

(3) EX: ALU execution

(4) MEM: data memory read or write

(5) WB: write result back into a register

6MIPS: Stage One

(1) IF: instruction fetchFetch the current instruction from memory using

the Program Counter (PC) as the address-add 4 to the PC (MIPS instruction=32 bits=4 bytes)

-and store new address as NPC

PC is a register that

contains the memory

address of the next

instruction

7MIPS: Stage One

Q: Why does PC have to be incremented by 4?

A: PC points (contains) to the first byte of the

instruction; each instruction is 4 byes (32 bits)

(2) ID: instruction decode and register read

-Determine which instruction is given

-Fetch the register values

(2 registers in MIPS

instruction set)

-Compare the two

registers and set

the EQUAL flag

if equal

MIPS: Stage Two

MIPS Instruction Formats

MIPS: Stage Two

- Memory reference: add the base register and the

offset to form the effective address

- Register-Register instruction: add, multiply,

logic operation

- Register-Immediate

instruction: add,

multiply, logic

operation on first

register and the

immediate value

MIPS: Stage Three

- LOAD or STORE: access memory

- BRANCH: update the PC using either PC or the

output of the ALU operation

- Otherwise do nothing

MIPS: Stage Four

Q: Why do we need Memory in MIPS?

https://www.youtube.com/watch?v=rZev35tJaEY

(5) WB: - write results back into an appropriate register

MIPS: Stage Five

13Example: add $s0, $s1, $s2

14Example: lw $t2, 16($s0)

Load will take the data from memory and put it into the register file

Store will take the data from register file and put it into the memory

PIPELINING

16Pipelining: examples

Laundry

Wash Dry Fold Clothes Put Away

Serial

Pipelined

17Pipelining: examples

Factory Assembly Line

Good Pipelining: Kia Sportage Assembly Line

Bad Pipelining: Chaplin: Modern Times

18PIPELINING: Why do we care?

Serial Microprocessor:

Executes n instructions using s number of stages

in ns clock periods

Total Execution Time = ns

Pipelined Microprocessor:

Executes n instructions using s number of stages

Total Execution Time = s + (n ─ 1)

Examples:

n=30, s=5

Serial Microprocessor 150 clock cycles

Pipelined Microprocessor 5+29=34 clock cycles

19MIPS: Five Stages with Pipeline Registers

20MIPS: Five Stages with Pipeline Registers

Inter-stage registers are master-slave D flip-flops; the master receives new data from the

previous stage of the instruction while the slave flip-flop provides data to the next stage

21Master Slave D-Flipflop

22MIPS: Five Stages with Pipeline Registers(1) IF: instruction fetch

IF/ID Register

(2) ID/RF: instruction decode and register fetch

ID/EX Register

EX/MEM Register

MEM/WB Register

(5) WB: write result back into a register

23MIPS Pipline Execution

24Pipelining: Without Controller

25Pipelining: With Controller

26Pipelining: With Controller

Controller is necessary to switch operations within and

between stages

Control information must be carried as a part of the

instruction, since this information is required at different

stages of the pipeline

This can be done by adding more inter-stage storage

register bits to forward control data yet to be used

27MIPS Pipelining: Example Program*

Assembly Code Operation

lw $10, 20($1) $10=$1 + 20

sub $11, $2, $3 $11=$2 - $3

and $12, $4, $5 $12=$4 and $5

or $13, $6, $7 $13=$6 or $7

add $14, $8, $9 $14=$8 + $9

*Ref: Dodge, "Lecture 20: The PIPELINED MIPS PROCESSOR", UT Dallas, 2012

28MIPS Pipelining: Idle

29MIPS Pipelining: lw $10, 20($1)

30MIPS Pipelining: sub $11, $2, $3

31MIPS Pipelining: and $12, $4, $5

32MIPS Pipelining: or $13, $6, $7

33MIPS Pipelining: add $14, $8, $9

34MIPS Pipelining: Processing

38MIPS Pipelining: Idle

39MIPS Pipelining: Summary Pipelining replaces the serial

processor with a row of five

'mini-processors', each capable

of completing one part of each

instruction

A new instruction is started every

clock cycle

Inter-process registers store instruction information (data, write

register, branch conditions) between cycles so that the instructions

are passed between the pipeline stages

When the pipeline is filled with instructions, an instruction

completes every clock cycle

Hazards

Pipelining

41MIPS Pipelining: Hazards Hazards occur because data required for executing the

current instruction may not be available

Example:

An instruction in the FETCH cycle

may need data from a register whose value will be changed by an

instruction elsewhere but still in process in the pipeline: e.g. EX,

MEM, or WB cycle)

So FETCH instruction could

access a register and

get incorrect data because

the register data has not

yet been updated by other

instruction(s)

42MIPS Pipelining: Types of HazardsTwo Types of Hazards

Data Hazard

Data hazards occur when an instruction needs register contents

for an arithmetic/ logical/memory instruction

Control Hazard

Control hazards occur when a branch instruction is pending and

the data necessary to initiate/bypass the branch is not yet available

in the same sort of scenario

Both occur because an instruction in the ID/RF stage of the

MIPS pipeline needs register data that will be shortly updated

by instructions in the EX or MEM/Bypass, or WB stage

43Data Hazards: Example1

Here, last four instructions require data from $2, which is changed

in the first instruction

data in $2 will not be rewritten until cycle 4, so the AND (2nd

instruction) and OR (3rd instruction) will fetch incorrect data from

ADD may not get correct information

SW will be correct

44Data Hazards: Example2

lw $1, 4($2) IF ID EX MEM WB

add $3, $1,$4 IF ID EX MEM WB

Load will take the data from memory and put it into the register file

Store will take the data from register file and put it into the memory

“Take the contents of $2 from the register file, add 4 to it, access the memory at

that location, then move the data at that location into $1 in the register file”

45Solution: Stalling

One solution is in insert bubbles

This means delaying certain operation in the pipeline

Another solution may require modification in the datapath,

which will raise the hardware cost

Hazards slow down the instruction execution speed

An alternative approach to deal with this is for the compiler

(or the assembler) to insert NOP instructions, or reorder the

instructions

lw $1, 4($2) IF ID EX MEM WB

add $3, $1,$4 IF nop nop nop ID

46Hazard and Solution: Example

Problem 14 Practice Test

MIPS with Pipelining - Weber State Universityfaculty.weber.edu/snaik/ECE3610/14Lec14.pdf · MIPS...

Documents

MIPS Processor · PDF fileDesign of Pipelined MIPS Processor Sept. 24 & 26, 1997 Topics • Instruction processing • Principles of pipelining • Inserting pipe registers • Data

Electrical and Computer Engineering University of Cyprus 22-10-2014 LAB3: IMPROVING MIPS PERFORMANCE WITH PIPELINING

Concetti di base del PIPELININGgunetti/DIDATTICA/architettureII/02-pipeline-1.pdf · 9 L’architettura MIPS pipelined • Sulla schematizzazione del pipelining del lucido precedente

MIPS In-Order Single-Issue Integer Pipeline Performance of ...meseec.ce.rit.edu/cmpe550-fall2014/550-8-27-2014.pdf · • Instruction Pipelining Review: – MIPS In-Order Single-Issue

Execution Cycle. Outline (Brief) Review of MIPS Microarchitecture Execution Cycle Pipelining Big vs. Little Endian-ness CPU Execution Time 1 IF ID EX

CSE431 L06 Basic MIPS Pipelining.1Irwin, PSU, 2005 CSE 431 Computer Architecture Fall 2005 Lecture 06: Basic MIPS Pipelining Review Mary Jane Irwin ( mji

Basic Pipelining & MIPS Pipelining Chapter 6 [Computer Organization and Design, © 2007 Patterson (UCB) & Hennessy (Stanford), & Slides Adapted from: Mary

Pipelining the CPU - Edward · PDF filePipelining the CPU ... The MIPS Pipeline The MIPS pipeline design is based on the five–step instruction execution discussed in the previous

MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle

CSIE30300 Computer Architecture Unit 04: Basic MIPS Pipelining Hsin-Chou Chi [Adapted from material by Patterson@UCB and Irwin@PSU]

Pipelining the MIPS Datapath - CS 233 · Pipelining the MIPS Datapath Today: Pipelining Monday: Forwarding values in the pipeline Wednesday: Exam 4 review session (optional) Friday:

What is pipelining? How is the pipelining Implemented ... implementation Data Path for R-instruction. ... Multiple Cycle MIPS CPU. Feb.2008_jxh_Introduction ComputerArchitecture_pipeline

CSE 490/590, Spring 2011 CSE 490/590 Computer Architecture MIPS Review & Pipelining I Steve Ko Computer Sciences and Engineering University at Buffalo

Instructor: Justin Hsia CS 61C: Great Ideas in Computer Architecture MIPS CPU Control, Pipelining 7/24/20121Summer 2012 -- Lecture #21

The Big Picture - University Of Maryland · Appendix A - Pipelining 11 MIPS Functions What Is Pipelining Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute

PIPELINING basics - · PIPELINING basics • A pipelined architecture for MIPS • Hurdles in pipelining • Simple solutions to pipelining hurdles • Advanced pipelining

Pipelining the MIPS Datapath - GitHub Pages · Today’s lecture Pipeline implementation Single-cycle Datapath Pipelining performance Pipelined datapath Example. Refresher: The Full

CSF 333/433 Computer Architecture Fall 2008 MIPS Pipeliningjorgev/cs333/readings/CSF-mips-pipeline.pdf · 2009. 6. 20. · Computer Architecture Fall 2008 MIPS Pipelining . CSF MIPS

MIPS with Pipelining · MIPS: Five Stages with Pipeline Registers 20 Inter-stage registers are master-slave D flip-flops; the master receives new data from the previous stage of the

Lecture 6: Pipelining MIPS R4000 and More Kai Bu kaibu@zju.edu.cn