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CSF MIPS Pipelining
CSF 333/433 Computer Architecture
Fall 2008
MIPS Pipelining
CSF MIPS Pipelining
Review: Single Cycle vs. Multiple Cycle Timing
Clk Cycle 1
Multiple Cycle Implementation:
IFetch Dec Exec Mem WB
Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10
IFetch Dec Exec Mem lw sw
IFetch R-type
Clk
Single Cycle Implementation:
lw sw Waste
Cycle 1 Cycle 2
multicycle clock slower than 1/5th of single cycle clock due to stage register overhead
CSF MIPS Pipelining
How Can We Make It Even Faster? Split the multiple instruction cycle into smaller and
smaller steps There is a point of diminishing returns where as much time is
spent loading the state registers as doing the work
Start fetching and executing the next instruction before the current one has completed Pipelining – (all?) modern processors are pipelined for
performance
Remember the performance equation: CPU time = CPI * CC * IC
Fetch (and execute) more than one instruction at a time Superscalar processing – stay tuned
CSF MIPS Pipelining
A Pipelined MIPS Processor Start the next instruction before the current one has
completed improves throughput - total amount of work done in a given time instruction latency (execution time, delay time, response time -
time from the start of an instruction to its completion) is not reduced
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
IFetch Dec Exec Mem WB lw
Cycle 7 Cycle 6 Cycle 8
sw IFetch Dec Exec Mem WB
R-type IFetch Dec Exec Mem WB
- clock cycle (pipeline stage time) is limited by the slowest stage - for some instructions, some stages are wasted cycles
CSF MIPS Pipelining
Single Cycle, Multiple Cycle, vs. Pipeline
Multiple Cycle Implementation:
Clk
Cycle 1
IFetch Dec Exec Mem WB
Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10
IFetch Dec Exec Mem lw sw
IFetch R-type
lw IFetch Dec Exec Mem WB
Pipeline Implementation:
IFetch Dec Exec Mem WB sw
IFetch Dec Exec Mem WB R-type
Clk
Single Cycle Implementation:
lw sw Waste
Cycle 1 Cycle 2
CSF MIPS Pipelining
MIPS Pipeline Datapath Modifications What do we need to add/modify in our MIPS datapath?
State registers between each pipeline stage to isolate them
Read Address
Instruction Memory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
16 32
ALU
Shift left 2
Add
Data Memory
Address
Write Data
Read Data IF
etch
/Dec
Dec
/Exe
c
Exec
/Mem
Mem
/WB
IF:IFetch ID:Dec EX:Execute MEM: MemAccess
WB: WriteBack
System Clock
Sign Extend
CSF MIPS Pipelining
Pipelining the MIPS ISA What makes it easy
all instructions are the same length (32 bits) - can fetch in the 1st stage and decode in the 2nd stage
few instruction formats (three) with symmetry across formats - can begin reading register file in 2nd stage
memory operations can occur only in loads and stores - can use the execute stage to calculate memory addresses
each MIPS instruction writes at most one result (i.e., changes the machine state) and does so near the end of the pipeline (MEM and WB)
What makes it hard structural hazards: what if we had only one memory? control hazards: what about branches? data hazards: what if an instruction’s input operands depend
on the output of a previous instruction?
CSF MIPS Pipelining
Graphically Representing MIPS Pipeline
Can help with answering questions like: How many cycles does it take to execute this code? What is the ALU doing during cycle 4? Is there a hazard, why does it occur, and how can it be fixed?
ALU
IM Reg DM Reg
CSF MIPS Pipelining
Why Pipeline? For Performance!
I n s t r.
O r d e r
Time (clock cycles)
Inst 0
Inst 1
Inst 2
Inst 4
Inst 3
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg A
LU
IM Reg DM Reg
ALU
IM Reg DM Reg
Once the pipeline is full, one instruction
is completed every cycle, so
CPI = 1
Time to fill the pipeline
CSF MIPS Pipelining
Can Pipelining Get Us Into Trouble? Yes: Pipeline Hazards
structural hazards: attempt to use the same resource by two different instructions at the same time
data hazards: attempt to use data before it is ready - An instruction’s source operand(s) are produced by a prior
instruction still in the pipeline
control hazards: attempt to make a decision about program control flow before the condition has been evaluated and the new PC target address calculated
- branch instructions
Can always resolve hazards by waiting pipeline control must detect the hazard and take action to resolve hazards
CSF MIPS Pipelining
I n s t r.
O r d e r
Time (clock cycles)
lw
Inst 1
Inst 2
Inst 4
Inst 3
ALU
Mem Reg Mem Reg
ALU
Mem Reg Mem Reg
ALU
Mem Reg Mem Reg A
LU
Mem Reg Mem Reg
ALU
Mem Reg Mem Reg
A Single Memory Would Be a Structural Hazard
Reading data from memory
Reading instruction from memory
Fix with separate instr and data memories (I$ and D$)
CSF MIPS Pipelining
How About Register File Access?
I n s t r.
O r d e r
Time (clock cycles)
add $1,
Inst 1
Inst 2
add $2,$1,
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
CSF MIPS Pipelining
How About Register File Access?
I n s t r.
O r d e r
Time (clock cycles)
Inst 1
Inst 2
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg A
LU
IM Reg DM Reg
Fix register file access hazard by doing reads in the second half of the cycle and writes in
the first half
add $1,
add $2,$1,
clock edge that controls register writing
clock edge that controls loading of pipeline state registers
CSF MIPS Pipelining
Register Usage Can Cause Data Hazards
I n s t r.
O r d e r
add $1,
sub $4,$1,$5
and $6,$1,$7
xor $4,$1,$5
or $8,$1,$9 A
LU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
Dependencies backward in time cause hazards
Read before write data hazard
CSF MIPS Pipelining
Register Usage Can Cause Data Hazards
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
Dependencies backward in time cause hazards
add $1,
sub $4,$1,$5
and $6,$1,$7
xor $4,$1,$5
or $8,$1,$9
Read before write data hazard
CSF MIPS Pipelining
Loads Can Cause Data Hazards
I n s t r.
O r d e r
lw $1,4($2)
sub $4,$1,$5
and $6,$1,$7
xor $4,$1,$5
or $8,$1,$9 A
LU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
Dependencies backward in time cause hazards
Load-use data hazard
CSF MIPS Pipelining
stall
stall
One Way to “Fix” a Data Hazard
I n s t r.
O r d e r
add $1,
ALU
IM Reg DM Reg
sub $4,$1,$5
and $6,$1,$7
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
Can fix data hazard by
waiting – stall – but impacts
CPI
CSF MIPS Pipelining
Another Way to “Fix” a Data Hazard
I n s t r.
O r d e r
add $1,
ALU
IM Reg DM Reg
sub $4,$1,$5
and $6,$1,$7 A
LU
IM Reg DM Reg
ALU
IM Reg DM Reg
Fix data hazards by forwarding results as soon
as they are available to
where they are needed
xor $4,$1,$5
or $8,$1,$9
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
CSF MIPS Pipelining
Another Way to “Fix” a Data Hazard
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
Fix data hazards by forwarding results as soon
as they are available to
where they are needed
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
I n s t r.
O r d e r
add $1,
sub $4,$1,$5
and $6,$1,$7
xor $4,$1,$5
or $8,$1,$9
CSF MIPS Pipelining
Forwarding with Load-use Data Hazards
I n s t r.
O r d e r
lw $1,4($2)
sub $4,$1,$5
and $6,$1,$7
xor $4,$1,$5
or $8,$1,$9 A
LU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
CSF MIPS Pipelining
Forwarding with Load-use Data Hazards
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
Will still need one stall cycle even with forwarding
I n s t r.
O r d e r
lw $1,4($2)
sub $4,$1,$5
and $6,$1,$7
xor $4,$1,$5
or $8,$1,$9
CSF MIPS Pipelining
Branch Instructions Cause Control Hazards
I n s t r.
O r d e r
lw
Inst 4
Inst 3
beq
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
ALU
IM Reg DM Reg
Dependencies backward in time cause hazards
CSF MIPS Pipelining
stall
stall
stall
One Way to “Fix” a Control Hazard
I n s t r.
O r d e r
beq
ALU
IM Reg DM Reg
lw
ALU
IM Reg DM Reg
ALU
Inst 3 IM Reg DM
Fix branch hazard by waiting –
stall – but affects CPI
CSF MIPS Pipelining
Corrected Datapath to Save RegWrite Addr Need to preserve the destination register address in the
pipeline state registers
Read Address
Instruction Memory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
16 32
ALU
Shift left 2
Add
Data Memory
Address
Write Data
Read Data
IF/ID
Sign Extend
ID/EX EX/MEM
MEM/WB
CSF MIPS Pipelining
Corrected Datapath to Save RegWrite Addr Need to preserve the destination register address in the
pipeline state registers
Read Address
Instruction Memory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
16 32
ALU
Shift left 2
Add
Data Memory
Address
Write Data
Read Data
IF/ID
Sign Extend
ID/EX EX/MEM
MEM/WB
CSF MIPS Pipelining
MIPS Pipeline Control Path Modifications All control signals can be determined during Decode
and held in the state registers between pipeline stages
Read Address
Instruction Memory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
16 32
ALU
Shift left 2
Add
Data Memory
Address
Write Data
Read Data
IF/ID
Sign Extend
ID/EX EX/MEM
MEM/WB
Control
CSF MIPS Pipelining
Other Pipeline Structures Are Possible What about the (slow) multiply operation?
Make the clock twice as slow or … let it take two cycles (since it doesn’t use the DM stage)
ALU
IM Reg DM Reg
MUL
ALU
IM Reg DM1 Reg DM2
What if the data memory access is twice as slow as the instruction memory? make the clock twice as slow or … let data memory access take two cycles (and keep the same
clock rate)
CSF MIPS Pipelining
Sample Pipeline Alternatives ARM7
StrongARM-1
XScale
ALU
IM1 IM2 DM1 Reg DM2
IM Reg EX
PC update IM access
decode reg access
ALU op DM access shift/rotate commit result (write back)
ALU
IM Reg DM Reg
Reg SHFT
PC update BTB access
start IM access
IM access
decode reg 1 access
shift/rotate reg 2 access
ALU op
start DM access exception
DM write reg write
CSF MIPS Pipelining
Summary All modern day processors use pipelining Pipelining doesn’t help latency of single task, it helps
throughput of entire workload Potential speedup: a CPI of 1 and fast a CC Pipeline rate limited by slowest pipeline stage
Unbalanced pipe stages makes for inefficiencies The time to “fill” pipeline and time to “drain” it can impact
speedup for deep pipelines and short code runs
Must detect and resolve hazards Stalling negatively affects CPI (makes CPI less than the ideal
of 1)
