Execution Cycle. Outline (Brief) Review of MIPS Microarchitecture Execution Cycle Pipelining Big vs. Little Endian-ness CPU Execution Time 1 IF ID EX

Execution Cycle

2

Outline

• (Brief) Review of MIPS Microarchitecture• Execution Cycle• Pipelining• Big vs. Little Endian-ness• CPU Execution Time

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

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MIPS Microarchitecture

• Recall the datapath for the lw (load word) command

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• The first step was to fetch the instruction

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• fetch the instruction

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• The next step was to decode the instruction

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• decode the instruction

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• Next, execute the instruction

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• execute the instruction

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• Next, access memory (if necessary)

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• Finally, write back to a register

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• write back to a register

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• Just described classic 5-stage execution cycle• Fetch• Decode• Execute• Memory• Write Back

• 5-stage execution cycle typical of RISC machines• RISC is easier to explain• CISC is more complicated…

• x86 is CISC

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Outline


IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

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Execution Cycle (aka Instruction Cycle)

IF – Instruction Fetch

ID – Instruction Decode

EX - Execute

MEM – Memory

WB- Write Back

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Execution Cycle - Fetch

IF

ID

EXE

MEM

WB

• Send the program counter (PC) to memory • fetch the current instruction from memory• Update the PC

• PC = PC + 4• (since each instruction is four bytes)

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Execution Cycle - Decode

IF

ID

EXE

MEM

WB

• Figure out type of instruction (e.g., load, add, etc.)• Based on “opcode”

• Determine registers involved• aka “operands”

• Get things “setup” for execution• Control Unit sets appropriate pins

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Execution Cycle - Execute

IF

ID

EXE

MEM

WB

• ALU operates on operands prepared during decode

• ALU performs function based on instruction type• Arithmetic (add, subtract, …)• Logic (equivalence, negation, …)

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Execution Cycle - Memory

IF

ID

EXE

MEM

WB

• If instruction is LOAD, • Read data from effective memory address • Effective memory address computed during EXE

• If instruction is STORE,• Write data from register to effective memory address• Effective memory address computed during EXE

• MEM is an OPTIONAL execution stage• Memory access does not always occur

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Execution Cycle – Write Back

IF

ID

EXE

MEM

WB

• Write results “back” to a register• Result type depends on instruction

• Results could be from:• ALU computation

-or-• Memory access (i.e., load)

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Execution Cycle – Fetch

• The execution cycle then repeats…

• The next instruction is already indicated by PC• Recall that PC set to PC + 4 during previous fetch

IF

ID

EXE

MEM

WB

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Outline


IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

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Pipelining

• It’s laundry day, and you have to complete the following tasks:

1. Wash white clothes in washing machine2. Dry white clothes in dryer3. Wash color clothes in washing machine4. Dry color clothes in dryer5. Wash athletic clothes in washing machine6. Dry athletic clothes in dryer

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Pipelining

• Would you do the following?• I.e., Wait for each load to wash and dry before starting next?

wash white

s

dry white

s

wash color

s

dry color

s

wash athletic

dry athletic

time

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Pipelining

• Heck no!!• What a waste of time!!• What do you do instead?

wash white

s

dry white

s

wash color

s

dry color

s

wash athletic

dry athletic

time

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Pipelining

• Overlap: wash one load while another is drying

wash white

s

dry white

s

wash color

s

dry color

s

wash athletic

dry athletic

time

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Pipelining

• Do more things at once…

wash white

s

dry white

s

wash color

s

dry color

s

wash athletic

dry athletic

time

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Pipelining

• Complete tasks in less time…

FREE TIME!!

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Pipelining

• Can this be applied to the execution cycle?• Yes!!

• Fetch the next instruction while decoding the current instruction?

• Decode the next instruction while executing the current instruction?

• …

IF ID EX MEM WB

IF ID EX MEM WB

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Pipelining

• Typical 5-stage pipeline of RISC CPU• 5th instruction is being fetched while 1st instruction is being written back

• There are much deeper and fancier pipelines…

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

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Pipelining

• Typical 5-stage pipeline of RISC CPU• 9 clock cycles to complete 5 instructions

clock cycle

Instruction 1 2 3 4 5 6 7 8 9

instr-1 IF

ID

EXE

MEM WB

instr-2 IF ID EXE MEM WB



instr-5 IF ID EXE MEM

WB

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Pipelining

• Without pipelining• 25 clock cycles to complete 5 instructions

IF ID EX MEM WB IF ID EX MEM WB…

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Pipelining

• There are several things that can disrupt a pipeline• Called hazards

• E.g., What happens if the next instruction depends on the result of the current instruction?

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Pipeline Hazards

• Three types of hazards• Control hazard• Data hazard• Structural hazard

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Pipeline Hazards: Control

• Control Hazard• Occurs when pipelining branches (e.g., if statements)• … or other instructions that change the PC

???

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Pipeline Hazards: Data

• Data Hazard• Occurs when an instruction tries to use data before it’s available• For example:

1: R1 <- R2 + R32: R4 <- R1 + R5

• Contents in R1 (register 1) may have been loaded for instruction #2 before instruction #1 has finished.

• Several types of data hazards…

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Pipeline Hazards: Data

• Data Hazard1: R1 <- R2 + R32: R4 <- R1 + R5

IF ID EX MEM WB

IF ID EX MEM WB

1:

2:

R1 used in instruction #2’s execution before instruction #1 writes back

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Pipeline Hazards: Structural

• Structural Hazard• Occurs when one hardware component is needed by two (pipelined)

tasks at same time

• Example: read from and write to memory at the same time• Fetch an instruction from memory while writing data to memory

• Hence why instruction and data memory are separated

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Pipelining: Solutions

• Ways to minimize pipeline hazards• Stall• Flush• Out-of-order execution• Forwarding• Bypassing• Branch prediction• …

• Beyond the scope of this course…• Learn about / master pipeline hazards

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Break Time!!!

I don’t fish, but this likes nice…

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Outline


IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

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Big vs. Little Endian

• Some important jargon:

0x97 46 AB 07

1001 0111 0100 0110 1010 1011 0000 0111

MSB: Most

Significant Bit

LSB: Least

Significant Bit

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0x97 46 AB 07

1001 0111 0100 0110 1010 1011 0000 0111

Most Significant Byte

Least Significant Byte

MSB can stand for most significant bit OR byte

LSB can stand for least significant bit OR byte

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• Endian refers to the ordering of bytes for multiple byte words• How the bytes are stored in memory • How the bytes are interpreted

• Whether the MSB comes “first” or “last”

• Whether the LSB comes “first” or “last”

MSB - Most Significant ByteLSB - Least Significant Byte

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Big Endian

• Most significant byte stored at smallest address• Least significant byte stored at largest address

0x97 46 AB 07addres

s byte

1000 97

1001 46

1002 AB

1003 07

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Little Endian

• Most significant byte stored at largest address• Least significant byte stored at smallest address

0x97 46 AB 07addres

s byte

1000 07

1001 AB

1002 46

1003 97

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Example

• Store 0x46 A0 B7 FF using:

address byte

1274

1275

1276

1277

address byte

1274

1275

1276

1277

Big Endian Little Endian

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Example

• Store 0x46 A0 B7 FF using:

address byte

1274 46

1275 A0

1276 B7

1277 FF

address byte

1274 FF

1275 B7

1276 A0

1277 46

Big Endian Little Endian

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Outline


IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

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CPU Execution Time

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Example

• What is the execution time required to complete: • 10 instructions• with 5 cycles per instruction• using a 100 Hz CPU?

• Hz = cycles / second

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Example

• 10 instructions• 5 cycles per instruction• 100 Hz CPU = 100 cycles per second = 1 second per 100 cycles

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Next Time..

• Review for midterm

• Bring your laptop (if you can)• Linux bootstrap day

• Install VMWare onto your computer• Will need very soon!!

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Execution Cycle. Outline (Brief) Review of MIPS Microarchitecture Execution Cycle Pipelining Big vs. Little Endian-ness CPU Execution Time 1 IF ID EX