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Modeling Methodologies for Dynamic Reconfigurable Systems
Thesis Defense - May 2008
Fabio Cancare
Thesis Committee:
Tanya Berger-Wolf, Shantanu Dutt (Chair), Donatella Sciuto
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RationaleRationale
Dynamic reconfiguration is a new and promising technique, it can be applied to cope with:
Lack of available resourcesSystem adaptabilitySystem reliability
Main drawback: implementing DR systems is a complex and time-consuming taskModel-based design paradigm allow the fast development of complex architecture
Understand how it is possible to exploit the model-design paradigm in dynamic reconfigurable system
implementation
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Innovative ContributionInnovative Contribution
Outline a model-based design flow for implementing large designs onto FPGAs with limited available resources
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Useful NoveltiesUseful Novelties
Development of SysGen, a tool automating a portion of the low-level implementation phase
Implementation of a real-world application demanding for Dynamic Reconfigurable to enhance its perfomance
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OutlineOutline
Fundamental ConceptsProposed Flow
High-level Modeling PhaseLow-level Implementation Phase
Case StudyResultsConclusions and follows-up
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OutlineOutline
Fundamental ConceptsProposed Flow
High-level Modeling PhaseLow-level Implementation Phase
Case StudyResultsConclusions and follows-up
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Reconfigurable ComputingReconfigurable Computing
“Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher
performance than software, while maintaining a higher level of flexibility than hardware”
(K. Compton and S. Hauck, Reconfigurable Computing: a Survey of Systems and Software, 2002)
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Reasons BehindReasons Behind
Applications often require performance which cannot be achieved by software
Applications often require to be flexible, modifiable, adaptable. Traditional hardware cannot achieve such results
Reconfigurable ComputingReconfigurable Computing techiniques are able to alter a concrete architecture once it has been deployed onto a high-performance device, in order to meet:
Resources constraintsAdaptability constraintsReliability constraints
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Reconfigurable Computing TechniquesReconfigurable Computing Techniques
Targeted devices: PLDs (Programmable Logic Devices)
In particular, FPGAs (Fields Programmable Gate Arrays)
Several configuration techniques:Static vs DynamicPartial vs TotalExternal vs Internal
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Useful DefinitionsUseful Definitions
CoreCore: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)IP-CoreIP-Core: a core described using a HDL combined with its communication infrastructure (i.e. the bus interface)Reconfigurable Functional UnitReconfigurable Functional Unit: an IP-Core that can be plugged and/or unplugged at runtime in an already working architectureReconfigurable RegionReconfigurable Region: a portion of the device area used to implement a reconfigurable coreReconfigurable SlotReconfigurable Slot: a high-level representation of a Reconfigurable Region
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OutlineOutline
Fundamental ConceptsProposed Flow
High-level Modeling PhaseLow-level Implementation Phase
Case StudyResultsConclusions and follows-up
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Flow OverviewFlow Overview
Dynamic Partial ReconfigurationFlow composed of two phases:
HLMPLLIP
Support from system specification to system FPGA implementation
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High Level Modeling PhaseHigh Level Modeling Phase
From the System Specification to the System Hardware Description
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HLMP – Tools and TechniquesHLMP – Tools and Techniques
Two techniques to model dynamic reconfigurable systems are proposed:
Reconfiguration Aware ModelingReconfiguration Unaware Modeling
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Simulink HDL Coder Compliant ModelsSimulink HDL Coder Compliant Models
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HLMP – Reconfiguration Aware ModelingHLMP – Reconfiguration Aware Modeling
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HLMP – Reconfiguration Unaware ModelingHLMP – Reconfiguration Unaware Modeling
The first technique requires more knowledge but can lead to better results
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Low Level Implementation PhaseLow Level Implementation Phase
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System GenerationSystem Generation
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LLIP – The Caronte Flow and SysGenLLIP – The Caronte Flow and SysGen
Main LLIP thesis contribution: SysGen
SysGen
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OutlineOutline
Fundamental ConceptsProposed Flow
High-level Modeling PhaseLow-level Implementation Phase
Case StudyResultsConclusions and follows-up
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Real-world ApplicationReal-world Application
Inpeco Corporation proposed to implement an embedded vision system exploiting dynamic reconfigurationThe goal is to provide functionalities such as:
Mapping of the test-tubes within a rackTest-tube sample chromatic analysisTest-tube lateral recognition
The system must also be as flexible as possible, since new functionalities may be required in the future
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Overall DescriptionOverall Description
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Real-world Application – System Model Real-world Application – System Model
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OutlineOutline
Fundamental ConceptsProposed Flow
High-level Modeling PhaseLow-level Implementation Phase
Case StudyResultsConclusions and follows-up
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FPGA Logical view
Classical SystemClassical System
The static system implementation uses 96.9% of targeted device, a Xilinx XC4VFX12-FF668-10 FPGA, slices (and some functionalities are missing)
FPGA Physical view
BaseArch.
RGB to grayscale
Edge detection
Circle detection
Slot detection
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FPGA Logical view
Dynamic Reconfigurable SystemDynamic Reconfigurable System
The dynamic reconfigurable implementation uses only 66.6% of available slices (26.0% of them can be reused)
Physical view
Static Area
BaseArch.
Rec.Area
RFU
FreeResource
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Occupation DataOccupation Data
Resource Type Used Available PercentageSlices 5303 5472 96.9%Flip Flops 3269 10944 29.9%4 input LUTs 9032 10944 82.5%LUTs used as logic 8624 9032 95.5%LUTs used as shift registers 24 9032 0.3%LUTs used as RAMs 384 9032 4.2%FIFO16/RAMB16s 16 36 44.0%
Static System
System Component Slice Occupied Slice Available PercentageBase architecture 2364 5472 43.2%RGB to grayscale 212 5472 3.9%Edge detector 936 5472 17.1%Circles detector 1427 5472 26.0%Slots detector 507 5472 9.3%
Dynamic Reconfigurable
System
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Classic System vs DR SystemClassic System vs DR System
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Scientific PapersScientific Papers
A paper describing the improved version of the low-level implementation phase has been published in the RAW (Reconfigurable Architectures Workshop) 2008 proceedings:
A Design Flow Tailored for Self Dynamic Reconfigurable Architecture
(Marco D. Santambrogio, Donatella Sciuto and Fabio Cancare)
A paper describing the high-level modeling phase has been submitted at CODES+ISSS (International Conference on Hardware-Software Codesign and System Synthesis) 2008
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OutlineOutline
Fundamental ConceptsProposed Flow
High-level Modeling PhaseLow-level Implementation Phase
Case StudyResultsConclusions and follows-up
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Conclusions and Follow-upsConclusions and Follow-ups
The model-based design paradigm has been successfully used as part of a dynamic reconfigurable system implementation flowTwo high-level modeling techniques were outlinedEnhancement of the Caronte low-level implementation phaseThe proposed flow has been employed to produce a first version of an industrial application
Test the approach with other applicationsFor what concerns the case study, it is necessary to implement the other functionalities and to introduce DMA
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General InformationGeneral Information
Webpagewww.dresd.org/?q=hlr
Mailing [email protected]
ContactTo have more information regarding HLR:
[email protected] a complete list of information on how to contact us:
www.dresd.org/?q=contact_hlr
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Any Question?Any Question?
Thank you very much!
