Thesis F. Redaelli UIC Slides EN

University of Illinois at Chicago

Thesis Committee

Prof. J. Lillis, Prof. S. Dutt, Prof. D. Sciuto

Task Scheduling T Tailored forailored for PPartiallyartially D Dynamicallyynamically

RReconfigurableeconfigurable D Devicesevices

UIC Thesis Defence UIC Thesis DefenceMay 2007 May 2007

.:: Francesco Redaelli ::..:: Francesco Redaelli ::.

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OutlineOutline

• Outline

• Context Definition

• Problem Definition

• Reconfiguration Features

• State of the Art

• ILP Formulation

• Reconfiguration-aware Scheduler

• Experimental Results

• Conclusion and Future Works

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AimsAims

(A1) Definition of a formal model for the scheduling problem in a partially dynamically reconfigurable scenario

(A2) Development of a heuristic method to solve in reasonable time the proposed scheduling problem

(A3) Validation of the proposed ILP model and heuristic scheduler

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What’s next…What’s next…

• Outline





• ILP Formulation




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Context DefinitionContext Definition

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ReconfigurationReconfiguration

The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation.

Gerald Estrin, 1960

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Partial Total

8


Partial TotalDynamic

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• Outline





• ILP Formulation




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Problem Definition Problem Definition 1 of 21 of 2

•G=<O,P>

•O set of tasks

•P set of dependences between tasks (edges)

•schedule the task graph onto a dynamically partially reconfigurable architecture with an area constraint Atot in order to minimize the completion time.

Each task i is characterized by:

• tyi the type of the task;

• ci the area occupied onto the FPGA;

• tri the time needed to reconfigure the task onto the

FPGA;

• tei the execution time of the task;

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Problem Definition Problem Definition 2 of 22 of 2

A solution for this problem is found giving for eack task:

• the reconfiguration beginning time;

• the execution beginning time;

• the position on the FPGA where it is mapped.

The FPGA area constraint Atot is given as the number of columns available for the reconfigurable hardware.

The area property ci of each task is given as the number of adjacent columns onto the FPGA.

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• Outline





• ILP Formulation




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Reconfiguration FeaturesReconfiguration Features

Partially Dynamically Reconfigurable FPGAs allow:

•Configuration prefetching

•Module reuse

•Anti-fragmentation techniques

Try to exploit these features in the best way to schedule the task graph

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Configuration PrefetchingConfiguration Prefetching

Ti: execution of task i

Ri: configuration of task i

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Module ReuseModule Reuse



T1

T2

T3

T4R4

T1

T2

T3

T4

T5R5

time

FPG

A A

REA

time

FPG

A A

REA

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Anti-Fragmentation TechniquesAnti-Fragmentation Techniques



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• Outline





• ILP Formulation




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State Of the Art State Of the Art 1 of 31 of 3

Scheduling done using a list-based approach

HW/SW Co-design usually considered

Anti-fragmentation techniques are not considered:

• First Fit

• Best Fit

Most frequently used deconfiguration policy is the LIU one with no limitation

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[BBD06a] S. Banerjee, E. Bozorgzadeh, N. D. Dutt “Integrating physical constraints in HW-SW Partitioning for Architectures with partial dynamic reconfiguration”, IEEE Transactions on very large scale integration system, vol. 14, no. 11, november 2006

PRO:

• Extendible for only HW environments;

• Configuration prefetching;

• Explicit adjacent column based constraints for task mapping;

• Partial reconfiguration;

CONS:

• No module reuse;

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[BBD06b] S. Banerjee, E. Bozorgzadeh, N. Dutt, ”PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures”, In Proceedings of Asia and South Pacific Design Automation Conference, ASP-DAC, 24-27 January, 2006.

PRO:

• Thought for only HW environments;

• Configuration prefetching;

• Anti-fragmentation techniques for linear task graphs;

• Partial reconfiguration;

CONS:

• Only linear task graphs;

• No module reuse.

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• Outline





• ILP Formulation




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ILP Formulation - Basic IdeaILP Formulation - Basic Idea

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ILP Formulation ILP Formulation 1 of 21 of 2

Constants:

• tyij equal to 1 if task i has the same type of task j;

• tri the time needed to reconfigure the task onto the FPGA;

• tei the execution time of the task;

• ci the number of adjacent columns occupied onto the FPGA.

Variables:

• ritk = 1 if task i is on the FPGA at time t starting from column k

= 0 otherwise

• mri = 1 if task i exploits module reuse

= 0 otherwise

• recit = 1 if task i is reconfigured at time t

= 0 otherwise

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ILP Formulation ILP Formulation 2 of 22 of 2

OBJECTIVE OBJECTIVE FUNCTIONFUNCTIONTfMIN

Variables (Cont'd)

• Soni: time when task i arrives on the FPGA

• Soffi: time when task i is removed from the FPGA

• Tf: task graph completion time

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ILP Formulation – Constraints ILP Formulation – Constraints 1 1 of 5of 5

1) Area constraint

Atotcrhiihk

Atot

k

O

i

11,

2) Non overlap constraint

1,,)1,1max(1

ihl

k

ickl

O

irkh

3) Right space

0211

ihk

Atot

icAtotk

T

h

O

ir

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4) Zero time

0011

ki

Atot

k

O

ir

7) Always same column

)1(,,,111

ihkimk

T

miml

Atot

l

T

mrTrrkhi

ihk

Atot

kirhSoff

1

,, hi 8) Definition of on board time and offboard time

)1(11 ihk

Atot

kihk

Atot

kirTrhSon

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1,11

iiihk

Atot

k

T

hSonSoffri

9) Continuous usage

10) Reconfigured tasks constraints

iihk

Atot

k

T

h

ei

ri

mrTrtti 11

,

ii

T

himrTrechSoni

)(,

1

iii

T

hmrTSonrechi

)(,

1

29


)1()1(1,,, )1()(,1

iihkkhikihjij

O

ijjmrTrTrrtykhi

12) Permission of reuse

1,)1,1max(1

im

h

rithm

O

irech

11) Single reconfiguration device

)1(,11 iihk

Atot

k

T

h

ei

mrTrti

13) Reused task constraints

iih

T

hmrreci

1,

1

30


iejjSofftSoffPji ,),(

14) Precedences

TTf 16) Final time constraint

iSoffTfVi ,

15) Final time definition

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• Outline





• ILP Formulation




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NapoleonNapoleonReconfiguration-Aware Scheduler Reconfiguration-Aware Scheduler 1 of 31 of 3

Napoleon: heuristic reconfiguration-aware scheduler, list-based with priority function the ALAP value of a node. It allows out of order scheduling for particular task graphs.

It tries to exploits at best

• Configuration prefetching

• Module reuse

It also uses anti-fragmentation techniques to improve the quality of the solution

It tries to build a solution taking into account the constraints found in the ILP formulation of the problem

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Anti-Fraqmentation Techniques:

farthest placement



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limited deconfiguration




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• Outline





• ILP Formulation




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Experimental Results Experimental Results

GLPK [http://gnuwin32.sourceforge.net/packages/glpk.htm] has been used to solve the ILP instances

Benchmark

Ten task graphs with ten nodes [BBD06a]

9135 task graphs with a number of nodes in a 10-1000

range

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Other AlgorithmsOther Algorithms

ASAP

ALAP

DyASAP

These algorithms have been used to verify the real effectiveness of Napoleon

They have been chosen as the most representative for the solution of our problem in the literature

When a deconfiguration policy is used it is unlimited

All these algorithms have been implemented

ASAPS

ALAPS

DyASAPS

ASAPB

ALAPB

DyASAPB

ASAPLIU

ALAPLIU

DyASAPLIU

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Results Results 1 of 41 of 4

39


40


Ten1 Ten2 Ten3 Ten4 Ten5 Ten6 Ten7 Ten8 Ten9 Ten100

5

10

15

20

25

30

35

40

ALAPASAPBDyASAPSALAPLIUNapoleonILP

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• Outline





• ILP Formulation




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Conclusions and Future WorksConclusions and Future Works

Conclusions:

ILP model formulation for the scheduling problem in a partially dynamically reconfigurable scenario --> (A1)

Napoleon heuristic method based on the ILP formulation --> (A2)

Napoleon obtains schedule length (in average) 18.6% better than the other algorithms --> (A3)

Future works

Integrate Napoleon into a general framework, to create a scheduling/reconfiguration-aware partitioning

Integrate Napoleon in DRESD-HLR to complete the design flow to implement large applications onto partially dynamically reconfigurable devices

Try new anti-fragmentation techniques

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Questions?Questions?

Thank you…Thank you…

Business

Thesis F. Redaelli UIC Slides EN