Metaswitch and Intel: A Systematic Approach to NFV

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Intel and Metaswitch A Systematic approach to NFVSimon Dredge @dredgie Director, Technical MarketingCarrier Network Virtualization // Intel Pre-Conference Workshop // November 2015 //

The Brains of the New Global Network

Systematic steps to NFV

// Make the transition from NEP to Network Software ProviderMetaswitch Networks | Proprietary and confidential | 2015 | 2

2

Systematic steps to NFV

NICCPU

Network FunctionOperating System

// Make the transition from NEP to Network Software ProviderMetaswitch Networks | Proprietary and confidential | 2015 | 3

3

Systematic steps to NFV

NICCPU

Network FunctionOperating System

NICCPU

Virtual MachineNetwork FunctionOperating SystemvNIC

// Make the transition from NEP to Network Software ProviderMetaswitch Networks | Proprietary and confidential | 2015 | 4

4

Systematic steps to NFV

NICCPU

NICCPU

Network FunctionOperating System

NICCPUvSwitch

Virtual MachinevNIC

Network FunctionOperating System

Virtual MachineNetwork FunctionOperating SystemvNIC

// Make the transition from NEP to Network Software ProviderMetaswitch Networks | Proprietary and confidential | 2015 | 5

5

Steps to NFV: CarriersMetaswitch Networks | Proprietary and confidential | 2015 | 6

Custom HardwareVirtualizedCloud / NFVLowHigh

COTS Hardware

PricePerf.EfficiencyFlexibility

NFV or Bust

FlexibilityIncreased dependency on SDN techniques augment Capex savings with OpexMetaswitch Networks | Proprietary and confidential | 2015 | 7

7

Out with the Old: Reinventing the SBCMetaswitch Networks | Proprietary and confidential | 2015 | 8

General Purpose CPU

DSPMediaSignalingblacklisted packet discard

NetworkProcessor

CryptoTCAM

No vMigration

SBC Application

NxCPU CoreOS KernelSystem Memory

I/OIntel Architecture

A path to NFVA Picture of two Distinct SBC approachesMetaswitch Networks | Proprietary and confidential | 2015 | 9

Smart Software and powerful processors Eliminate the need for custom hardware //

9

// Multi-thread across multiple cores

// Use cache memory as the TCAM

// Leverage CPU AES instruction set

// Do performance jobs in the kernel

// New codecs are designed for CPUAn SBC Architected for the CloudMetaswitch Networks | Proprietary and confidential | 2015 | 10

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Performance and Dataplane Acceleration// Perform processor-intensive functions in the kernel / close to the hardwareMetaswitch Networks | Proprietary and confidential | 2015 | 11

Performance and Dataplane Acceleration// Single Root IO Virtualization (SR-IOV)

// DMAs into guest I/O memory space without interrupting the hypervisor or VM CPU

// Bypasses the Hypervisor / vSwitch// Perform processor-intensive functions in the kernel / close to the hardwareMetaswitch Networks | Proprietary and confidential | 2015 | 12

Performance and Dataplane Acceleration// Data Plane Development Kit (DPDK)

// A collection of open source Linux libraries and drivers

// Polled zero-copy DMA into large ring FIFO / ring buffer

// Single Root IO Virtualization (SR-IOV)

// DMAs into guest I/O memory Space without interrupting the hypervisor or VM CPU

// Bypasses the Hypervisor / vSwitch// Perform processor-intensive functions in the kernel / close to the hardwareMetaswitch Networks | Proprietary and confidential | 2015 | 13

SBC Performance Testing Results

SR-IOVKernel Smarts

DPDK

100%

Perimeta vSBC comparison with classic hardware SBCs

94%

85%Metaswitch Networks | Proprietary and confidential | 2015 | 14

// Lightweight Linux Containers (LXC)

// More efficient for VNFC / Microservices

// No access to the Kernel, unlike VMs

// 20% of the function / 80% of the CPU

// Employ Graphics Processors (GPUs)

// Offload processor-intensive operationsFuture: Micro services and managed containers Metaswitch Networks | Proprietary and confidential | 2015 | 15

THANK YOUSimon Dredge @dredgie Director, Technical MarketingNovember 2015

The Brains of the New Global Network

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