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Dan Glotter CEO & Founder, OptimalTest
9 September 2013
Escape prevention
& RMA management
It’s time to check
is “good” really good ?
Quality
Top fabless executives consensus:
“ >>50% of Quality issues & Escapes originate from the Back-end”
Note: Back-end= WS, WLP, Assembly, FT, SLT, Module-Test
2 9/9/13
Trends driving quality (1) -- Wafer level packaging --
(WLCSP | WCSP | WLP | WLBGA)
9/9/13 3
For the last few years new Wafer Level Packaging technology is being used for many products like mobile phones, laptop, MP3, GPS etc.
After the FAB process the wafer goes through those steps:
Wafer bumping, wafer level test, back grind, dicing, and
Packing in tape & reel to support a full turn-key WLCSP solution
That means that THERE IS NO MORE FT/BI/SLT OPERATION !!! The tape is going directly to the customer for board level mounting
Thus, Quality becomes critical since there is no other gate keeper
Trends driving quality (2) -- Multi Chip Packaging (2D, 2.5D, 3D & TSV) --
9/9/13 4
MCP refers to a packaging configuration containing up-to 8 chips, connected via wire-bonds to a multi-layer circuit board, and protected by either a molded encapsulant or a ceramic package
A common example is a memory card containing 2 devices
An expensive flash – say 128GB ~10$ device
A cheap controller – a few cents device
The problem is if the package fails due to the cheap controller
The problem intensifies when it evolves many devices
Future Trends driving quality
-- Wafer to Wafer Through Silicon Via (TSV) –
9/9/13 5
Through Silicon Via (TSV) enable 3D IC by stacking silicon wafers (and/or dies) and interconnecting them vertically so that they behave as a single device
Expected example: combining full wafers of CMOS logic, DRAM and III-V materials into a single IC
Problem is if the wafer’s quality level varies from the other wafer’s quality level
The problem intensifies when it evolves multiple wafers
Financial Trends driving quality -- Dual design wins changed the game rules --
-- Devices’ Quality drive profitability --
9/9/13 6
Key OEMs will use the following strategy in the design will selection:
Chip performance vs. the overall electronic device characteristics The Price Ability to meet supply/demand Having 2 design wins for negotiation purposes & supply/demand Quality levels and previous DPPM performance
Once decision is made on the 2 design wins, and assuming that the winners meet the 5 criteria, the next critical priority is QUALITY
Failure to meet contractual committed DPPM will drive 2 actions:
Immediate exposure to the CEO of the chip manufacturer + task force Temporarily lowering immediate purchase and choosing the other design win to SIGNAL
the importance of Quality If DPPM levels are not controlled and becomes an ongoing issue, then most probably it
will affect the ability to get NEW design wins
The Need
9/9/13 7
Handling potential escapes requires a comprehensive system which covers the end-to-end supply chain:
Analysis and simulation tools to evaluate potential escapes and outlier algorithms on historical data
Rule generation and publication processes to deploy escape prevention and outlier rules at test houses
Execution of the escape prevention and outlier rules on OptimalTest's servers once testing is completed anywhere in the supply chain
Fully integrated and automated modification of inkless bin maps for assembly or in Final Test anywhere in the supply-chain
Monitoring and feedback tools to track the actual performance of the escape prevention and outlier detection
Tight Quality “Safety Net”
9/9/13 8
The solution should be an Escape Prevention Solution (EPS) to
enable a tight safety net that becomes the “escape gate-
keeper” in any of your testing operations
The solution should offer Fabless or IDM Business Units the
ability to create & activate rules vis-à-vis their Foundry, OSAT
or IDM factory – The rules should be executed through an
integrated supply chain infrastructure to provide full Quality
& health control
Some facts… about OptimalTest
9/9/13 9
Strategic supplier of top Fabless, IDM & OSAT
Installed across whole world-wide Fabless/Foundry/OSAT supply chain at
-
#1 Fabless #2 Fabless #3 Fabless
#5 IDM #3 OSAT
2013: ~3,300 testers - over 25M units run on OT per day… ~10B per year…. and growing
#4 Fabless #5 Fabless
Escape Prevention Solution
9/9/13 10
OptimalTest’s Escape Prevention Solution consists of the
following elements:
RMA database for thorough management of the escapes
3 families of Outlier Detection capabilities for Wafer Sort & Final Test: Parametric , Geographical & Cross-Operational
OT-Detect: an excursion prevention system that automatically tracks after ALL your products for ANY changes in BASELINE production (HB, SB, Params)
Dozens of unique algorithms that were “created with blood” following many escapes and thorough RMA analysis
OptimalTest is the only Outlier Detection provider with an
infrastructure embedded into ALL the Foundries’ & OSAT’s operations
Wafer Sort - Outlier Detection Parametric & Geographic
9/9/13 11
DPAT: "Dynamic Part Average Testing"
NNR: "Nearest Neighbor Residual" is the best algorithm to use for avoiding yield overkill caused by Fab-related geographical differences
It can also use "bivariate" tests - virtual tests created as a regression of the two real parametric tests.
Z-PAT: "Z-Axis Part Average Testing"
GDBN: "Good Die in Bad Neighborhood"
Bad Reticule Detection: "Bad Reticule Detection"
Zonal: “Low yield zone based detection"
Final Test - Parametric Outlier Detection
9/9/13 12
OptimalTest’s Outlier Detection for Final Test is based on 3 optional methodologies:
1) In real time at Final Test based on Die-ID
a) Same operation with a TP API to OT
2) Post Final Test operation and Based on Die-ID (ULT/OTP/ECID)
a) Option a: Next Operation execution (i.e. SLT or WH)
b) Option b: FT-PAT operation (Short TP that reads only Die ID)
3) In real-time at Final Test operation without Die-ID The downside of this method is the outlier baseline statistical size
Cross-Operational Outlier Detection
9/9/13 13
Cross-Operational Quality based on Die-ID
Contributing operations
E-Test/PCM/WAT
Wafer Sort
Final Test
Burn-In
System Level Test
Example: E-Test based bin-switching post-WS The ability to identify potential bad devices based on E-Test data geographical
analysis – The bin-switching post wafer sort – Requires Data-Feed-Forward within the supply chain
RMA Database
9/9/13 14
The new RMA Database will provide detailed information about parts returned from customers.
Data Entry: Users can identify parts by ECID and mark them as returned in the database, together with categorization data
Data Retrieval: The RMA database is searchable and is listed in standard summary tables so that information about RMAs can be analyzed in OT-Portal
Historical Analysis: Lots containing parts which are returned are flagged in the database as “unpurgeable”. It impacts all operations in which the part or wafer was tested. Cross operation reports can be used to analyze the cause of the failure
Example of Escape Prevention Rules
9/9/13 15
Probe mark tracking The algorithm tracks probe marks per each die at wafer sort and compares with a specified value. The rule takes into account retests & multiple operations as well as “hidden” probe marks in parallel testing when dice are touched but not tested
Other rules:
Failing tests in good parts PRR validation (Part Results Record) ULT validation Freeze detection Parametric trend Process capability (CPK) Good die/device with “out of spec” test results