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논리회로 설계실험
담당교수 : 전재욱담당조교 : 석민식 , 송지호
2
1 Analog & Digital
2 Binary Digit Operation
3 Gate Symbol
4 Combinational Logic Circuit
1 ANALOG & DIGITAL
Sub. Contents.1.1 Analog & Digital
1.2 Analog
1.3 Digital
3
1.1 Analog & Digital
4
V
T0
V
T0
Analog Digital
1.2 Analog
5
Input SignalOutput Signal
양적인 비례 관계
1.3 Digital
6
Input SignalOutput Signal
논리적인 비례 관계
2 BINARY DIGIT OPERA-TION
Sub. Contents.2.1 Binary System
2.2 Boolean Algebra
2.3 Venn Diagram
7
2.1 Binary System
○ Binary System• 0 과 1 로 이루어진 수• 표기법 : 10001001(2)
○ Decimal to Binary Conversion
8
652
32 … 116 … 008 … 004 … 002 … 001 … 0
22222
1000001128 64 32 16 8 4 2
10 1 0 0 0 0 0 1Binary :
2.2 Boolean Algebra
○ Logical Sum : +► A + B = Y
0 + 0 = 0
0 + 1 = 1
1 + 1 = 1
○ Logical Product : •► A • B = Y
0 • 0 = 0 0 • 1 = 0 1 • 1 = 1
○ Logical Not : /, ‾,n,`► A ( /A, nA, A`) = Y
0 = 1 1 = 0
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A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Truth Table
2.2 Boolean Algebra – Single Variable
○ AND X • 0 = 0
X • 1 = X
X • 0 = 0
X • X = 0
○ NOT X = X
○ OR X + 0 = X
X + 1 = 1
X + X = X
X + X = 1
10
2.2 Boolean Algebra – Multi Variable
○ Commutative Law• X + Y = Y + X• X • Y = Y • X
○ Associative Law • X + (Y + Z) = (X + Y) + Z = X + Y + Z• X(Y • Z) = X • Y • Z = XYZ
○ Distributive Law• X(Y+Z) = X • Y + X • Z = XY + XZ• (X + W)(Y + Z) = X • Y + X • Z + W • Y + W • Z = XY + XZ + WY + WZ
○ Other Law• X + XY = X• X + XY = X + Y
11
2.3 Venn Diagram
12
XY
XY XY
2.4 De-Morgan Law
13
A + B = A • B
A • B = A + B
3 GATE SYMBOL
Sub. Contents.3.1 Buffer & NOT Gate
3.2 AND & NAND Gate
3.3 OR & NOR Gate
3.4 XOR & ExOR Gate
3.5 Relativity Theorem
14
3.1 Buffer & NOT Gate
15
NOT Gate Buffer
Input Output
0 1
1 0
Input Output Input Output
Input Output
0 0
1 1
3.1 Buffer & NOT Gate - Analog Not Gate Cir-cuit
16
Input
Output
B
C
E
B = 0
B = 1
3.2 AND & NAND Gate
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AND Gate NAND Gate
Input A
Input BOutput
Input A
Input BOutput
Input A Input B Output
0 0 0
0 1 0
1 0 0
1 1 1
Input A Input B Output
0 0 1
0 1 1
1 0 1
1 1 0
3.2 AND & NAND Gate - Analog AND Gate Cir-cuit
18
B
C
E=>
B
C E
Output
Input A Input B
< TR > < Switch >
3.3 OR & NOR Gate
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OR Gate NOR Gate
Input A
Input BOutput
Input A
Input BOutput
Input A Input B Output
0 0 0
0 1 1
1 0 1
1 1 1
Input A Input B Output
0 0 1
0 1 0
1 0 0
1 1 0
3.3 OR & NOR Gate - Analog OR Gate Cir-cuit
20
Input A Input B
Output
3.4 XOR & ExOR Gate
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ExOR(XOR) Gate ExNOR Gate
Input A
Input BOutput
Input A
Input BOutput
Input A Input B Output
0 0 0
0 1 1
1 0 1
1 1 0
Input A Input B Output
0 0 1
0 1 0
1 0 0
1 1 1
A ⊙ B = YA B = Y
3.5 Relativity Theorem
A + B = B + A
A+(B+C) = (A+B)+C
A(B+C) = A•B+A•C
A+0=A
A+1=1
A+A=A
A+A=1
A=A
A+B=A•B
A+A•B=A
A+A•B=A+B
A•B=B•A
A(B•C)=(A•B)C
A+B•C=(A+B)(A+C)
A•1=A
A•0=0
A•A=A
A•A=0
A=A
A•B=A+B
A(A+B)=A
A(A+B)=A•B22
4 COMBINATIONAL LOGIC CIRCUIT
Sub. Contents.4.1 Combinational Logic
4.2 Half-Adder
4.3 Full-Adder
4.4 Half-Subtracter
4.5 Full-Subtracter
4.6 Subtraction
4.7 Adder-Subtracter
23
4.1 Combinational Logic
24
Input A
Input B
Input C
Input D
Output
(A+B) (CD) = Output
4.2 Half-Adder
25
Input A
Input BSUM
CARRY
(A B) = SUMA • B = CARRY
4.2 Half-Adder
26
HalfAdder
Input A
Input B
SUM
CARRY
Input A Input B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
0+000
0+101
1+001
1+111
0010011+1000001
1010010
HalfAdder
HalfAdder
HalfAdder
HalfAdder
HalfAdder
HalfAdder
HalfAdder
CARRY ?
4.3 Full-Adder
27
HalfAdder
HalfAdder
Input A
Input B
SUM
CARRYInput C
Input A Input B Input C SUM CARRY
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
Input A Input B Input C SUM CARRY
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1
4.3 Full-Adder
28
Carry
Input AInput B
SUM
CarryInput
4.3 Full-Adder
29
FullAdder
HalfAdder
FullAdder
FullAdder
FullAdder
FullAdder
FullAdder
FullAdder
A1 B1A2 B2A3 B3A4 B4A5 B5A6 B6A7 B7A8 B8
SUM1SUM2SUM3SUM4SUM5SUM6SUM7SUM8CARRY
10010011+10010001100100100
4.4 Half-Subtracter
30
1-100
1-001
0-111
Borrow
DataInput AInput B
0-000
HalfSub-
tracter(HS)
Input A
Input B
SUM
Borrow
Input A Input B Data Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
4.5 Full-Subtracter
31
HSHS
Input A
Input B
Data
BorrowInput C
Input A Input B Input C Data Borrow
0 0 0 0 0
0 1 0 1 1
1 0 0 1 0
1 1 0 0 0
Input A Input B Input C Data Borrow
0 0 1 1 1
0 1 1 0 1
1 0 1 0 0
1 1 1 1 1
4.5 Full-Subtracter
32
Bor-row
Input AInput B
Data
Bor-rowInput
4.5 Full-Subtracter
33
FS HSFS FS FS FS FS FS
A1 B1A2 B2A3 B3A4 B4A5 B5A6 B6A7 B7A8 B8
D1D2D3D4D5D6D7D8Borrow
10011001-01000001101011000
4.6 Subtraction
34
10011001-01000001
?10111110 10111111
One’s complement Two’s complement
10011001+10111111101011000
10011001 = 15301000001 = 65
153 - 65 = 88
88
4.7 Adder-Subtracter
35
FA FAFA FA FA FA FA FA
A1 B1A2 B2A3 B3A4 B4A5 B5A6 B6A7 B7A8 B8
D1D2D3D4D5D6D7D8
Sel
10011001+10111111001011000
10011001-01000001
?
Plus & Minus Code
36
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