Chapter 4: Combinational Logic - WordPress.com · Chapter 4: Combinational Logic Eastern Mediterranean University 0 / 65 Combinational Circuit Design ... Scale of Integration (SSI,MSI,LSI,VLSI,SoC.)

Chapter 4: Combinational Logic

Eastern Mediterranean University 0 / 65

Combinational Circuit Design

Analysis Procedure (Find out nature of O/P)

Boolean Expression Approach

Truth Table Approach

Design Procedure

Example 1: BCD to Excess-3 code convertor

Example 2: Seven Segment Decoder

Standard and Canonical Terms

BCD to Excess-3 Code Convertor

Seven Segment Decoder

Binary Adder

Binary Adder ( 4-bits) with carry propagation

Cascading Multiple Adders

Reducing Carry Propagation Delay

(Parallel Adder, Carry Look Ahead Adder)

Binary Coded Decimal (BCD) Adder


BCD Adder (Using two binary Adder)

Binary Adder

A3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy

Binary Adder

A3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy

0 0

0

0

S3 S2 S1 S0Cy

x3 x2 x1 x0 y3 y2 y1 y0

ErrX +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value

9 + 0 1 0 0 1 0 0 0 0 = 9 0 1 0 0 1 0 0 0 0 1 0 0 1 = 9

9 + 1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16

9 + 6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21

9 + 9 1 0 0 1 1 0 0 1= 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24

BCD Operands: X= (x3 x2 x1 x0)

Y= (y3 y2 y1 y0)

Sum = S3,S2,S1,S0

Question : Design a magnitude comparator to compare two variables “A”

and “B”.Assume that the input numbers A and B are of two bits each.

Generate three output as A>B, A=B, A<B


Magnitude Comparator

Compare 2-bit number to 2-bit number


A1A0 B1B0

A<B A=B A>B

Generate Truth Table for all possible combination of A1A0 and B1B0.

Get K map for all three output.

Design hardware.



Compare 2-bit number to 2-bit number


A1A0 B1B0

A<B A=B A>B

A B A>B A=B A<B

A1 A0 B1 B0

0 0 0 0 0 1 0

0 1 1 1 0 0 1

1 0 0 1 1 0 0

Decoders


1. Concept and Specification

2. Application

3. Designing 2x4 Decoders

4. Decoders with Enable input

5. Designing 3x8 Decoders

6. Expanding (3x8 using 2x4 decoders)

7. Active High / Active Low output

8. Implementation using Decoders

Concept and Application


1. It is capable to identify combination of input bits and generate

unique output, say for 0000 0, 1000 8.

2. For two bit input it will generate 4 bit out put

3. Specification is nxm , means it is n input bits and m output bits.

4. Example specification are 2x4 , 3x8 etc.

Bin

ary

Dec

od

erI1

I0

y3

y2

y1

y0


Decoders (Concepts and Applications)

Extract “Information” from the code

Binary Decoder (2x4)

● Example: 2-bit Binary Number

BinaryDecoder

x1

x0

Only onelamp will turn on

0

0

1

0

0

0


Decoders (2x4 Truth Table and hardware )

2-to-4 Line Decoder

I1 I0 Y3 Y2 Y1 Y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

Bin

ary

Dec

od

erI1

I0

y3

y2

y1

y0

I1

I0

Y3

Y2

Y1

Y0

013 IIY 012 IIY

011 IIY 010 IIY


Decoders (With Enable Input)

Bin

ary

Dec

od

erI1

I0

E

Y3

Y2

Y1

Y0

E I1 I0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0 EI0

Y3

Y2

Y1

Y0

I1

I1 I0 Y3 Y2 Y1 Y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0 I1

I0

Y3

Y2

Y1

Y0

Bin

ary

Dec

od

erI1

I0

y3

y2

y1

y0


Decoders

3-to-8 Line Decoder (Give Hardware Diagram)

Bin

ary

Dec

od

erI2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

I2

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

I1

012 III

012 III

012 III

012 III

012 III

012 III

012 III

012 III

MSI Circuit Design

Scale of Integration (SSI,MSI,LSI,VLSI,SoC.)

Decoders:

(Cascading Decoders, Solving Boolean Expressions using Decoders)

Encoders

(Concept, Design, Cascading, Solving Expressions using Encoders)

Octal Encoder, Priority Encoder, Interfacing Application)

Multiplexers

(Concept, Design, Cascading, Solving Expression usinf MUX)


Scale of Integration


SSI: Small-scale Integration : Gates< 10

MSl: Medium-scale Integration : 10<Gates< 1000

LSl: Large-scale Integration : Gates> 1000

VLSI: Very Large-scale Integration : Gates>100000

SoC: Systems on Chip :Million Gate, Software & Hardware.

MSI (Medium Scale Integration)

Example MSI (Medium Scale Integration)

Decoders

Encoders

Multiplexers

De-multiplexers

PLA

PAL etc.



Decoders (3x8 decoders using 2x4 decoders)

Expansion

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

I2 I1 I0

Bin

ary

Dec

od

erI0

I1

E

Y3

Y2

Y1

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Bin

ary

Dec

od

erI0

I1

E

Y3

Y2

Y1

Y0


Decoders

Active-High / Active-Low output (Give H/W)

I1 I0 Y3 Y2 Y1 Y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

I1 I0 Y3 Y2 Y1 Y0

0 0 1 1 1 0

0 1 1 1 0 1

1 0 1 0 1 1

1 1 0 1 1 1

Bin

ary

Dec

od

erI1

I0

Y3

Y2

Y1

Y0I1

I0

Y3

Y2

Y1

Y0

Bin

ary

Dec

od

erI1

I0

Y3

Y2

Y1

Y0


Implementation Using Decoders

Each output is a minterm

All minterms are produced

Sum the required minterms

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

x

y

z

0127 IIIY 0126 IIIY 0125 IIIY

0124 IIIY

0123 IIIY

0122 IIIY 0121 IIIY

0120 IIIY

Set of minterms available at o/p of decoder


Implementation Using Decoders

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

x

y

z

0127 IIIY

0126 IIIY

0125 IIIY

0124 IIIY

0123 IIIY

0122 IIIY

0121 IIIY

0120 IIIY

What is the meaning of implementation using MSI

Implement SOP

f (a, b, c) = m2, m5, m6, m7

Eastern Mediterranean University

17 / 65

Use Decoder IC to Implementation Full Adder

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

x

y

z

S C

x y z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

0127 IIIY

0126 IIIY 0125 IIIY

0124 IIIY

0123 IIIY

0122 IIIY 0121 IIIY

0127 IIIY

S(x, y, z) = ∑(1, 2, 4, 7)

C(x, y, z) = ∑(3, 5, 6, 7)


Implementation Active Low Active High

How do we go for Active Low and Active High output.?

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

x

y

z

S C

As we know OR gate = Negative NAND Gate

Put –ve NAND gate on behalf of OR gate


Implementation Active Low Active High

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

x

y

z

S C

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

x

y

z

S C

Encoders

Example MSI (Medium Scale Integration)

Decoders

Encoders

Multiplexers

Demultiplexers

PLA

PAL etc.



Encoders

Put “Information” into code

Binary Encoder

● Example: 4-to-2 Binary Encoder

x3 x2 x1 y1 y0

0 0 0 0 0

0 0 1 0 1

0 1 0 1 0

1 0 0 1 1

BinaryEncoder

y1

y0

x1

x2

x3

Only oneswitch

should be activated at a time


Encoders

Design Octal-to-Binary Encoder (8-to-3)

I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Bin

ary

En

cod

er Y2

Y1

Y0

I7

I6

I5

I4

I3

I2

I1

I0


Design Equation for Octal to Binary Encoder

I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Bin

ary

En

cod

er Y2

Y1

Y0

I7

I6

I5

I4

I3

I2

I1

I0

13570

23671

45672

IIIIY

IIIIY

IIIIY

I7

I6

I5

I4

I3

I2

I1

I0

Y2

Y1

Y0

Digital Systems

24 / 65

1. Designing Priority Encoder

Multiplexers

1. Concept and Block Diagram and Specification

2. Designing 2x1, 4x1 MUX

3. Designing Quad 2x1 MUX

4. MUX with Enable input

5. Implement Boolean function using MUX

f(x,y)=Σ m(0,1,3) using 4x1 MUX

f(x,y,z)=Σ m(1,2,6,7) using 8x1 MUX

f(x,y,z)=Σ m(1,2,6,7) using 4x1 MUX

f(a,b,c,d)=Σm(1,3,4,11,12,13,14,15) using 8x1 MUX

6. Realizing larger size MUX using small size MUX

25 / 65

Design a Priority Encoders for 4 bit input

Pri

ori

tyE

nco

der V

Y1

Y0

I3

I2

I1

I0

I3 I2 I1 I0 Y1 Y0 V

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 0 0 1 1

0 0 1 1 0 1 1

0 1 0 0 1 0 1

0 1 0 1 1 0 1

0 1 1 0 1 0 1

0 1 1 1 1 0 1

1 0 0 0 1 1 1

1 0 0 1 1 1 1

1 0 1 0 1 1 1

1 0 1 1 1 1 1

1 1 0 0 1 1 1

1 1 0 1 1 1 1

1 1 1 0 1 1 1

1 1 1 1 1 1 1

I3 I2 I1 I0 Y1 Y0

0 0 0 0 0 0

0 0 0 1 0 0

1 0 1 0 1 1

1 1 1 1 1 1

Four I/P I3,I2,I1,I0

I3 Highest Priority (Assumed)

I0 Lowest Priority (Assumed)


Priority Encoders of 4 bit input

I0

I1

I2

I3

Y1

Y0

V

0123

1230

231

IIIIV

IIIY

IIY

Y1

I1

1 1 1 1I2

I3

1 1 1 1

1 1 1 1

I0

I3 I2 I1 I0 Y1 Y0 V

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 0 0 1 1

0 0 1 1 0 1 1

0 1 0 0 1 0 1

0 1 0 1 1 0 1

0 1 1 0 1 0 1

0 1 1 1 1 0 1

1 0 0 0 1 1 1

1 0 0 1 1 1 1

1 0 1 0 1 1 1

1 0 1 1 1 1 1

1 1 0 0 1 1 1

1 1 0 1 1 1 1

1 1 1 0 1 1 1

1 1 1 1 1 1 1

MULTIPLEXER Circuit (MUX)


MULTIPLEXER Circuit (MUX)

1. MUX is used to transfer large number of data over small unit.

2. It is a combinational circuit that select one input, out of many and

directs into single output, hence called as Many into One.

3. Selection of one input line is controlled by set of selection input, also

called as control input.

4. For N input lines we need log 2N selection lines.


Concepts and Block Diagram:


Multiplexers 4x1

MUX Y

I0

I1

I2

I3 S1 S0

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Truth Table

Block Diagram

Concepts and Block Diagram:

MUX Specification

Specification of MUX is Nx1, that means N: Number of Input Bits

1: Out put bit

Examples are 4x1,8x1….etc


Design 2x1 Multiplexers

MUX YI0

I1S

I1

I0

S

Y

S0 Y

0 I0

1 I1

Block Diagram Truth Table

Give Circuit Diagram

Design 4x1 Multiplexers

MUX Y

I0

I1

I2

I3 S1 S0

I1

I0

S1

YI2

I3

S0

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Truth Table

Block Diagram

Give Circuit Diagram

Design Quad 2-to-1 MUX

MUX

A3

A2

A1

A0

S

Y3

Y2

Y1

Y0B3

B2

B1

B0

What is Quad 2-to-1 MUX..?

We have two input numbers A and B, of 4 bits each.

If we want to fetch all 4 bits of A i.e. a3,a2,a1,a0 at one time and

all 4 bits of B i.e. b3,b2,b1,b0 at another time,

then we need quad 2x1 MUX

It is done via selection input “S”.

Define value of “S”

S=0 means all bits of A i.e. a3,a2,a1,a0 will pass to the output

S=1 All bits of B i.e. b3,b2,b1,b0 will pass to the output.

Find out the number of output bits….? Block Diagram

Input bits are four a3,a2,a1,a0

b3,b2,b1,b0

Output bits are four Y3,Y2,Y1,Y0


a3

a2

a1

a0

b3

b2

b1

b0S

MUX

A3

A2

A1

A0

S

Y3

Y2

Y1

Y0B3

B2

B1

B0

Y3

Y2

Y1

Y0

Question : Can we design above MUX using 4 number of 2x1 MUX..?

S Y3, Y2,Y1,Y0

0 a3 a2 a1 a0

1 b3 b2 b1 b0

Give Truth TableVariable Planning (i.e. Input Output)

Design Quad 2-to-1 MUX using 4 no of 2x1 MUX

MUX3 YI0

I1 S

MUX2 YI0

I1 S

MUX1 YI0

I1 S

MUX0 YI0

I1 S

a3

a2

a1

a0

b3

b2

b1

b0

S

MUX

A3

A2

A1

A0

S

Y3

Y2

Y1

Y0B3

B2

B1

B0

Y3

Y2

Y1

Y0

I1

I0

S

Y

MUX YI0

I1S

Give complete Circuit diagram of above design..

S0 Y

0 I0

1 I1


MUX3 YI0

I1 S

MUX2 YI0

I1 S

MUX1 YI0

I1 S

MUX0 YI0

I1 S

a3

a2

a1

a0

b3

b2

b1

b0

S

Y3

Y2

Y1

Y0

S E

A3

A2

A1

A0

B3

B2

B1

B0

MUX

A3

A2

A1

A0

S E

Y3

Y2

Y1

Y0B3

B2

B1

B0

Y3

Y2

Y1

Y0

Give complete Circuit diagram of above circuit diagram..

Design Quad 2-to-1 MUX (Identify 2x1 MUX)

MUX3 YI0

I1 S

MUX2 YI0

I1 S

MUX1 YI0

I1 S

MUX0 YI0

I1 S

a3

a2

a1

a0

b3

b2

b1

b0

S

Y3

Y2

Y1

Y0

S E

A3

A2

A1

A0

B3

B2

B1

B0

MUX

A3

A2

A1

A0

S E

Y3

Y2

Y1

Y0B3

B2

B1

B0

Y3

Y2

Y1

Y0

I0,3

I1,3

I0,2

I1,2

I1,1

I0,1

I0,0

I1,0

37 / 65

Multiplexers with Enable input

Y3

Y2

Y1

Y0

S E

A3

A2

A1

A0

B3

B2

B1

B0

MUX

A3

A2

A1

A0

S E

Y3

Y2

Y1

Y0

B3

B2

B1

B0

Extra Buffers

If E is defined at logic HIGH then E=1 will generate all output bits.

If E is defined at logic LOW then E=0 will generate all output bits.

Circuit Diagram Block Diagram

38 / 65

Multiplexers with Enable input

Y3

Y2

Y1

Y0

S E

A3

A2

A1

A0

B3

B2

B1

B0

MUX

A3

A2

A1

A0

S E

Y3

Y2

Y1

Y0

B3

B2

B1

B0

If E is defined at logic HIGH then E=1 will generate all output bits.

If E is defined at logic LOW then E=0 will generate all output bits.

If S=0 and E’=0 what is the output…? Y=A or Y=B

If S=1 and E’=0 what is the output..? Y=A or Y=B

If E’=1 what is the output..?


Implementation Using Multiplexers

Realize following function using MUX F(x, y) = ∑(0, 1, 3)

using 4x1 MUX

Question 1: Design Combinational circuit using 4x1 MUX. Boolean exp

of 2 variable and MUX of 2 pow 2 = 4 input, so the design in simple.

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

MUX Y

I0

I1

I2

I3 S1 S0

Mean term 0 means x’ y’

Mean term 1 means x’ y

Mean term 2 means x y’

Mean term 3 means x y

If we connect S0 with y literal

S1 with x literal

This would lead to

I0 = x’ y’

I1 = x’ y

I2 = x y’

I3 = x y



MUX Y

I0

I1

I2

I3 S1 S0

x y F

0 0 1

0 1 1

1 0 0

1 1 1x y

F

1

1

0

1

F(x, y) = ∑(0, 1, 3) using 4x1 MUX

Block Diagram

Question 1: Design Combinational circuit using 4x1 MUX. Boolean exp

of 2 variable and MUX of 2 pow 2 = 4 input, so the design in simple.



x y z F

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

MUX Y

I0

I1

I2

I3

I4

I5

I6

I7S2 S1 S0

x y z

0

1

1

0

0

0

1

1

F

Question 2: Implement following Boolean expression using 8x1 MUX

F(x, y, z) = ∑(1, 2, 6, 7) using 8x1 MUX

Expression of three variable and number of selection input of 8x1

MUX is calculated as log 2 8 = 3 input, so the design is simple.



MUX Y

I0

I1

I2

I3 S1 S0

x y

F

Question 3: Implement following Boolean function using MUX

F(x, y, z) = ∑(1, 2, 6, 7) , do not use 8x1 MUX but 4x1 MUX is

available.

Function given is of three variable, and 4x1 MUX is available.

Given 4x1 Mux will have log 2 4 = 2 selection input.

Three input variable and two selection input are not simple, hence the

design steps will be different



MUX Y

I0

I1

I2

I3 S1 S0

x y z F

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

x y

FF = z

F = z

F = 0

F = 1

z

z0

1

Question 3: Implement following Boolean function using MUX

F(x, y, z) = ∑(1, 2, 6, 7) , do not use 8x1 MUX but 4x1 MUX is available.


MUX Y

I0

I1

I2

I3

I4

I5

I6

I7S2 S1 S0


A B C D F

0 0 0 0 0

0 0 0 1 1

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1 A B C

F

F = DD

F = DD

F = D

D

F = 0

0

F = 0

F = D

F = 1

F = 1

0

D

1

1

Question 4: Implement following function using 8x1 MUX

F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)

Given function is of 4 variable, selection input of available 8x1

MUX is calculated as log 2 8 =3, hence design is not simple.

45 / 65

Multiplexer Expansion (Design 8x1 using dual 4x1 and single 2x1)


8x1

MUX

Y

I0

I1

I2

I3

I4

I5

I6

I7

S2 S1 S0

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

Block DiagramTruth Table

46 / 65

Y

I0

I1

I2

I3

I4

I5

I6

I7

S2 S1 S0

MUXY

I0

I1

I2

I3 S1 S0

MUX Y

I0

I1

I2

I3 S1 S0

MUXYI0

I1S

0 01

Multiplexer Expansion (Design 8x1 using dual 4x1 and single 2x1)

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7


DeMultiplexers

DeMUXI

Y3

Y2

Y1

Y0S1 S0

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

I

Y3

Y2

Y1

Y0

S0

S1


Multiplexer / DeMultiplexer Pairs

Y

I7

I6

I5

I4

I3

I2

I1

I0

I

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

MUX DeMUX

S2 S1 S0 S2 S1 S0

x2 x1 x0 y2 y1 y0

Synchronize


Compare DeMultiplexers / Decoders

Bin

ary

Dec

od

erI1

I0

E

Y3

Y2

Y1

Y0

E I1 I0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

DeMUXI

Y3

Y2

Y1

Y0S1 S0

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0


Three-State Gates (Tristate Inventor and Buffer)

Tri-State Buffer

Tri-State Inverter

A Y

C

C A Y

0 x Hi-Z

1 0 0

1 1 1

A Y

C


Three-State Gates

A

YC

B

D

C D Y

0 0 Hi-Z

0 1 B

1 0 A

1 1 ?

Not Allowed

Y=

A

C

B

A if C = 1

B if C = 0


Three-State Gates

I0

Y

E

S1

I1

I2

I3

Bin

ary

Dec

od

erI1

I0

E

Y3

Y2

Y1

Y0

S0


Design Encoder / Decoder Pairs

Question : Design a switching circuit to interface eight ON/OFF

switch ( 0,1,,2…7)to operate 8 LED (0,1,2…7). Assuming that if switch

0 will operate LED0 , and switch 7 will operate LED7.


Encoder / Decoder Pairs

Y2

Y1

Y0

I7

I6

I5

I4

I3

I2

I1

I0

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryEncoder

BinaryDecoder

Documents

Chapter 4: Combinational Logic - WordPress.com · Chapter 4: Combinational Logic Eastern Mediterranean University 0 / 65 Combinational Circuit Design ... Scale of Integration (SSI,MSI,LSI,VLSI,SoC.)