Chapter 5 Larger combinational system

Chapter 5 Larger combinational system

Contents

Delay in combinational logic circuit Analysis of combinational circuits Design of combinational circuits Some common types of circuits: adde

rs( 加法器 ), decoder( 译码器 ), encoder( 解码器 ) an priority encoder, multiplexer( 数选器 )

Gate array: ROM, PLA, PAL

Consider the effect of the delay through gates

Delay in combinational logic circuits

When the input to a gate changes, the output of that gate does not change instantaneously( 即刻 ); but, there is a small delay, Δ. If the output of one gate is used as the input to another, the delays add.

AB

C

X

F

Figure 5.1

X

AB

C

F

X

AB

C

F

No small delay, Δ.

There is a small delay, Δ.

1Δ 2Δ

1Δ

1Δ 1Δ

2Δ

a a hazardhazard or a or a glitchglitch

4.1.1 Analysis of Combinational Circuits 组合电路分析

This section will present the analysis process of digital circuits and examples .

Analysis is a procedure from a logic circuit to function descriptions.

Purpose: Analysis is used to determine the behavior of a logical circuit , to verify that the behavior of a circuit matches its specification; or to assist in converting the circuit to a different form ， either to reduce the number of gates or to realize it with different elements.

Step 1: Write out the algebraic expression of a logic circuit.Step 2: Formalize the truth table .Step 3: Describe the function or behavior of a logic circuit.

ab

c

a

b'a'

b

c

f ( a, b, c)

P1

P2

P3

P4

P5

P6

Fig 4.1.

Example 4.1: Find a simplified switching expression and circuit for network of Fig 4.1

ab

c

a

b'a'

b

c

f ( a, b, c)

P1

P2

P3

P4

P5

P6

Fig 4.1

1P a b

2P b c

3 ' 'P a b

4P a c

5 1 2P PP

6 3 4P P P 5 6( , , )f a b c P P

Analysis:

cbcaba

cbcaabba

cbaab

caabcbbcbaab

baabcbba

cabacbbaf

''

''''

'''

)'')(''''(

)'')((

)''())((

A

B

C

B’

A’

Example 4.3: Analyze the function of Fig. 4.0.4.

&

&

&

&

&

11

d0

Fd1

d2

d3

A1 A0

Fig 4.0.4.

1. Write out the algebraic expression

0 1 0 1 1 0 2 1 0 3 1 0

0 1 0 1 1 0 2 1 0 3 1 0

0 0 1 1 2 2 3 3

F = ( d A A )( d A A )( d A A )( d A A )

= d (A A )+ d (A A )+ d (A A )+ d (A A )

= d m + d m + d m + d m

2. Formalize the truth table

A1 A0 F

m0 d0

m1 d1

m2 d2

m3 d33. The function of this logic diagram

The three steps of analysis are listed as follows:

Step 1: Write out the algebraic expression of a logic circuit.Step 2: Formalize the truth table .Step 3: Describe the function or behavior of a logic circuit.

ab

cs

outc& ≥ 1

=1

1

=1abc

S

Cout

Fig 4.0.3.

and-or-not gate

Example 4.2: analyze behaviors of Fig. 4.0.3.

Example 4.2: analyze behaviors of Fig. 4.0.3.

( )out

S a b c

C a b c ab

1. Write out the algebraic expression

2. Formalize the truth table

a b c Cout S

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 00 10 11 00 11 01 01 1

3. Describe the function or behavior of a logic circuit

1-bit full adder

ai

bi

ci

Si

Ci+1

Full Adde

r

This section will present the design process of digital circuits and examples.

Digital circuitsDigital circuits are designed by transforming a word descriptions of function into a set of logic equations and then realizing the equations with logic elements.

The design process for combinational circuits is shown as follows : (see P17-19)

1: Represent each of the inputs and outputs in variable. 2: Formalize the design specification either in the form of truth table or of algebraic expressions. 3: Simplify the description (algebraic expressions) in terms of gates . 4: Implement the circuits with components.

4.1 Design (Synthesis) of Combinational Circuits 组合电路设计（综合）

Example 4.1.1 : Design a full subtracter, that is a circuit which computes a-b-c, where c is the borrow from the next less significant digit and produces a difference , D, and a borrow, P from the next more significant bit. (P275 Solved Problems 1.)  

 (2) logic expression

D=a’b’c+a’bc’+ab’c’+abc P=a’b’c+a’bc’+bc

(1) the truth table

a b c D P0 0 0 0 00 0 1 1 10 1 0 1 10 1 1 0 11 0 0 1 01 0 1 0 01 1 0 0 01 1 1 1 1

Solution 1: (1) showing the truth table (2) simplifying logic expression (3) drawing the logic circuit

(3) logic circuit

ab'c'abc

b

c

bc

D

P

a'

c'a'b'

 (2) logic expression

D=a’b’c+a’bc’+ab’c’+abc P=a’b’c+a’bc’+bc

ab'c'

abc

a'bc'a'b'c

b

c

D

P

?

Solution 2: 

( )

P = a + a +b c bc bc

a b c bc

=1=1

&

&

&&a

bc D

P

bc

D=a’b’c+a’bc’+ab’c’+abcP=a’b’c+a’bc’+bc

( ) ( )

( ) ( )

D = c + c + c + c

= a b c a b c

a b c a b c

a b ab ab

a c

b

b

a

P66 use NAND express NOT

A B C D F 说明0 00 00 00 0

0 00 11 01 1

1111

O→OO→AO→B

O→AB0 10 10 10 1

0 00 11 01 1

0101

A 禁送O

A→AA 禁送

BA→AB

1 01 01 01 0

0 00 11 01 1

0011

B 禁送O

B 禁送A

B→BB→AB

1 11 11 11 1

0 00 11 01 1

0001

AB 禁送O

AB 禁送A

AB 禁送B

AB→AB

表 3-6 真值表 Example 4.1.2 Blood type detect

1.Formalize the truth table

ABCD

00 01 11 10

00

01

图 3-8 输血、受血卡诺图

1 1 1 1

0 1 1 0

11

10

0

0

0

0

1

1

0

1

2.From truth table to k-map

3.Write the logic expression

CBCDDABA

CBCDDABAF

CBCDDABA

CBCDDABAF

A B C D

F

A B C D

F

&

& & & &

11

4. Draw the logic circuit

Exercise : Analyze the function for each of following circuits.

A

B

F1

F2

&

&& &

1

The classification of digit elements (components):1: SSI (small scale integration)—gates

2: MSI (medium scale integration)—single function module

such as Adder, Decode, Encode, Multiplexer

Comparator, ROM,PLA,PAL ,Counter , shift-register

3: LSI (large scale integration)—some functions or

small system

4: VLSI (very large scale integration)—a system

SUM

Carry out

Attention : CI0=0

4.2 Adders ( 加法器）

S3CO

A3 B3 CI

4-bitAdder

S2 S1 S0

A2 A1 A0 B2 B1 B0

4-bits adder integrated （ 4 位加法器）

Example 4.2.1: use of 4-bits adders to realize a 8-bits adder .

S3CO

A3 B3 CI

4- bi tAdder

S2 S1 S0

A2 A1 A0 B2 B1 B0

S3CO

A3 B3 CI

4- bi tAdder

S2 S1 S0

A2 A1 A0 B2 B1 B0

0a7 a4 b7 b4 a3 a0 b3 b0

Co S7 S4 S3 S0

Example 4.2.2: Design a 4-bits subtracter using 4-bits adders and gates to realize it .

From 1.1.4 section ,we knew that (A-B) is computed as (A+(-B)) , thus we take the bit by bit complement of B and then add. The logic circuit is shown as following .

S3CO

A3 B3 CI

ΣS2 S1 S0

A2 A1 A0 B2 B1 B0

1 1 1 1

A

B

Example 4.2.3: Design an adder to add two decimal digits (plus a carry in), where the digits are stored in 8421 code .(Assume that none of the unused combinations of input variables ever occur.) The output is the code for a decimal digit plus the carry out. (see P276)

0011 3 0111 7 1000 8

0101 5 0101 5 1001 9

0 1000 8 0 1100 -- 1 0010 1 2

Sum<=9 0110 6 0110 6

No correction 1 0010 1 2 1 1000 1 8

The logic design for S.P.2

4-Bit Adder

4-Bit Adder

Carry detect

cinBA

c

0

0 0

Cout sum

Carry Detect logic design

c

cout

s2

s1

s3

4.3 Decoders ( 译码器 )

n2

a b 0 1 2 3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

A Decoder is device that, when activated, selects one of several output lines, based on a coded input signal. Most commonly, the input is an n-bit binary number, and there are output lines.example: a two-input (four output) decoder

a b

0

1

2

3

The output is active high

4.3 Decoders ( 译码器 )

Most decoders also have one or more enable inputs. When it is inactive, all of the outputs of the decoder are inactive. In most systems with a single enable input, that input is active low.

En’

a b 0 1 2 3

1 X X 0 0 0 0

0 0 0 1 0 0 0

0 0 1 0 1 0 0

0 1 0 0 0 1 0

0 1 1 0 0 0 1

a

b

0

12

3

En’

1 . The function table of the 74138 decoder (3-to-8 decoder with 3 input lines and 8 output lines)

En1En2’En3’ C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 x x x x x 1 1 1 1 1 1 1 1 x 1 x x x x 1 1 1 1 1 1 1 1 x x 1 x x x 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0

enable inputsEN1=1EN2’=0EN3’=0

Address inputs

active low Outputs输出低电平有效

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

74138

C B A EN1 EN2' EN3'

4.3.1

＆ ＆ ＆ ＆ ＆ ＆ ＆＆

11 1

1 1 1＆

F0 F1F2 F3 F4

F5 F6F7

S1 S2 S3A0 A1 A2

图3-14 74138逻辑图

74138 logic circuit

1

2

3

4

5

7

6

A

B

C

S2

S3

GND

S1

Vcc

Y0

Y1

Y2

Y3

Y5

Y4

8

16

15

14

13

12

10

11

9

Y7

Y6

74138

A0 A1 A2

F0 F1 F2 F3 F4 F5 F6 F7

S3 S2 S1

74138

A A1 A

F0 F1 F2 F3 F4 F5 F6 F7

S3 S2 S1

74138

The pin connection and symbol of 74138

There are many commercial decoder chips as follows:

Notice :The n-to-2n decoder is called full decoder. In order to understand more about active low output

, the example of logic simulation of 2-to-4 decoder is presented.

A0A1 EN'

2-4 DecoderY0 Y1 Y2 Y3Y2

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10Y11Y12Y13Y14Y15

E N 1 ' E N 2 'D C B A

74154

2-to-4decoder4-to-16 decoder

2.BCD to decimal decoder

0 1 2 3 4 5 6 7 8 9

D C B A

BCD to decim al decoder

Active high outputsBCD code Decimal digits DCBA 0123456789 00 0 0 1000000000 00 0 1 010000000000 1 0 0010000000 00 1 1 0001000000 . . . . . . . . . . 10 0 0 000000001010 0 1 000000000110 1 0 0000000000. . . . . . . . . .11 1 1 0000000000

4.3.1

BCD to Decimal decoder implement

1.Formalize the truth table (omit).

2. Draw K-map

0 4 X 8

1 5 X 9

3 7 X X

2 6 X X

ABCD 00 01 11 10

00

01

11

10

3. Algebra expression

0=A’B’C’D’ 1=A’B’C’D

2=B’CD’ 3=B’CD

4=BC’D’ 5=BC’D

6=BCD’ 7=BCD

8=AD’ 9=AD

4.Draw the logic circuit.( 略 )

3.Display Decoder (see P261)Digital watches and other electronic equipment often display BCD-encoded decimal digits on seven-segment displays. ( 七段数码显示管）

Decimal DCB code Display Segmentdigit WXYZ a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 2 0 0 1 0 1 1 0 1 1 0 1 3 0 0 1 1 1 1 1 1 0 0 1 4 0 1 0 0 0 1 1 0 0 1 1 5 0 1 0 1 1 0 1 1 0 1 1 6 0 1 1 0 0 0 1 1 1 1 1 7 0 1 1 1 1 1 1 0 0 0 0 8 1 0 0 0 1 1 1 1 1 1 1 9 1 0 0 1 1 1 1 0 0 1 1

BCD seven-segmentdecoder

a b c d e f g

Z Y X W

a

b

c

d

e

f g

a b c d e f g

4.3.1

4.3.2 Decode application 译码器应用

A common use of the enable function of a decoder is to extend the decoding capability by allowing multiple decoders .

Example 4.3.1: use of 3-to-8 decoders to realize 4-to-16 decoder. (active low outputs)

3-8 decoder: input-3 output-84-16 decoder: input-4 output-16

74138 is a 3-8 decoder, which has one active high enable and two active low enable. We have to use these enable signals to realize 4-16 decoder.

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

74138

C B A EN1 EN2' EN3'

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

74138

C B A EN1 EN2' EN3'

b c d

Y0

1 00 0

Y7 Y8 Y15

a

a b c d Y

0 0 0 0 Y0

0 0 0 1 Y1

0 0 1 0 Y2

0 0 1 1 Y3

0 1 0 0 Y4

0 1 0 1 Y5

0 1 1 0 Y6

0 1 1 1 Y7

1 0 0 0 Y8

1 0 0 1 Y9

1 0 1 0 Y10

1 0 1 1 Y11

1 1 0 0 Y12

1 1 0 1 Y13

1 1 1 0 Y14

1 1 1 1 Y15

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

74138

C B A EN1 EN2' EN3'

4-16 DecoderFunctional Table

4.3.2 Decoder applications Address Decoding ( 地址译码 ) Example 4.3.2: Find the addresses of Y0~Y7 as shown in

Fig.4.3 .

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

74138

A2 A1 A0 S1 S2 S3

A2 A1 A0

A4A7 A5 A6

A3

& ≥ 1

Fig.4.3

AA77 A A66 A A55 A A44 A A33 A A22 A A11 A A00

1 0 1 0 0 1 0 1 0 0 x x xx x xF1 F2

To make 74138 running, To make 74138 running, FF11=1=1, and , and AA33=0=0, and , and FF22=0=0..

FF11=A=A55AA77=1 =1 => => AA55=A=A77=1=1

FF22=A=A44+A+A66=0 =0 => => AA44=A=A66=0=0

Addresses are:

(10100000)2~(10100111)2

or (A0H ~ A7H)

Implement the logic functions using decoder and gates.

Each active high output of a decoder corresponds to a minterm of that function, thus all we need is an OR gate connect to appropriate outputs.

With an active low output decoder, the OR gate is replaced by a NAND (making a NAND-NAND circuit from an AND-OR).

4.3.2 Decoder applications (con.)

Active high output 3-8 decoder truth table

A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Y0=A’B’C’

Y1=A’B’C

Y2=A’BC’

Y3=A’BC

Y4=AB’C’

Y5=AB’C’

Y6=ABC’

Y7=ABC

This is minterm

For example:

realize the following functions using a 74138 decoder and gates

)7,6,5,3,2,1(

)7,4,0(

2

1

mF

mF

74138

A B C

1

1E '2E 3

'E

0Y 7Y

2F1F

4Y

WHY?

10111

10110

01101

01100

01011

01010

01001

10000

f’fabc

Example :Example : Write the expression

f(a,b,c)= ∑m(1,2,3,4,5)f(a,b,c)= ∑m(1,2,3,4,5)

=a’b’c+a’bc’+a’bc+ab’c’+ab’c=a’b’c+a’bc’+a’bc+ab’c’+ab’c=m=m11+m+m22+m+m33+m+m44+m+m55

f ’(a,b,c)= ∑m(0,6,7)f ’(a,b,c)= ∑m(0,6,7)

=m0+m6+m7=m0+m6+m7

f=(f ’)’=(m0+m6+m7)f=(f ’)’=(m0+m6+m7)

=m=m00’m’m66’m’m77’’

=M=M00MM66MM77

=(a+b+c)(a’+b’+c)(a’+b’+c’)=(a+b+c)(a’+b’+c)(a’+b’+c’)

∑∑m(1,2,3,4,5)= Mm(1,2,3,4,5)= M00MM66MM77

MM00=a+b+c=a+b+c

mm00=a’b’c’=a’b’c’

mm00’=(a’b’c’)’’=(a’b’c’)’

=a+b+c=a+b+c =M=M00

MMii=m=mii’’

Example 4.3.4: realize the following functions using a 74138 decoder and gates:

Example 4.3.5: design 1-bit full adder using a 74138 decoder and gates.

There are three examples in P279-4,P280-5 and P281-6

(2,3,6,7))(

(1,2,4,5))(1

Ma,b,cf

ma,b,cf

2

4.4 Encoders and Priority Encoders ( 编码器和优先编码器 )

An encoder is the inverse of a decoder. A decoder’s output code normally has more bits than its input code. If the device’s output code has fewer bits than the input code, the device is usually called an encoder.

For example, use NAND gate to implement 8-3 encoder

I1 I2 I3 I4 I5 I6 I7 I8 F3 F2 F1 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1

真值表

86421 IIIIF 8642 IIII

87432 IIIIF 87653 IIIIF

I1

I2

I3

I4

I5

I6

I7

I8

& & &

F3 F2 F1

8-3 encoder logic circuit

4.4 Encoders and Priority Encoders ( 编码器和优先编码器 )

If more than input can occur at the same time, then some priority must be established. The output would then indicate the number of the highest priority device with an active input. The priorities are normally arranged in descending (or ascending).

The truth table for an eight-input priority encoder is shown in page 244, table 4.6.

For example: SP7

Design a priority encoder with four active high inputs 0,1,2 and 3, and three active high outputs, A and B indicating the number of the highest priority device requesting service, and N, indicating no active requests. Input 0 is the highest priority ( and the 3 is the lowest).

4.54.5 Multiplexers (Data Selectors) Multiplexers (Data Selectors) P245 多路数据选择器

A multiplexer is basically a switch that passes one of its data inputs through to the output, as a function of a set of select inputs. Often, sets of multiplexers are used to choose among several multi bit input numbers.

数据选择器实质上是一个开关，作为一组选择输入的函数，它让某一路输入数据通过，到达输出。经常使用一组数据选择器，从几个多位输入数字中进行选择。

&

&

&

&

&

11

d0

Fd1

d2

d3

A1 A0

.

1. Write out the algebraic expression

0 1 0 1 1 0 2 1 0 3 1 0

0 1 0 1 1 0 2 1 0 3 1 0

0 0 1 1 2 2 3 3

F = ( d A A )( d A A )( d A A )( d A A )

= d (A A )+ d (A A )+ d (A A )+ d (A A )

= d m + d m + d m + d m

2. Formalize the truth table

A1 A0 F

m0 d0

m1 d1

m2 d2

m3 d3

3. The function of this logic diagramMultiplexers

Recall: the combination logic analysis

4.54.5 Multiplexers (Data Selectors) Multiplexers (Data Selectors) P245

多路数据选择器 4.5.1 The function table of a Multiplexer (4-to-1 Multiplexer ) (4 选 1 数选器 )

En’ S1S0 Y1 x x 0 0 0 0 D0

0 0 1 D1

0 1 0 D2

0 1 1 D3a 4-way Multiplexer

Select inputs

Data inputs

active lowEnable input

output

S1

S0

Y

D0 D1 D2 D3

EN'4- to-1

MUX

function table

In general, a multiplexer (also called data selector) is a modular device that selects one of many input lines to appear on a single output line.

From the function table we may write

The selection input code forms the minterms of two variable, S1 and S0. Hence,we may write

D0

D1

D2

D3

Y

S1S0

ii

i DmY

3

0

En’ S1S0 Y1 x x 0 0 0 0 D0

0 0 1 D1

0 1 0 D2

0 1 1 D3

301201101001 )()()()( DSSDSSDSSDSSY

TDDDDmmmmY ][][ 32103210

There are many commercial MUX chips as follow:

8-to-1 MUX two (dual) 4-to-1 MUX

four (qual) two-way MUX (2-to-1MUX)

S0S1

Y

D7D6D5D4D3D2D1D0

S2

EN'74151Y'

S0S1

YA

B3B2B1B0A3A2A1A0

74153YB

ENA'ENB'

S

YA

D1D0C1C0B1B0A1A0

74157YC

EN'

YB YD

4.5.2 Extending the multiplexer capability

Example 4.5.1: use of 4-to-1 MUX to realize 16-to-1 MUX.

A3 A2 A1 A0 Y

0 0 0 0 D0

0 0 0 1 D1

0 0 1 0 D2

0 0 1 1 D3

0 1 0 0 D4

0 1 0 1 D5

0 1 1 0 D6

0 1 1 1 D7

1 0 0 0 D8

1 0 0 1 D9

1 0 1 0 D10

1 0 1 1 D11

1 1 0 0 D12

1 1 0 1 D13

1 1 1 0 D14

1 1 1 1 D15

1. Using A3 and A2 to control four 4-1 MUXs’ enables2. Using A3 and A2 to control four 4-1 MUXs’ outputs

S1

S0

Y

D0 D1 D2 D3

EN'4- to-1

MUX ?Solutions:

Solution 1:decoding to extend

S1

S0

Y2

D4 D5 D6 D7

EN'4-to-1 S1

S0

Y3

D8 D9 D10 D11

EN'4-to-1 S1

S0

Y4

D12 D13 D14 D15

EN'4-to-1S1

S0

Y1

D0 D1 D2 D3

EN'4-to-1

≥1

A0A1 EN'

2-to-4decoder

Y0 Y1 Y2 Y3Y2

0A3 A2

A1

A0

Y

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

Solution 2: selecting to extend

S1

S0

Y2

D4 D5 D6 D7

EN'4-to-1 S1

S0

Y3

D8 D9 D10 D11

EN'4-to-1 S1

S0

Y4

D12 D13 D14 D15

EN'4-to-1S1

S0

Y1

D0 D1 D2 D3

EN'4-to-1A1

A0

S1

S0

Y

D0 D1 D2 D3

EN'4-to-1A2

A30

00 0 0

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

4.5.3 MUX applications Implement the logic functions using MUX and gates.

The expression of 4-to-1 MUX

(1)

The expression of a logic function

(2)

As compared (1) with (2) , we can consider A , B and C as S1 , S0 and Di. We can write

S1=A 、 S0=B

D0=C’ 、 D1=C 、 D2=C 、 D3=C’

301201101001 )()()()( DSSDSSDSSDSSY

CABCBACBACBA

CABCBABCACBAmF

)()()()(

(0,3,5,6)

Can you design a circuit for F using 4-to-1 MUX as above?

S1

S0

Y

D0 D1 D2 D3

EN'4- to-1

F

BA

C1

Gnd

Example 4.5.2: realize the following functions using a 8-to-1 MUX and a 4-to-1 MUX separately.

,7)(1,2,3,4,5mF

Select 8-to-1 MUX, we have

From the function of F, we know that there are 3 variables, (ABC). A 8-to-1 MUX has 3 select inputs, and a 4-to-1 MUX has 2.

10111110

,7)(1,2,3,4,5

76543210

mmmmmmmm

mF

7766554433221100

76543210012

7

0

))((

DmDmDmDmDmDmDmDm

DDDDDDDDAAADmY T

iii

Case 1. Variable select inputs, then data inputs =0 or 1

S0S1

Y

D7D6D5D4D3D2D1D0

S2

EN'74151Y'A

BC

0 1 1 1 1 1 0 1

1

F F’

Case 2. Variable > select inputs, then data inputs = variable or function

Select 4-to-1 MUX, we have

,7)(1,2,3,4,5mF

We have to make 2 variables of ABC become the select inputs of 4-to-1 MUX. Here we select AB=A1A0, thus

0 1 2 3

0 1 1 2 2 3

1 1

F C C C C C C

C

AB AB AB AB AB AB

m m m m m mC C C C C

m C m m m C

3

1 0 0 1 2 3 0 0 1 1 2 2 3 30

( )( )Ti i

i

Y m D A A D D D D m D m D m D m D

(1,2,3,4,5,7)F m

ABC ABC ABC ABC ABC ABC

S1

S0

Y

D0 D1 D2 D3

EN'4-to-1

F

B

A

C

Gnd

1

For example

We have four 3-bit numbers, w2—w0, x2—x0, y2—y0, and z2—z0. We want to select one of these, based on the input s and t( where st=00 selects w, st=01 selects x and so forth). The answer is to appear on output lines f2—f0.

1.use a 74153 multiplexer chip to do this.

2. Use 4-1 multiplexer to do this.

现有 4 个 3 位的数字 , w2—w0, x2—x0, y2—y0, and z2—z0. 需要从中选择一组 , 条件是基于输入 s 和 t( 当 st=00 时选择 w 一组，当 st=01 时选择 x一组，依次类推）。选择的答案显示在一组输出线路上 f2—f0.

1 ）使用 4 选一数据选择器完成该功能

2 ）请使用 74153 芯片完成该功能。

4.6 Three-state gates and open-collector gates 三态门和集电极开路门（ OC ） So far, we never connected the output of one gate to the

output of another gate, since if the two gates were producing opposite values, there would be a conflict. There is a real possibility that one or more of the gates would be destroyed .

There are two design techniques that have been used that do allow us to connect outputs to each other .They are referred as three-state (or tristate) output gates and open-collector( 集电极开路 ) (or OC) gates.

This is dangerous!

a

F=( ab) ' ( cd) 'b

cd

active high enableactive low enable

4.6.1 Three-state gates （三态门） In a three-state gate ,there is an enable input, shown on the side o

f the gate. If that input is active (it could be active high or active low), the gate behaves as usual. If the control input is inactive, the output behaves as if it is not connected (as an open circuit 开路 ).

EN a f 1 x Z 0 0 0 0 1 1

EN a f 0 x Z 1 0 0 1 1 1

Three state buffer

a f

EN

a f

EN

Three-state NAND gate

Three state outputs also exist on other more complex

gates as follow .

&EN

&EN

Three-state AND gate

Three-stateNOT gate

The applications of three-state gates

Realizing a 2-to-1 MUX or wired OR( 线或 )

2-to-1MUX

e F0 b

1 a b

e

aF

Wired-ORF=ae+be’

F

ab

de

cQuestion

F=?

Three-state used for Bus

Display Printer Keys

CPU

A0A1 EN'

2-4 DecoderY0 Y1 Y2 Y3Y210 01 00

Bus

A bus is a set of lines over which data is transferred. The bus itself is really just a set of multiplexers.

4.7 Gate arrays—ROMs, PLAs and PALs 4.7.1 The basic concept on Gate arrays( 门阵列 ) Gate arrays are one approach to the rapid implementation of fa

irly complex systems . They come in several varieties , but all have much in common .The basic structures are illustrated as follow .

AND arrays

OR arrays

Two structures simplified for array gates are shown .

F G

A B

F G

BA

There are three common types of combinational logic arrays.We will discuss them in more detail in the sections later .

A “x” or a dots is represented a connection. Please see example 4.5

4.7.2 ROM( 只读存储器） In a read-only memory (ROM), the AND array is fixed. It is just a decoder, consisting of 2n AND gates .The user can only specify the connections to the OR array. Thus, it produces a sum of minterms. A ROM has one AND gate for each minterm.

Example: F and G functions implemented with ROM is shown right.

F=A’B’+A’B+AB G=A’B’+AB’

F G

A

A'B'

A'B

AB'

AB

B

ROM technologies

PROM -- programmable read-only memory( 可编程 ROM) The user can enter the connections using a special programming dev

ice （编程器） . Unfortunately, ROMs and PROMs can’t be altered once they are

programmed. They must be discarded . EPROM--erasable programmable read-only memory The EPROM is programmed by using a special programming devic

e. The EPROM may then be reprogrammed with new information. However, it can be quickly dissipated by irradiating the chip with an ultraviolet light . （通过在紫外线下照射可以使其内部信息快速消除）。

EEPROM(E2PROM)--electrically erasable, programmable ROM The EEPROM is similar to an EPROM. In an EEPROM the erasure

is done electrically by applying a special voltage to the chip.

Designing with ROM (P253)

To design a system using a ROM , you need only to have a list of miniterms for each function.

Example 4.7.1: Realize following functions using ROM .

)15,11,7,5,1(),,,(

)15,14,10,7,5,4,3(),,,(

)15,11,9,8,7,3(),,,(

DCBAY

DCBAX

DCBAW

The Structure and Capability for Memory(ROM and RAM)

A0

A1

A2

An- 1

W0

W1

W2

W3

W4

W5

W6

D7 D6 D5 D4 D1D3 D2 D0

1 1 1

W2n

-1

n-to-2n

decoder

Addressinputs

words

Data outputs

4.7.4 PLA （可编程逻辑阵列）The most general type is the programmable logic array(PLA). In the PLA, the user specifies the all of the connections (in both AND array and OR array). Thus , we can create any set of sum of products expressions .

F=A’B’+A’B+AB=A’+B

G=A’B’+AB’=B’

F G

A

A'

B

B'

B Both AND array and OR array are programmable.

Designing with PLA (P254-256)

Example 4.7.2: Consider the same example we used to illustrate the ROM and realize following functions using PLA .

( , , , ) (3,7,8,9,11,15)

( , , , ) (3, 4,5,7,10,14,15)

( , , , ) (1,5,7,11,15)

W A B C D

X A B C D

Y A B C D

4.7.4 PAL (Programmable Array Logic 可编程阵列逻辑 )

In a PAL the connections to the OR gates are specified(fixed); the user can determine the AND gate inputs. Each product term can be used only for one of the sums. Each output comes from an OR that has its own group of AND gates connected to it .

Programmable Fixed

Design with PAL

( , , , ) (3,7,8,9,11,15)

( , , , ) (3,4,5,7,10,14,15)

( , , , ) (1,5,7,11,15)

W A B C D

X A B C D

Y A B C D

From the second K-map. We will get: W=AB’C’+A’CD+ACD

X=A’BC’+ACD’+A’CD+BCD

Y=A’C’D+ACD+BCD

From the second K-map. We will get: W=AB’C’+A’CD+ACD

X=A’BC’+ACD’+A’CD+BCD

Y=A’C’D+ACD+BCDA B C D

W

X

Y

Read example 4.9

4.8 Solving Larger Problem 4.8.1 sections will be read by student-self . 4.8.2 An error coding and decoding system(P268)

We are designing two systems that are to be used in conjunction with an error detection and correction scheme . We have 3 bits of information to be coded and transmitted. We will code these into 5-bit words, where the first 3 bits are just the information. The fourth bit is chosen such that there is an odd number of ones in bits 1,3,and 4. The fifth bit is chosen such that there is an odd number of ones in bits 2,3, and 5 .

Bit1 Bit2 Bit3 Bit4 Bit5 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1

要设计两个系统，联合起来用来进行错误检测和校正．我们有３位数据需要编码并传输，将３位数据编码为５位数据，其中前３位代表了要传输的信息，第４位是使１，３，４位具有奇数个１．第５位的选择是使２，３，５位具有奇数个１．

We will design a decoder circuit that takes the 5-bit word (possibly containing an error)-call the bits a,b,c,d,e- and produces one of the words that it could have been- call the answer p, q, r. In addition, there are two outputs to indicate how sure we are that the answer is correct. Output f is 1 if the received word is the same as one of the transmitted,(that is no errors were made); and output g is 1 if the answer is the only data that could have resulted from no errors or a single error.

我们将设计一个解码电路获得 5 位字（可能包含有错误） - 将这五位字叫 a,b,c,d,e. 解码电路产生 3 位信息位，叫做 p,q,r. 同时，解码电路有两个输出用来显示对接受的数字其正确度有多么的确认。当接受到的数字和要传输的数字一致时（即没有错误），输出 f 为 1 ，当接受的数字是由单个错误和没有错误引起的，则输出为 1 。

A block diagram of the system is shown below.

Transmissionmedia

coder

Decoder/corrector

z

yx v

w

x

y

z

a

bc

de

p

qr

fg

Note:Note: When the 5-bit words are transmitted, an error may occur during that transmission. Here, we will design the system under the assumption that at most one error occurs in a 5-bit word. An error results in one of the 1’s changing to a 0, or one of the 0’s changing to a 1.

Solution process: Section 1 : design coder with ROM Step1: List the truth table of coder Step2: realize the logic circuit with ROM

The description of coderThe fourth bit is chosen such that

there is an odd number of ones in bits 1,3,and 4.

The fifth bit is chosen such that there is an odd number of ones

in bits 2,3, and 5 .

x y z v w 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1

truth table of coder

' '

' '

v x z xz

w y z yz

Section 2 : design decoder with ROM When a 5-bit word is received, there are three possibilities. First, no error: If abcde=xyzvw then pqr=xyz, flag f=1,g=1 Second, a single error matches only one transmitted word: If abcde=00111--xyzvw=00011 then pqr=xyz, flag f=0, g=1 Finally, a single error could come from two or more different tran

smitted words : If abcde=00010 --xyzvw=00011 or 01010 then p=x, q=0 or 1, r=z , f

lag f=0, g=0 x y z v w 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1

a b c d e p q r f g0 0 0 0 0 0 0 1 0 10 0 0 0 1 x 0 0 0 00 0 0 1 0 0 x 0 0 00 0 0 1 1 0 0 0 1 10 0 1 0 0 0 0 1 1 10 0 1 0 1 0 x 1 0 00 0 1 1 0 x 0 1 0 00 0 1 1 1 0 0 0 0 10 1 0 0 0 x 1 0 0 0

the truth tablex y z v w0 0 0 1 10 0 1 0 00 1 0 1 00 1 1 0 11 0 0 0 11 0 1 1 01 1 0 0 01 1 1 1 1

Step1: List the truth table of coder .Step2: realize the logic circuit with ROM

10 用 4 选一数据选择器实现下列函数 :F(ABC)=∑(0,2,4,5)F(ABC)= ∑(1,3,5,7)F(ABCD)= ∑(0,3,12,13,14)

作业