Wishbone classic bus cycle

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WISHBONE classic bus cycle

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  • 1. Hanbat Hanbat National National University University WISHBONE Classic BusWISHBONE Classic Bus CycleCycle Gookyi Dennis A. N.Gookyi Dennis A. N. SoC Design Lab.SoC Design Lab. AUGUST.08.2014

2. ContentsContents Classic Bus Cycle Data Organization 2 3. Connection DiagramConnection Diagram Connection diagram 3 CLK_I CLK_I ADR_O() ADR_I() DAT_I() DAT_I() DAT_O() DAT_O() WE_O WE_I SEL_O() SEL_I() STB_O STB_I ACK_I ACK_O CYC_O CYC_I WISHBONEMASTER WISHBONESLAVE 4. Block Read/Write CyclesBlock Read/Write Cycles The block transfer cycle perform multiple data transfer It is most useful when multiple masters are used on an interconnect Use of [CYC_O] signal during block cycles: 4 Asserted for duration of the block cycle Signal must be asserted to hold Access until the end of the cycle MASTERSIGNALS 5. BLOCK READ Cycle: StandardBLOCK READ Cycle: Standard 5 MASTERSIGNALS MASTER presents a valid address on [ADR_O()] MASTER negates [WE_O] to indicate a READ cycle. MASTER presents select [SEL_O()] to indicate where it expects data. MASTER asserts [CYC_O] to indicate the start of the cycle. MASTER asserts [STB_O] to indicate the start of the first phase. SLAVE presents valid data on [DAT_I()] MASTER monitors [ACK_I], and prepares to latch [DAT_I()] MASTER latches data on [DAT_I()] MASTER negates [STB_O] to introduce a wait state (-WSM-). MASTER presents a valid address on [ADR_O()] MASTER negates [WE_O] to indicate a READ cycle. MASTER presents bank select [SEL_O()] to indicate where it expects data. MASTER asserts [STB_O]. SLAVE presents valid data on [DAT_I()] MASTER latches data on [DAT_I()] MASTER terminates cycle by negating [STB_O] and [CYC_O]. 0 54321 6. BLOCK READ Cycle: PipelineBLOCK READ Cycle: Pipeline 6 MASTER presents a valid address on [ADR_O()] MASTER negates [WE_O] to indicate a READ cycle. MASTER presents bank select [SEL_O()] to indicate where it expects data. MASTER asserts [CYC_O] to indicate the start of the cycle. MASTER asserts [STB_O] to indicate the start of the first phase. MASTER monitors [ACK_I], and prepares to latch [DAT_I()] and [TGD_I()]. SLAVE presents valid data on [DAT_I()] MASTER presents a valid address on [ADR_O()] MASTER negates [WE_O] to indicate a READ cycle. MASTER presents bank select [SEL_O()] to indicate where it expects data. MASTER asserts [STB_O] to indicate the start of the second data phase. [STALL_I] during clock cycle 1 causes MASTER to repeat last cycle MASTER prepares latches data on [DAT_I()] MASTER negates [STB_O] MASTER latches data on [DAT_I()] MASTER negates [CYC_O] upon receiving second [ACK_O]. 0 4321 MASTERSIGNALS 7. BLOCK WRITE Cycle: StandardBLOCK WRITE Cycle: Standard 7 MASTER presents a valid address on [ADR_O()] MASTER asserts [WE_O] to indicate a WRITE cycle. MASTER presents bank select [SEL_O()] to indicate where it sends data. MASTER asserts [CYC_O] to indicate the start of the cycle. MASTER asserts [STB_O] to indicate the start of the first phase. SLAVE decodes inputs, and responding SLAVE asserts [ACK_I]. MASTER monitors [ACK_I]. MASTER negates [STB_O] to introduce a wait state (-WSM-). MASTER presents a valid address on [ADR_O()] MASTER asserts [WE_O] to indicate a WRITE cycle. MASTER presents bank select [SEL_O()] to indicate where it sends data. MASTER asserts [CYC_O] to indicate the start of the cycle. MASTER asserts [STB_O] to indicate the start of the second phase. SLAVE decodes inputs, and responding SLAVE asserts [ACK_I]. MASTER monitors [ACK_I]. MASTER terminates cycle by negating [STB_O] and [CYC_O]. 0 1 42 3 5 MASTERSIGNALS 8. BLOCK WRITE Cycle: PipelineBLOCK WRITE Cycle: Pipeline 8 MASTER presents a valid address on [ADR_O()] MASTER asserts [WE_O] to indicate a WRITE cycle. MASTER presents bank select [SEL_O()] to indicate where it expects data. MASTER asserts [CYC_O] to indicate the start of the cycle. MASTER asserts [STB_O] to indicate the start of the first phase. MASTER monitors [ACK_I], and prepares to latch [DAT_I()] and [TGD_I()]. Responding SLAVE asserts [ACK_I]. MASTER presents a valid address on [ADR_O()] MASTER asserts [WE_O] to indicate a WRITE cycle. MASTER presents bank select [SEL_O()] to indicate where it expects data. MASTER asserts [STB_O] to indicate the start of the second data phase. [STALL_I] during clock cycle 1 causes MASTER to repeat last cycle Responding SLAVE asserts [ACK_I]. MASTER negates [STB_O] when [STALL_I] inactive MASTER negates [CYC_O] upon receiving second [ACK_O]. 0 42 31 MASTERSIGNALS 9. RMW CycleRMW Cycle 9 MASTER presents [ADR_O()] MASTER negates [WE_O] to indicate a READ cycle. MASTER presents bank select [SEL_O()] to indicate where it expects data. MASTER asserts [CYC_O] to indicate the start of cycle. MASTER asserts [STB_O]. SLAVE presents valid data on [DAT_I()] MASTER monitors [ACK_I], and prepares to latch [DAT_I()] MASTER latches data on [DAT_I()] MASTER negates [STB_O] to introduce a wait state (-WSM-). MASTER asserts [WE_O] to indicate a WRITE cycle. MASTER presents WRITE data on [DAT_O()] MASTER presents new bank select [SEL_O()] to indicate where it sends data. MASTER asserts [STB_O]. SLAVE latches data on [DAT_O()] MASTER negates [STB_O] and [CYC_O] indicating the end of the cycle. SLAVE negates [ACK_I] in response to negated [STB_O]. 0 321 MASTERSIGNALS 10. Data OrganizationData Organization Data organization refers to the ordering of data during transfers There are two general types of ordering: BIG ENDIAN: MSB is stored in the lowest address LITTLE ENDIAN: MSB is stored in the highest address WISHBONE architecture supports both methods Data transfer nomenclature 10 Nomenclature Granularity Description BYTE(N) 8-bit An 8-bit BYTE transfer at address N WORD(N) 16-bit A 16-bit WORD transfer at address N DWORD(N) 32-bit A 32-bit double WORD transfer at address N QWORD(N) 64-bit A 64-bit quadruple WORD transfer at address N 11. Data OrganizationData Organization To compare BIG and LITTLE ENDIAN data organization, an example is taken below: 64-bit value of 0x0123456789ABCDEF is transferred through BYTE, WORD, DWORD and QWORD ports using both data organization methods 11 12. Data OrganizationData Organization BIG ENDIAN positioning of a 64-bit operand Operand location for input and output port 12 QWORD(0) DWORD(0) DWORD(1) WORD(0) WORD(1) WORD(2) WORD(3) BYTE(0) BYTE(1) BYTE(2) BYTE(3) BYTE(4) BYTE(5) BYTE(6) BYTE(7) DAT_I/DAT_O 0063 BYTE(7 ) BYTE(6 ) BYTE(5 ) BYTE(4 ) BYTE(3 ) BYTE(2 ) BYTE(1 ) WORD(3) WORD(2) WORD(1) WORD(0) DWORD(1) DWORD(0) QWORD(0)0 1 2 3 4 5 6 7 BYTE ORDERING WORD ORDERING DWORD ORDERING QWORD ORDERING ADDRESS 00 00 00 0007 15 31 63 13. Data OrganizationData Organization Variety of BIG ENDIAN transfers over various port sizes 0x0123456789ABCDEF 13 0x01 0x23 0x45 0x67 0x89 0xAB 0xCD 0XEF 0X0123 0X4567 0X89AB 0XCDEF 0X1234567 0X89ABCEDF 0X0123456789ABCDEF0 1 2 3 4 5 6 7 BYTE ORDERING WORD ORDERING DWORD ORDERING QWORD ORDERING ADDRESS 00 00 00 0007 15 31 63 14. Data OrganizationData Organization LITTLE ENDIAN positioning of a 64-bit operand Operand location for input and output port 14 QWORD(0) DWORD(0) DWORD(1) WORD(0) WORD(1) WORD(2) WORD(3) BYTE(0) BYTE(1) BYTE(2) BYTE(3) BYTE(4) BYTE(5) BYTE(6) BYTE(7) DAT_I/DAT_O 0063 BYTE(0 ) BYTE(1 ) BYTE(2 ) BYTE(3 ) BYTE(4 ) BYTE(5 ) BYTE(6 ) WORD(0) WORD(1) WORD(2) WORD(3) DWORD(0) DWORD(1) QWORD(0)0 1 2 3 4 5 6 7 BYTE ORDERING WORD ORDERING DWORD ORDERING QWORD ORDERING ADDRESS 00 00 00 0007 15 31 63 15. Data OrganizationData Organization Variety of LITTLE ENDIAN transfers over various port sizes 0x0123456789ABCDEF 15 0xEF 0xCD 0xAB 0x89 0x67 0x45 0x23 0X01 0XCDEF 0X89AB 0X4567 0X0123 0X89ABCDEF 0X01234567 0X0123456789ABCDEF0 1 2 3 4 5 6 7 BYTE ORDERING WORD ORDERING DWORD ORDERING QWORD ORDERING ADDRESS 00 00 00 0007 15 31 63