AHB WISHBONE BRIDGE

TableofContentsAuthors........................................................................................................................................2Copyright&License....................................................................................................................2RevisionNo................................................................................................................................2Disclaimer....................................................................................................................................2Introduction..................................................................................................................................3LimitationsofDesign..................................................................................................................3Synthesizability............................................................................................................................3PortDefinitions............................................................................................................................4BlockRepresentation...................................................................................................................6Resetoperation............................................................................................................................7WriteCycle..................................................................................................................................8ReadCycle...................................................................................................................................9WritewithWaitstates...............................................................................................................10

InsertedbyWishboneSlave..................................................................................................10InsertedbyAHBMaster.......................................................................................................11

Readwithwaitstates.................................................................................................................13InsertedbyWishboneSlave..................................................................................................13InsertedbyAHBMaster.......................................................................................................14

ReadafterWrite.........................................................................................................................16WriteafterRead.........................................................................................................................17

Authors

TooMuchSemiconductorSolutions(info@toomuchsemi.com)

Copyright&License

Copyright(c)2007TooMuchSemiconductorSolutionsPvtLtd.

RevisionNo.

1.0

Disclaimer

Thissourcefilemaybeusedanddistributedwithoutrestrictionprovidedthatthiscopyrightstatement is not removed from the file and that any derivativework contains the originalcopyrightnoticeandtheassociateddisclaimer.

Thissoftwareisprovidedasisandwithoutany expressorimpliedwarranties,including,but not limited to, the implied warranties of merchantability and fitness for a particularpurpose. in no event shall the author or contributors be liable for any direct, indirect,incidental, special, exemplary, or consequential damages (including, but not limited to,procurement of substitute goods or services; loss of use, data, or profits; or businessinterruption) however caused and on any theory of liability, whether in contract, strictliability,ortort(includingnegligenceorotherwise)arisinginanywayoutoftheuseofthissoftware,evenifadvisedofthepossibilityofsuchdamage.

Introduction

The AHBWishbone bridge is an RTL implementation of a synthesisable bridge tointerconnectAHBMastertoWishboneSlave.

LimitationsofDesign

ThisdesignwillnotworkforSequentialtransfers(ieforwrapandincrementaltypeoftransfers).

Noerror,retryandsplitcaseshavebeenconsideredinthedesign.

Wordsizeis32bits.Itcanbemodifiedasperrequirement.

Alltransfershasbeenconsideredasnonsequentialtype.

Synthesizability

This code is completely synthesizable. The only care that has to be taken is that thewishboneclock(clk_i)andreset(rst_i)signalshavebeenleftunconnectedinsidethedesign.Thewholedesign isworkingonAHBclock and reset signals that shouldbeprovidedbyAHBmaster.

PortDefinitions

PortName Direction

Size Source Description

Hclk in 1 AHBMaster BusClock

Hresetn in 1 AHBMaster ActiveLowSync.Reset

Hwdata in 32 AHBMaster Writedatabus

Hwrite in 1 AHBMaster Read/Writeenable

Hburst in 3 AHBMaster BurstType

Hsize in 3 AHBMaster notused

Htrans in 2 AHBMaster TransferType

Hsel in 1 AHBDecoder Slaveselectsignal

Haddr in 16 AHBMaster Addressbus

dat_i in 32 WBSlave DataBus

ack_i in 1 WBSlave Toindicatecurrenttransferstatus

clk_i in 1 WBSlave unconnected

rst_i in 1 WBSlave unconnected

adr_o out 16 Bridge Addressbus

dat_o out 32 Bridge Databus

cyc_o out 1 Bridge Toindicatevalidbuscycle

we_o out 1 Bridge Read/Writeenable

stb_o out 1 Bridge Toindicatevaliddatatransfercycle

Hrdata out 32 Bridge ReadDataBus

Hresp out 2 Bridge Response

Hready out 1 Bridge Toindicatebridgeisready.

BlockRepresentation

Hclk adr_o

Hresetnwe_o

Hwrite stb_oHaddr

cyc_oHwdata

dat_oHsel

Htrans dat_i

Hburst clk_i

Hready ack_i

Hresp rst_i

Hrdata

AHBWISHBONEBRIDGE

Resetoperation

TheAHBresetsignalisactiveLOWandisusedtoresetthesystemandthebus.Thisresethasbeenassertedanddeassertedsynchronouslyafter the risingedgeofHclk.The reset isrequiredtobeassertedatleastforoneclockcycle(AHBClock).

Fig. 1:Resetoperation

WriteCycle

WhenHwrite isHIGH, this signal indicatesawrite transferand theMasterwillbroadcastdataonthewritedatabus(Hwdata)whenHreadysignalisHIGH.

1) At1stclockedgetheaddress(A1)issampledbytheAHBSlaveonHaddr

2) ThisaddresssampledistransferedsynchronouslytothewishboneSlaveonadr_o.

3) Data(D1)forthisaddressissampledasynchronouslybyAHBSlaveonHwdata.

4) ThisdataiswrittenintotheWISHBONESlaveasynchronouslyondat_obus.

5) At2ndclockedgeaddress(A2)fornexttransferissampledbyAHBSlaveonHaddr.

6) At2ndclockedgeaddress(A1)anddata(D1)issampledbyWISHBONESlaveonadr_oanddat_obusrespectively.

7) At2ndclockedgeack_iisalsoasserted.

Fig 2:WriteCycle

ReadCycle

WhenHwriteisLOW,thissignalindicatesareadtransferandtheMasterwillreceivedataonthereaddatabus(Hrdata)providedtheHreadysignalisHIGH.

1) At1stclockedgetheaddress(A1)issampledbytheAHBSlaveonHaddr.

2) ThisaddresswillbetransferedsynchronouslytoWISHBONESlaveonadr_o.

3) Data(D1)forthisaddressissampledasynchronouslybyWISHBONEMasterondat_i.

4) ThisdataistransferedasynchronouslytoAHBMasteronHrdata.

5) Thisdata(D1)issampledbyAHBMasteron2ndclockedge.

6) At2ndclockedgeaddress(A2)fornexttransferissampledbyAHBSlaveonHaddr.

7) At2ndclockedgeack_iisasserted.

Fig. 3:ReadCycle

WritewithWaitstates

InsertedbyWishboneSlave

1) At1stclockedgetheaddress(A1)issampledbytheAHBSlaveonHaddr2) ThisaddresssampledistransferedsynchronouslytothewishboneSlaveonadr_o.3) Data(D1)forthisaddressistakenasynchronouslybyAHBSlaveafter1stclockedgeon

Hwdata.4) Thisdataislatchedasynchronouslyondat_obus.5) Address(A2)issampledat2ndclockedge.6) Ack_isignalispulledLOWbythewishboneSlaveafter2ndclockedge.7) Hreadysignalispulleddownasynchronously,toindicatethattheAHBSlaveandhence

wishboneSlaveisnotreadytocompleteitscurrenttransfer.8) Address(A3)atnextrisingclockedgeissampledbyAHBSlavewhen ack_iandhence

Hreadyisassertedagain.9) Data(D2)islatchedondat_obuswhenHreadyisasserted.

Fig. 4:WritecyclewithwaitstateinsertedbywishboneSlave

InsertedbyAHBMaster

ThisiswhenAHBMasterisbusy,sothatitcannotcontinueitsnextbustransferoperation.

Fig. 5:WriteCyclewithwaitstateinsertedbyAHBMaster

1) At1stclockedgetheaddress(A1)issampledbytheAHBSlaveonHaddr

2) ThisaddresssampledistransferedsynchronouslytothewishboneSlaveonadr_o.

3) Data(D1)forthisaddressistakenasynchronouslybyAHBSlaveafter1stclockedgeonHwdata.

4) Thisdataislatchedasynchronouslyondat_obus.

5) Address(A2)issampledat2ndclockedge.

6) AssertHtranstobusy(01)after1stclockedge.

7) At2ndclockedgethebridgewillsampletheHtranssignal.

8) Deassertstb_osignalsynchronously.

9) Ack_isignalwillalsobedeassertedasynchronouslybyWishboneSlaveinresponsetostb_osignal.

10) HtransisassertedtoNonSeq(10)transfertypeatclockedgeafterclockedge4

11) At4thclockedgethebridgewillsampletheHtranssignal.

12) Stb_oisassertedsynchronouslyatclockedge4

13) Ack_iisassertedasynchronouslywithresponsetostb_o.

14) Data(D2)islatchedasynchronouslyondat_obus.

15) Address(A3)at5thclockedgeissampledbyAHBSlave

ReadwithwaitstatesInsertedbyWishboneSlave

Fig. 6:ReadcyclewithwaitstateinsertedbywishboneSlave

1) At1stclockedgetheaddress(A1)issampledbytheAHBSlaveonHaddr2) ThisaddresssampledistransferedsynchronouslytothewishboneSlaveonadr_o.3) Data(D1) for this address is latched asynchronously bywishbone Slave after 1st clock

edgeondat_i.4) ThisdataislatchedasynchronouslyonHrdatabus.5) Address(A2)issampledat2ndclockedge.6) Ack_isignalispulledLOWbythewishboneSlaveafter2ndclockedge.7) Hreadysignalispulleddownasynchronously,toindicatethattheAHBSlaveandhence

wishboneSlaveisnotreadytocompleteitscurrenttransfer.8) Address(A3)atnext risingclockedge (6th ) is sampledbyAHBSlavewhenack_i and

henceHreadyisassertedagain.9) Data(D2)islatchedondat_ibusasynchronouslywhenHreadyisasserted.10) Data(D2)islatchedonHrdataasynchronouslyatthesametime.

InsertedbyAHBMaster

ThisiswhenAHBMasterisbusy,sothatitcannotcontinueitsnextbustransferoperation.

Fig. 7:ReadcyclewithwaitstateinsertedbyAHBMaster

1) At1stclockedgetheaddress(A1)issampledbytheAHBSlaveonHaddr

2) ThisaddresssampledistransferedsynchronouslytothewishboneSlaveonadr_o.

3) Data(D1)forthisaddressislatchedasynchronouslybywishboneSlaveafter1stclockedgeondat_i.

4) ThisdataislatchedasynchronouslyonHrdatabus.

5) Address(A2)issampledat2ndclockedge.

6) AssertHtranstobusy(01)after1stclockedge.

7) At2ndclockedgethebridgewillsampletheHtranssignal.

8) Deassertstb_osignalsynchronously.

9) Ack_isignalwillalsobedeassertedasynchronouslybyWishboneSlaveinresponsetostb_osignal.

10) HtransisassertedtoNonSeq(10)transfertypeatclockedgeafterclockedge4

11) At4thclockedgethebridgewillsampletheHtranssignal.

12) ]Stb_oisassertedsynchronouslyatclockedge4

13) Ack_iisassertedasynchronouslyinresponsetostb_o.

14) Address(A3)at5thclockedgeissampledbyAHBSlave

15) Data(D2)islatchedasynchronouslyondat_ibus

16) Data(D2)islatchedasynchronouslyatthesametimeonHrdatabus.

ReadafterWrite1) At1st clock edge the address(A1) is sampledby theAHBSlaveonHaddr alongwith

Hwritesignalandothercontrolsignals.2) ThisaddresssampledistransferedsynchronouslytothewishboneSlaveonadr_o.

3) Data(D1)forthisaddressissampledasynchronouslybyAHBSlaveonHwdata.

4) HwritesignalispulleddowntoLOW(forreadoperation)afterclockedge1.

5) Data(D1)islatchedintotheWISHBONESlaveasynchronouslyondat_obus.

6) At2ndclockedgeaddress(A2)fornexttransferissampledbyAHBSlaveonHaddralongwithHwritesignalandislatchedsynchronouslyonadr_obus.

7) we_osignalispulledLOWsynchronouslyat2ndclockedge.

8) At2ndclockedgeaddress(A1)anddata(D1)issampledbyWISHBONESlaveonadr_oanddat_obusrespectively.

9) WishboneSlavewilllatchdata(D2)foraddress(A2)asynchronouslyondat_ibus

10) Bridgewilllatchdata(D2)asynchronouslyonHrdataatthesametime.

Fig. 8:ReadafterwritecyclewithwaitstateinsertedbyAHBMasterduringwriteoperation

WriteafterRead

1) At1stclockedgetheaddress(A1)issampledbytheAHBSlaveonHaddr.

2) ThisaddresswillbetransferedsynchronouslytoWISHBONESlaveonadr_o.

3) Data(D1)forthisaddressissampledasynchronouslybyWISHBONEMasterondat_i.

4) D1istransferedasynchronouslytoAHBMasteronHrdata

5) HwritesignalispulledtoHIGHlogic(forwriteoperation)after1strisingedgeofclock.

6) Hwritelogicistransferedsynchronouslyonwe_oport.

7) At2ndclockedgeaddress(A2)issampledbyAHBSlavealongwithHwritesignal.

8) A2istransferedsynchronouslyfromHaddrtoadr_o.

9) Bridgetransfersdata(D2)asynchronouslyafter2ndclockedgefromHwdatatodat_o.

Fig. 9:WriteafterReadcyclewithwaitstateinsertedbywishboneSlaveduringreadoperation

AuthorsCopyright & LicenseRevision No.DisclaimerIntroductionLimitations of DesignSynthesizabilityPort DefinitionsBlock RepresentationReset operationWrite CycleRead CycleWrite with Wait statesInserted by Wishbone SlaveInserted by AHB Master

Read with wait statesInserted by Wishbone SlaveInserted by AHB Master

Read after WriteWrite after Read