User guide wishbone serializer

Wishbone serializer

User guide

Version: 0.1

Date: February 25 of 2010.

Author: Rafael Rodríguez (Seven Solutions S.L.)

Wishbone Serializer core

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Revision History

Version Date Notes

0.1 25-02-2011 First Draft

Contents

1. About this guide ....................................................................................................... 3

2. Introduction .............................................................................................................. 3

3. Files and folders structure overview......................................................................... 3

4. Architecture .............................................................................................................. 4

4.1. Wishbone serializer core .................................................................................. 4

4.2. Wishbone control logic..................................................................................... 6

4.3. Asynchronous FIFOs........................................................................................ 6

4.4. TX control logic ............................................................................................... 7

4.5. RX control logic ............................................................................................... 7

4.6. Aurora 8B/10B ................................................................................................. 7

5. Testbench.................................................................................................................. 7

6. Test setup.................................................................................................................. 8


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1. About this guide The Wishbone serializer user guide provides information about implementing,

customizing and simulating the wishbone serializer core.

2. Introduction

Wishbone serializer is an FPGA-core that establishes a transparent Wishbone bridge

between two FPGAs using the high-speed serial GTP transceivers on the Spartan-6

family. This core support the following scenario (fig. 1).

Figure 1.

The figure above is an example showing how wishbone serializer can be used to

communicate simultaneously a Master1 (in A-FPGA) with a Slave1 (in S-FPGA) and a

Master2 (in S-FPGA) with a Slave2 (in A-FPGA). Therefore wishbone serializer data

transfers are initiated either by master cores (in A-FPGA) or master cores (in S-FPGA).

These wishbone interfaces (master and slave) are compatible to wishbone specification

release B4 and operate in pipelined mode.

3. Files and folders structure overview

You can checkout files with the following command: svn co http://svn.ohwr.org/wb-serializer-core

Because this core was intended to be used with Xilinx ISE, the folder /trunk/HDL/ise

contains the ISE project.

You can find all VHDL source files in /trunk/HDL/rtl

The simulation systems for testing the functionality are located in /trunk/HDL/testbench


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The following folder contains the Aurora 8B/10B and FIFO cores /trunk/HDL/IP_cores

These cores have been generated with the Xilinx CORE Generator. Project files are

included so you can customize the cores using the Xilinx CORE Generator Graphical

User Interface (GUI).

The following folder contains the user constraints file (ucf) for the board SP605 /trunk/HDL/par

You can find all docs files in /trunk/doc

4. Architecture

Figure 2 shows the wishbone serializer with its main components.

Figure 2. Block diagram.

4.1. Wishbone serializer core

Figure 3 shows the user interface signals for the wishbone serializer core

(/trunk/hdl/rtl/wbserializer.vhd). Table 1 describes the function of each of the

signals in the interface.


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Figure 3. Top-Level User Interface signals.

Signal Description

wb_clk_i The Wishbone bus is clocked by this clk input (wishbone clk domain).

rst_i Resets the wishbone serializer core.

hard_err_o Hard error detected (Aurora 8B/10B).

soft_err_o Soft error detected in the incoming serial stream (Aurora 8B/10B).

Frame_err_o Channel frame/protocol error detected (Aurora 8B/10B).

lane_up_o Asserted for each lane upon successful lane initialization (Aurora 8B/10B).

channel_up_o Asserted when Aurora 8B/10B channel initialization is complete and

channel is ready to send data. The Aurora 8B/10B core cannot receive data

before CHANNEL_UP.

init_clk_i INIT_CLK is used to register and debounce the GT_RESET signal (Aurora

8B/10B).

gt_reset_in_i The reset signal for the PMA modules in the transceivers is connected to

the top level through a debouncer.

system_rst_o rst_I after internal debouncer.

wb_mst* Wishbone signals (master port).

wb_slv* Wishbone signals (slave port).

rxp_i Positive differential serial data input pin.

rxn_i Negative differential serial data input pin.

txp_o Positive differential serial data output pin.

txn_o Negative differential serial data output pin.

Gtpdo_p_i Positive differential input clock.

Gtpdo_n_i Negative differential input clock.

Table 1. User Interface signals. For more specific information about these signals, you

can see the Xilinx document: ug353.pdf included in the folder /trunk/doc.


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4.2. Wishbone control logic

This block (/trunk/hdl/rtl/wb_control_logic.vhd) acts as a wishbone B4 in

pipelined mode slave and master port on the system bus. The wishbone control logic is

using an external clock (WB clk domain) that can be different from the Aurora 8B/10B

core clock.

The mst_x sends a read request on the slave interface and waits for answer. This

information is sent as a sequence of address + control via the egress FIFO. The received

data (from slv_x) are stocked in the ingress FIFO. Finally, the wishbone control logic

reads data from the ingress FIFO and put this data into the slave interface.

The address space is limited to be able to use one 32 bit word to forward both address

and control information. Table below outline the 32 bit information regarding address

and control signals.

adr_i[26:0] 27

sel_i[3:0] 4

we_i 1

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The mst_x sends a write request on the slave interface and don’t have to wait for

answer. This information is sent as a sequence of (address + control) and data via the

egress FIFO.

Moreover (on the slave interface) from the content in the ingress FIFO (address +

control and data) wishbone bus master clock cycle is generated. Read data are

forwarded to egress FIFO.

In order to distinguish between adr/cmd and data frames, we have added a bit control in

the FIFOs (32 bits + 1 bit control) to mark whether it’s a data or a (addr + control).

In a write transfer, data crosses the serial link in one direction: an address and control

information together with a data array from the mst_x to the slv_x side. In a read

transfer, the address crosses the serial link from the mst_x to the slv_x side and after

this, a data crosses the serial link back from the slv_x to the mst_x side. This has an

huge impact for wishbone masters. Writing through the bridge can be done very fast,

because a wishbone master don’t have to wait until the transfer is finished. But a

wishbone master has to wait for the data while reading through the serial link.

4.3. Asynchronous FIFOs

Because of the two clock domains (wishbone clock domain and Aurora 8B/10B clock

domain), the whole data flow is buffered with asynchronous FIFOs.

In order to increase performance, the core has two FIFOs (egress and ingress) for each

interface (slave or master) (fig.2). Thus, if we have a slow connection (e.g. mst1 to slv2)

this should not affect the other connection (e.g. mst2 to slv1).

This FIFOs have the following features:

- 32 bits data bus + 1 bit control.

- Depth depending on system requirements.


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- Full support for asynchronous write and read clock.

- FIFO empty indicator.

- FIFO full indicator.

- First-Word Fall-Through FIFO Read Operation. The first-word fall-through

(FWFT) feature provides the ability to look-ahead to the next word available

from the FIFO without issuing a read operation.

These cores have been generated with the Xilinx CORE Generator, so you can

customize the cores using the Xilinx CORE Generator Graphical User Interface (GUI).

4.4. TX control logic

This block (/trunk/hdl/rtl/tx_control_logic.vhd) reads content from egress

FIFOs and sends this content via Aurora 8B/10B core. It arbitrates between two FIFOs,

which are connected to the slave interface and the master interface, respectively. This

arbiter is waiting for a request signal from one of these FIFOs and it grants the local link

to the first requester until the end of the cycle. Before an adr/cmd or data frame, the

block add a tag to decode the data accurately. This tag contains information about the

type of data (adr/ctrl or data).

4.5. RX control logic

When this block (/trunk/hdl/rtl/rx_control_logic.vhd) receives a frame from

local link interface, it decodes this information (using the tag added by TX control logic

module) and inserts the data into the appropriate FIFO. RX control logic inserts the data

into the FIFO ingress (master interface) if the data type is addr/ctrl (read transfer) or

addr/ctrl + data (write transfer). Otherwise, RX control logic inserts the data into the

FIFO ingress (slave interface).

4.6. Aurora 8B/10B

Wishbone serializer is based on the Aurora 8B/10B core. This core have been generated

with the Xilinx CORE Generator with framing user data interface, so you can customize

the core using the Xilinx CORE Generator Graphical User Interface (GUI). This user

interface complies with the LocalLink interface specification. The Aurora 8B/10B is

clocked by the GT REFCLK that is a dedicated external clock. For more information

about this core, you can see the Xilinx documents: ds637.pdf and ug353.pdf included in

the folder /trunk/doc.

5. Testbench

As mentioned above, the folder /trunk/HDL/testbench contains all necessary files for

simulating the system:

- main_tb.vhd is a testbench file for simulating the example design. Two

wishbone serializer cores are instantiated and connected in this top level file. In

addition, the system contains two masters and two slaves that perform transfers


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simultaneously. The data is written to the slaves and after that, the data is read

from the same address. If the data is not the same, which was written, an error

message is printed.

- simulate_mti.do is a ModelSim macro file that compiles the example design

sources, the structural simulation model, and the demonstration testbench then

runs the functional simulation to completion.

- mti_wave.do is a ModelSim macro file that opens a wave window.

The Modelsim macro (simulate_mti.do) compiles the example design and testbench,

and adds the relevant signals to the wave window (mti_wave.do). After the design is

compiled and the wave window is displayed the data transfer begins after the

CHANNEL_UP signal is asserted.

The ISE project (/trunk/hdl/ise/wishbone_serializer_core.xise) is ready to

launch the simulation macro (simulate_mti.do). See fig. 4.

Figure 4. Ise project navigator window design (simulation).

6. Test setup

Finally, for the test setup, we have used two boards sp605 (fig. 5). These boards are

connected by SMA-connectors. This configuration is similar to the board “VME FMC

carrier” developed at CERN.

The top level file /trunk/hdl/rtl/test_sp605.vhd contains a example design that

instantiates a master, a slave and the wishbone serializer core.

The master (in the current FPGA) writes an array data into a slave (in other FPGA) via

high speed link (GTP), and after that the master reads the array data from a slave (in the

same address). If a data is not the same, which was written, an error has occurred, then

the test_ok_o signal is deasserted. This signal is connected to a GPIO led (DS3).

If you want to test this example, you must connect two sp605 boards by SMA-

connectors. In addition, you must configure the two FPGAs with this example.


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The ChipScope ICON and ILA cores are added and aid in debugging and validating the

design in boards and are provided with the ISE project (see figure 6).

Example design constraits are included in /trunk/hdl/par/wbserializer.ucf.

Remember to set pin constraits in this file before using the example design on another

board.

Figure 5. Test setup.

Figure 6. Ise project navigator window design (Implementation).

Technology

User guide wishbone serializer