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MICROPROCESSOR&COMPUTER ARCHITECTURE
4CS253 / UE 4CS253
UNIT-2
Session – 6 & 7BASIC PERFORMANCE ISSUES
IN PIPELINE
& PIPELINE HAZARDS
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Pipelining: Its Natural!
• Laundry Example• Amar, Babu, Cathy, Dave
eah have ne lad " lthest #ash, dry, and "ld
• $asher ta%es &' minutes
• Dryer ta%es (' minutes
• )*lder+ ta%es ' minutes
A B C D
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SEQUENTIAL LAUNDR
• -e.uential laundry ta%es / hurs "r ( lads
• I" they learned pipelining, h# lng #uld laundry ta%e0
A
B
C
D
30 40 20 30 40 20 30 40 20 30 40 20
6 PM 7 8 9 10 11 Midnight
T
a
sk
O
r
d
er
Time
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PIPELINED LAUNDR START !OR"ASAP
•
Pipelined laundry ta%es &12 hurs "r ( lads
A
B
C
D
6 PM 7 8 9 10 11 Midnight
T
a
s
k
O
r d
e
r
Time
30 40 40 40 40 20
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PIPELINE THROU#HPUT AND LATENC
I* ID E3 4E4 $B
2 ns ( ns 2 ns 5' ns ( ns
Cnsider the pipeline abve #ith the indiateddelays1 $e #ant t %n# #hat is the pipelinethroughput and the pipeline latency 1
Pipeline thrughput: instrutins mpleted per send1
Pipeline lateny: h# lng des it ta%e t exeute a single instrutin in the pipeline1
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PIPELINE THROU#HPUT AND LATENC
I* ID E3 4E4 $B
2 ns ( ns 2 ns 5' ns ( ns
Pipeline thrughput: h# "ten an instrutin is mpleted1[ ]
[ ]
)(10/1
4,10,5,4,5max/1
)(),(),(),(),(max/1
overhead register pipelineignoring nsinstr
nsnsnsnsnsinstr
WBlat MEM lat EX lat IDlat IF lat instr
=
=
=
Pipeline lateny: h# lng des it ta%e t exeute an instrutin in the pipeline1
nsnsnsnsnsns
WBlat MEM lat EX lat IDlat IF lat L
28410545
)()()()()(
=++++=
++++=
Is this right0
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PIPELINE THROU#HPUT AND LATENC
I* ID E3 4E4 $B
2 ns ( ns 2 ns 5' ns ( ns
-imply adding the latenies t mpute the pipelinelateny, nly #uld #r% "r an islated instrutin
I* 4E4IDI5 L6I57 8 9nsE3 $B4E4IDI*I L6I7 8 &&nsE3 $B
4E4IDI*I&L6I&7 8 &9ns
E3 $B4E4IDI*I(
L6I27 8 (&ns
E3 $B
$e are in truble! he lateny is nt nstant1 his happens beause this is an unbalanedpipeline1 he slutin is t ma%e every state
the same length as the lngest ne1
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PIPELININ# LESSONS
• Pipelining desn;t helplateny " single tas%,
it helps thrughput "entire #r%lad
• Pipeline rate limited bysl#est pipeline stage
• 4ultiple tas%s
peratingsimultaneusly
• Ptential speedup 8Number pipe stages
•
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BASICPERFORMANCEISSUES IN
PIPELINE
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• Pipelining inreases CP< thrughput1
• Des nt redue the exeutin time " an individualinstrutin1
• In "at, it slightly inreases due t verhead in thentrl " the pipeline1
• Prgram ttal exeutin time is dereased1
• i1e1, he prgram exeutes "aster, even thugh nsingle instrutin runs "aster!
• Exeutin time " eah instrutin des ntderease, puts limit n the pratial depth " thepipeline1
• Pipeline Lateny: Limits arise "rm the imbalaneamng the pipeline stages and pipelining verhead1
• Pipeline Imbalane: redues per"rmane as l%
an run n "aster than the time needed "r the
ORMANCE ISSUES - PIPELININ#
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• Pipeline verhead: mbinatin " pipeline register
delay and the l% s%e#1• Pipeline registers delay: add setup time that
triggers a #rite and prpagatin delay t the l%1
• Cl% s%e#: 4aximum delay bet#een #hen the l%
arrives at any t# registers1
ORMANCE ISSUES - PIPELININ#
Pipelin
eregisters
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SPEEDUP FROMPIPELININ# - E$AMPLE
So%'ion(
he average instrutin exeutin time n the unpipelined pressr is
A)e*+,e ins'*'ion e.e'ion 'i/e 0 C%o1
%e 3 A)e*+,e CPI 0 4 ns $ 5 89 : 289; . : 89 . < = 0
> ns
Average instrutin time unpipelined
(1( nsSPEEDUP from pipelining 0
Cnsider the unpipelined pressr in the previus setin1 Assumethat it has a 5ns l% yle and that it uses ( yles "r AL<
peratins and branhes and 2 yles "r memry peratins1 Assumethat the relative "re.uenies " these peratins are ('>, '>, and('>, respetively1 -uppse that due t l% s%e# and setup, pipeliningthe pressr adds '1 ns " verhead t the l%1 Ignring anylateny impat, h# muh speedup in the instrutin exeutin rate#ill #e gain "rm a pipeline0
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• -imple ?I-C pipeline #uld "untin =ne "r integerinstrutins i" every instrutin #ere in@een@en'" every ther instrutin in the pipeline @ I@e+%Pie%ine
• But, in reality instrutins in the pipeline an dependn ne anther Deen@en
• his prevents the next instrutin t exeute duringits designated l% yle1
• his situatins are alled aards1
ELININ# ISSUES
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PIPELININ#HAZARDS
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PIPELINE HAZARDS
• Pipeline Hazards are situatins that prevent the next
instrutin in the instrutin stream "rm exeuting inits designated l% yle1
• aards redue the per"rmane "rm the idealspeedup gained by pipelining1
hree types " haards
– Structural hazards• Arise "rm resure nits #hen the hard#are an;t
supprt all pssible mbinatins " verlappinginstrutins
– Data hazards
• Arise #hen an instrutin depends n the results " aprevius instrutin in a #ay that is expsed byverlapping " instrutin in pipeline
– Control hazards• Arise "rm the pipelining " branhes and ther instrutins
that hange the PC 6Prgram Cunter7
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PIPELINE HAZARDS
• aards in pipeline an ma%e the pipeline t
stall . • Eliminating a haard "ten re.uires that sme
instrutins in the pipeline t be all#ed tpreed #hile thers are delayed1 – $hen an instrutin is stalled, instrutins issued
latter than the stalled instrutin are stpped, #hilethe nes issued earlier must ntinue1
– ther#ise, haard #ill never lear1
• N ne# instrutins are "ethed during the stall1• It is nt mplex as it might sund!
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PERFORMANCE OF
PIPELININ# !ITH STALLS
Average instrutin time unpipelined
SPEEDUP from pipelining 0-----------------------------------------------Average instrutin time pipelined
• A stall auses the pipeline per"rmane t degrade "rm idealper"rmane1
• mpute the atual speedup "rm pipeliningFF11
CPI unpipelined 3 Cl% yle unpipelined 0 -----------------------------------------------------
CPI pipelined 3 Cl% yle pipelined
CPI nie%ine@ C%o1 %e
nie%ine@
0 ----------------------- $--------------------------------- CPI ie%ine@
C%o1 %e ie%ine@
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SPEEDUP FROMPIPELININ# !ITH STALLS • Pipelining dereases the CPI r l% yle time1• raditinal t use CPI t mpare pipelines1•
Assuming that the i@e+% CPI on + ie%ine@ *oesso* is+%/os' +%+s 41
• Cmputatin " pipelined CPI is given by,• CPI ie%ine@ 0 I@e+% CPI : Pie%ine s'+%% %o1 %es
e* ins'*'ion
0 4 : Pie%ine s'+%% %o1 %es e*ins'*'ionIgnring, the yle time verhead " the pipelining andassuming that the pipeline stages are per"etly balaned, thenthe yle time " the t# pressrs an be e.ual1
hen,CPI nie%ine@ C%o1 %e nie%ine@
See@ 0 ----------------------- $--------------------------------- CPI ie%ine@
C%o1 %e ie%ine@
CPI nie%ine@ See@ 0
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SPEEDUP FROM PIPELININ# !ITHSTALLS - CONTINUED
C+se 4 (• A%% ins'*'ions '+1e 'e s+/e n/e* o %es i
eG+%s 'e n/e* oie%ine s'+,es – +%so +%%e@ @e' o 'e ie%ine>
In 'e e+*%ie* +seUnie%ine@ CPI 0 Te @e' o 'e ie%ine o* ie%ine
@e'>
i>e> Pie%ine @e'See@ 0
-------------------------------------------------------------4 : Pie%ine s'+%% %o1 %es e* ins'*'ion
An@i 'e*e +*e no ie%ine s'+%%sTen ie%inin, +n i/*o)e 'e e*o*/+ne 'e @e' o'e ie%ine>
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SPEEDUP FROM PIPELININ# !ITHSTALLS - CONTINUED
C+se 2( I ie%inin, +s i/*o)in, 'e %o1 %e 'i/e 'en i'+n e +ss/e@ '+'
Ten Unie%ine@ CPI 0 Pie%ine@ CPI 0 4>
TsCPI nie%ine@ C%o1 %e
nie%ine@
SPEEDUP from pipelining 0 ----------------------- $--------------------------------- CPI ie%ine@C%o1 %e ie%ine@ 4
C%o1 %e nie%ine@
See@ 0 --------------------------------------------------------------- $
-------------------------- 4 : Pie%ine s'+%% %o1 %es e* ins'*'ionC%o1 %e ie%ine@
Nte: In ases, #here pipe stages are per"etly balaned and n
verhead, the l% yle n the pipelined pressr is smaller
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SPEEDUP FROM PIPELININ# !ITHSTALLS - CONTINUED
C%o1 %e nie%ine@
Clock cycle pipelined 0 --------------------------------- Pie%ine@ @e'
Hene C%o1 %e nie%ine@ Pie%ine@ @e' 0 ------------------------------------------
's %e+@s 'o Clock cycle pipelined
4C%o1 %e nie%ine@
See@ 0 ---------------------------------------------------------------
$------------------------ 4 : Pie%ine s'+%% %o1 %es e* ins'*'ionC%o1 %e ie%ine@
4
See@ 0 --------------------------------------------------------------- $
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SPEEDUP FROM PIPELININ# !ITHSTALLS – PROBLEM 4
4
See@ 0 --------------------------------------------------------------- $Pipeline depth 4 : Pie%ine s'+%% %o1 %es e* ins'*'ion
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STRUCTURAL HAZARDS
• I" ertain mbinatin " instrutins an;t beammdated beause " resure nits, themahine is said t have a structural hazard.
• It an be generated by:
– -me "untinal unit is nt "ully pipelined1
– -me resures has nt been dupliated enugh t
all# all the mbinatins in the pipeline t exeute1
– Ex: A mahine may have nly ne register =le #riteprt, but under ertain nditins, the pipeline might#ant t per"rm t# #rites in ne l% yle @ this #ill
generate strutural haard1• $hen a se.uene " instrutins enunter this haard, the
pipeline #ill stall ne " the instrutins until the re.uired unitis available1
• -uh stalls #ill inrease the Cl% yle Per Instrutin "rm its
ideal 5 "r pipelined mahines1
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STRUCTURAL HAZARDS
•
Cnsider a Gn Neumann arhiteture 6same memry"r instrutins and data7
STRUCTURAL HAZARDS
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STRUCTURAL HAZARDS
• -tall yle added 6mmnly alled pipeline bubble7
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STRUCTURAL HAZARDS
• Anther #ay t represent the stall @ n
instrutin is initiated in l% yle (
Instruction Number
Clock number
1 2 3 4 5 6 8 ! 10
loa" I# I$ %& '%'
Instruction i*1 I# I$ %& '%'
Instruction i*2 I# I$ %& '%'
Instruction i*3 stall I# I$ %& '%'
Instruction i*4 I# I$ %& '%'
Instruction i*5 I# I$ %& '%'
STRUCTURAL HAZARDS
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STRUCTURAL HAZARDS
• A mahine #ithut strutural haard #ill
have l#er CPI• $hy a designer all#s strutural haard0
– redue st•
Pipelining all the "untinal units rdupliating them may be t stly
– redue lateny• Intrduing t many pipeline stages may
ause lateny issues
DATA HAZARDS
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DATA HAZARDS
• Data haards ur #hen the pipeline hanges
the rder " readH#rite aesses t perands sthat the rder diers "rm the rder seen byse.uentially exeuting instrutins n an unpipelined mahine1
• Cnsider the exeutin " "ll#ing instrutins,n ur pipelined example pressr:
– ADD ?5, ?, ?&
– -
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DATA HAZARDS
• he use " results "rm ADD instrutin auses haardsine the register is nt #ritten until a"ter thse
DATA HAZARDS
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DATA HAZARDS
• Eliminate the stalls "r the haard invlving -
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DATA HAZARDS
• -tre re.uires an perand during 4E4 and "r#arding issh#n here1 – he result " the lad is "r#arded "rm the utput in 4E4H$B t
the memry input t be stred
– In additin the AL< utput is "r#arded t AL< input "r address
alulatin "r bth Lad and -tre
DATA HAZARDS CLASSIFICATION
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DATA HAZARDS CLASSIFICATION
• Depending n the rder " read and #rite aess inthe instrutins, data haards uld be lassi=ed as
three types1• Cnsider t# instrutins i and , #ith i urring
be"re 1 Pssible data haards1 – ?A$ 6?ead A"ter $rite7
• tries t read a sure be"re i #rites t it , s inrretly gets
the ld valueM• mst mmn type " haard, that is #hat #e tried t explain s
"ar1
– $A$ 6$rite A"ter $rite7• tries t #rite an perand be"re is #ritten by i1 he #rite ends up
being per"rmed in #rng rder, having i ver#rite the perand#ritten by , the destinatin ntaining the perand #ritten by irather than the ne #ritten by
• Present in pipelines that #rite in mre than ne pipe stage
– $A? 6$rite A"ter ?ead7• tries t #rite a destinatin be"re it is read by i, s the instrutin
i inrretly gets the ne# value• his desn;t happen in ur example, sine all reads are early and
#rites late
DATA HAZARDS REQUIRIN# STALLS
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DATA HAZARDS REQUIRIN# STALLS
•
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DATA HAZARDS REQUIRIN# STALLS
• he lad instrutin an "r#ard the results t AND and? instrutin, but nt t the -
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DATA HAZARDS REQUIRIN# STALLS
• he lad interl% auses a stall t be inserted at l%yle (, delaying the -
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DATA HAZARDS REQUIRIN# STALLS
• Be"re stall insertin
+ 1, 0(2) I# I$ %& '%'
-. 4, 1, 5 I# I$ %& '%'
/N$ 6, 1, I# I$ %& '%'
8, 1, ! I# I$ %& '%'
+ 1, 0(2) I# I$ %& '%'
-. 4, 1, 5 I# I$ stall %& '%'
/N$ 6, 1, I# stall I$ %& '%'
8, 1, ! stall I# I$ %& '%'
• A"ter stall insertin
COMPILER SCHEDULIN# FOR DATA HAZARDS
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COMPILER SCHEDULIN# FOR DATA HAZARDS
• Cnsider a typial de, suh as A 8 B C
+ 1, I# I$ %& '%'
+ 2, C I# I$ %& '%'
/$$ 3, 1, 2 I# I$ stall %& '%'
- /, 3 I# stall I$ %& '%'
• he ADD instrutin must be stalled t all# the lad " C tmplete
• he -$ needs nt be delayed beause the "r#arding hard#arepasses the result "rm 4E4H$B diretly t the data memry input"r string
COMPILER SCHEDULIN# FOR DATA HAZARDS
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COMPILER SCHEDULIN# FOR DATA HAZARDS
• ?ather than ust all# the pipeline t stall,
the mpiler uld try t shedule thepipeline t avid the stalls, by rearrangingthe de – he mpiler uld try t avid the generating
the de #ith a lad "ll#ed by an immediateuse " the lad destinatin register
– his tehni.ue is alled pipeline scheduling r instruction scheduling and it is a very
used tehni.ue in mdern mpilers
INSTRUCTION SCHEDULIN# E$AMPLE
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INSTRUCTION SCHEDULIN# E$AMPLE
• Oenerate de "r ur example pressr
that avids pipeline stalls "rm the "ll#ingse.uene: – A 8 B C – D 8 E *
• -lutin – L$ ?b, B – L$ ?, C – L$ ?e, E M s#ap instrutins t avid stall – ADD ?a, ?b, ? – L$ ?", " – -$ a, ?a M s#ap instrutin t avid stall – -
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Q A
n 2 stage pipeline