Seoul Korea December 9, 2008Seoul Korea December 9, 2008

Assembly and Packaging Assembly and Packaging 20082008

International Technology International Technology Roadmap for Roadmap for

SemiconductorsSemiconductors

... 2

Assembly and Packaging Technical Assembly and Packaging Technical Working Group Participants for 2008Working Group Participants for 2008

W. R. Bottoms, Chair William Chen, Co-chairAbhay Maheshwan - Xilinx George Harman – NIST (retired) Luu Nguyen – National Semi Ryosuke Usui - Sanyo

Bernd Appelt- ASE Gilles Poupon - LETI Mario Bolanos-Avila - TI Sebastian Liau - ITRI

Bernd Roemer- Infineon Harold Hosack - SRC Masao Matsuura - Sony Shigeyuki Ueda - Rohm

Bob Chylak – K&S Henry Utsunomiya – Intercon. Tech. Masashi Otsuka - Toshiba Shoji Uegaki - ASE

Bob Pfahl- iNEMI Hirofumi Nakajima - NEC Max Juergen Wolf - Fraunhofer Shuhya Haruguchi - Sharp

Carl Chen - SPIL Hisao Kasuga - NEC Michitaka Kimura - Renesas Sonjin Cho - Samsung

Charles Reynolds - IBM James Wilcox - IBM Mike Hung - ASE Souvik Banerjee - Linde

Charles Richardson - iNEMI Jie Xue - Cisco Muhannad S. Bakir – Georgia Tech Stan Mihelcic - Easic

Chi-Shih Chang - Retired John Hunt - ASE Namseog Kim - Samsung Steve Bezuk - Kyocera

Choon Heung Lee - Amkor Joseph Adam – StatsChippak Richard Arnold - TI Steve Greathouse - Plexus

Clinton Chao - TSMC Keith Newman - Sun Richard F. Otte - Promex Takanori Kubo - Kyocera

Coen Tak - NXP Kishor Desai – LSI Logic Ricky S W Lee - HKUST Takashi Takata - Panasonic

Debendra Mallik - Intel Klaus Pressel - Infineon Rong-Shen Lee - ITRI Weichung Lo – ITRI

Eiji Yoshida - Fujitsu Lei Mercado - Medtronic Ryo Haruta - Renesas Zhiping Yang - Apple

60 Active participants with representation from Europe, Japan, Korea, Taiwan and the United States

Major Activities Major Activities

Completed System in Package Paper

The next Step in Assembly and Packaging: System Level Integration in the package (SiP)

Published on the ITRS web site

 Held 8 face to face meetings in 6 countries

Began work on major revisions required in 2009

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Rapid Changes in Package Rapid Changes in Package TechnologyTechnology

A gap exists between the time CMOS scaling can no longer maintain progress at Moore’s Law rate and when a new switch is ready.

Packaging innovation is enabling:• equivalent scaling through functional

diversification • density increase through 3D packaging

A new generation of package architectures are needed to support increase in functional density and decrease in cost per function.

New Package Types are New Package Types are Gaining Market shareGaining Market share

-10.00%0.00%10.00%20.00%30.00%40.00%50.00%60.00%70.00%

Perc

ent

Gro

wth

Rat

e

CAAGR 2007-2012

New Packaging Requirements Stimulate New Packaging Requirements Stimulate Development of new Technolofies with Development of new Technolofies with

Difficult ChallengesDifficult Challenges

Typical SiP Typical SiP 20102010

New Packaging Requirements Stimulate New Packaging Requirements Stimulate Development of new Technologies with Development of new Technologies with

Difficult Challenges remainingDifficult Challenges remainingStacked dieWafer level packagingThrough silicon viasEmbedded components (active and passive)

Wafer thinningWafer to wafer bondingDie to wafer bondingNew materialsand more

IC1

IC2

These Technologies are in These Technologies are in Prototype TodayPrototype Today

WL-Assembly die (TSV) to wafer

PCB

IC1 with TSV and Front / Backside RDL

IC2 with Front Side RDL

Tungsten filled TSV: Depth 50 µm

CuSnCu Interconnects

IC2IC1

PCB

Source: Fraunhofer IZM

Applications Applications for New Materials New MaterialsApplications Applications for New Materials New Materials

In this decade most, if not all packaging materials will change due to changing functional and regulatory requirements– Bonding wire– Molding compounds– Underfill– Thermal interface materials– Die attach materials– Substrates– Solder

In the next decade most will change again with the introduction of nanoparticles, new molecules and nanotubes

New MaterialsNew MaterialsNew MaterialsNew Materials

Cu interconnect Ultra Low k dielectrics High k dielectrics Organic semiconductors Green Materials

– Pb free– Halogen free

Many are in use today Many are in development

Nanotubes Nano Wires Macromolecules Nano Particles Composite materials

Difficult Challenges >22nmDifficult Challenges >22nm 9 Categories identified

– Impact of BEOL including Cu/low κ– Wafer level CSP– Co-design and simulation tools– Embedded components– Thinned die issues– Gap between Chip and Package cost trend– High current density packages– Flexibility requirements for packages– 3D packaging

Difficult ChallengesDifficult Challenges Difficult Challenges ≥22 nm Summary of Issues

-Direct wire bond and bump to Cu or improved barrier systems bondable pads

- Dicing for ultra low k dielectric

-Bump and underfill technology to assure low-κ dielectric integrity including lead free solder bump system

-Improved fracture toughness of dielectrics

-Interfacial adhesion

-Reliability of first level interconnect with low κ

-Mechanisms to measure the critical properties need to be developed.

-Probing over copper/low κ

-I/O pitch for small die with high pin count

-Solder joint reliability and cleaning processes for low stand-off

-Wafer thinning and handling technologies

-Compact ESD structures

-TCE mismatch compensation for large die

-Mix signal co-design and simulation environment

-Rapid turn around modeling and simulation

-Integrated analysis tools for transient thermal analysis and integrated thermal mechanical analysis

-Electrical (power disturbs, EMI, signal and power integrity associated with higher frequency/current and lower voltage switching)

-System level co-design is needed now.

-EDA for “native” area array is required to meet the Roadmap projections.

-Models for reliability prediction

-Low cost embedded passives: R, L, C

-Embedded active devices

-Quality levels required not attainable on chip

-Wafer level embedded components

- Wafer/die handling for thin die

- Different carrier materials (organics, silicon, ceramics, glass, laminate core) impact

-Establish infrastructure for new value chain

-Establish new process flows

-Reliability

-Testability

-Different active devices

-Electrical and optical interface integration

Impact of BEOL including Cu/low κ on packaging

Wafer level CSP

Coordinated design tools and simulators to address chip, package, and substrate co-design

Embedded components

Thinned die packaging

Reliability of Low k

EDA

Tools

-System level co-design needed now

-EDA for “native” area array

-Models for reliability prediction

Thin Wafers

-Reliability-Wafer/die handling-Testability

Difficult Challenges ≥ 22 nm Summary of Issues

-Increased wireability at low cost

-Improved impedance control and lower dielectric loss to support higher frequency applications

-Improved planarity and low warpage at higher process temperatures

-Low-moisture absorption

-Increased via density in substrate core

-Alternative plating finish to improve reliability

-Solutions for operation temp up to C5-interconnect density scaled to silicon (silicon I/O density increasing faster than the package substrate technology

-Production techniques will require silicon-like production and process technologies after 2007

-Tg compatible with Pb free solder processing (including rework at260°C)

-Electromigration will become a more limiting factor. It must be addressed through materials changes together with thermal/mechanical reliability modeling.

-Whisker growth

-Thermal dissipation

-Conformal low cost organic substrates

-Small and thin die assembly

-Handling in low cost operation

-Thermal management

-Design and simulation tools

-Wafer to wafer bonding

-Through wafer via structure and via fill process

-Singulation of TSV wafers/die

- Test access for individual wafer/die

-Bumpless interconnect architecture

Close gap between chip and substrate, Improved Organinc

substrates

High current density packages

Flexible system packaging

3D packaging

Difficult ChallengesDifficult Challenges

-Thermal management

-Through wafer via structure and via fill process

- Test access for individual wafer/die

3D Packaging

-Increased wireability at low cost

-Improved planarity and low warpage at higher

process temperatures

-Increased via density in substrate core

Performance

at low Cost

Difficult Challenges <22nmDifficult Challenges <22nm

5 Categories identified– Package cost reduction curve– Small die with high power and pin count– High frequency– System level design capability – Emerging device types

•Organic devices•Nanostructures and materials•Biological interfaces

Difficult Challenges <22 nm Summary of Issues

-Margin in packaging is inadequate to support investment required to reduce cost

-Increased device complexity requires higher cost packaging solutions

These devices may exceed the capabilities of current assembly and packaging technology requiring new solder/UBM with:

-Improved current density capabilities

-Higher operating temperature

-Substrate wiring density to support >20 lines/mm

-Lower loss dielectrics—skin effect above 10 GHz

-“Hot spot” thermal management

There is currently a “brick wall” at five-micron lines and spaces.

-Partitioning of system designs and manufacturing across numerous companies will make required optimization for performance, reliability, and cost of complex systems very difficult.

-Complex standards for information types and management of information quality along with a structure for moving this information will be required.

-Embedded passives may be integrated into the “bumps” as well as the substrates.

-Organic device packaging requirements not yet defined (will chips grow their own packages)

-Biological interfaces will require new interface types

Small die with high pad count and/or high power density

High frequency die

System-level design capability to integrated chips, passives, and substrates

Emerging device types (organic, nanostructures, biological) that

require new packaging technologies

Package cost does not follow the die cost reduction curve

Difficult ChallengesDifficult Challenges

High frequency Die-Lower loss dielectrics

- Skin effect above 10 GHz

- There is currently a “brick wall” at five micron lines and spaces

- “Hot spot” thermal management

Emerging device types (organic, nanostructures, biological) that require

new packaging technologies

The Rapid Pace of Change The Rapid Pace of Change Required Major RevisionsRequired Major Revisions

– Warpage at peak temperature (AP4b) New table added to address warpage

– Package Level System Integration (AP9) Changed to provide quantitative projections

– Technologies and processes for SiP (AP10) Increased detail, segmented by process

– Automotive Operating Environment Specifications (AP21) New table added to address automotive packaging requirements

Warpage is a Major Factor with Warpage is a Major Factor with shrinking pitch, thinner shrinking pitch, thinner

packagespackagesBGA Pitch (mm)

Range of Ball Diameters

(mm)

0.9 -0.18, +0.23 -0.13, +0.23 -0.13, +0.23 -0.13, +0.23 -0.13, +0.23 -0.13, +0.23 -0.13, +0.23 -0.13, +0.23

0.6 -0.17, +0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23

0.6 -0.17, +0.23 -0.12, +0.24 -0.12, +0.24 -0.12, +0.24 -0.12, +0.24 -0.12, +0.24 -0.12, +0.24 -0.12, +0.24

0.4 -0.14, +0.22 -0.11, +0.22 -0.11, +0.22 -0.11, +0.22 -0.11, +0.22 -0.11, +0.22 -0.11, +0.22 -0.11, +0.22

0.55 -0.17, + 0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23 -0.12, +0.23

0.25 -0.1, +0.15 -0.1, +0.15 -0.1, +0.15 -0.1, +0.15 -0.1, +0.15 -0.1, +0.15 -0.1, +0.15 -0.1, +0.15

0.45-0.14 (0.12),

+ 0.22-0.14 (0.12),

+ 0.22-0.13, +0.22 -0.13, +0.22 -0.11, +0.22 -0.11, +0.22 -0.09, +0.22 -0.09, +0.22

0.25-0.096, +

0.22-0.096, +

0.22-0.09, +0.22 -0.09, +0.22 -0.08, +0.22 -0.08, +0.22 -0.68, +0.22 -0.68, +0.22

0.35 -0.11, + 0.2 -0.11, + 0.2 -0.10, +0.20 -0.10, +0.20 -0.09, +0.20 -0.09, +0.20 -0.77, +0.20 -0.77, +0.20

0.25-0.096, +0.22

-0.096, +0.22

-0.09, +0.22 -0.09, +0.22 -0.80, +0.22 -0.80, +0.22 -0.68, +0.22 -0.68, +0.22

0.3 -0.1, +0.17 -0.1, +0.17 -0.95, +0.17 -0.95, +0.17 -0.85, +0.17 -0.85, +0.17 -0.72, +0.17 -0.72, +0.17

0.2 -0.09+0.12 -0.09+0.12 -0.85, +0.12 -0.85, +0.12 -0.77, +0.12 -0.77, +0.12 -0.65, +0.12 -0.65, +0.12

0.8

0.65

0.5

0.4

1.27mm

1

There are standards for room temperature warpage in process through JEDEC. They do not

address the problems at maximum temperature

A section will be added to the 2009 Roadmap to address this in detail

Year of Production 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023

Low cost/Hand held

Max die/SiP 8 9 11 12 13 14 14 14 15 15 16 16 17 17 18 18

package height (8 die stacked)(um)

1.2 1.0 1.0 1.0 1.0 1.0 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.6 0.6 0.6

Max pin count 800 800 900 900 1000 1000 1000 1000 1000 1000 1000 1000.0 1000 1000 1000 1000

Min DAF thickness 15 15 15 15 10 10 10 10 5 5 5 5 5 5 5 5

Min Substrate thickness

180 180 160 160 140 140 100 100 80 80 80 80 80 80 80 80

Min resin thickness over die (wire bond)

150 150 100 100 80 80 70 70 60 60 50 50 50 50 50 50

TSV - 100 100 100 200 200 300 300 400 400 500 700 800 1000 1500 1700

Face to face 2000 2000 4000 4000 5000 5000 6000 6000 6000 6000 6000 6000 7000 7000 7000 7000

Wire bond 50 70 90 120 150 180 210 240 270 300 330 370 400 450 500 530

PoP 160 160 200 200 240 240 240 240 260 260 260 260 280 280 280 280

TSV - 20 20 30 40 60 90 110 120 160 200 400 600 800 900 1000

Face to face 68 100 156 200 340 400 500 550 600 650 700 750 800 850 900 1000

Wire bond 21 21 26 26 26 42 42 42 42 52 52 52 52 52 52 52

PoP 21 21 26 26 26 42 42 42 42 52 52 52 52 52 52 52

TSV 20 15 15 10 10 10 10 8 8 8 8 8 8 8 8 8

Face to face 130 100 100 70 70 50 50 35 35 35 35 35 20 20 20 20

Wire bond 50 40 40 40 30 30 20 20 20 20 20 20 15 15 15 15

PoP (wire) 50 40 40 40 30 30 20 20 20 20 20 20 15 15 15 15

PoP (FC) 100 70 70 50 50 50 50 50 50 50 50 50 35 35 35 35

TSV - 2 3 3 3 4 4 4 4 4 5 7 7 8 8 9

Face to face 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Wire bond 8 10 10 12 12 12 14 14 14 14 16 16 16 16 18 18

PoP 2 2 2 2 3 3 3 3 3 4 4 4 4 4 4 4

High performanceMax die/SiP 6 6 7 7 7 8 8 8 9 9 9 10 10 10 11 11

Max pin count 3190 3350 3509 3684 3860 4053 4246 4458 4670 4904 5138 5394 5651 5934 6231 6543

TSV - 400 400 700 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500

Face to face 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 13000 14000 15000 16000 17000

TSV - 100 100 200 300 500 700 1000 1500 1700 2000 2300 2500 2700 2900 3100

Face to face 68 100 200 400 700 1000 1500 2000 2500 2750 3000 3250 3413 3583 3762 3950

TSV - 50 50 30 30 20 20 20 15 15 13 13 12 12 10 10

Face to face 130 100 70 70 70 50 50 50 50 50 50 50 50 50 50 50

TSV 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8

Face to face 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Max die-to-die bonds/SiP

Max die-to-die bandwidth in SiP

(Gbps)*

Min die thickness (um)

Max die-to-die bonds/SiP

Max die/stack

Max die-to-die bandwidth in SiP

(Gbps)*

Min die thickness (um)

Max die/stack

Package Level System IntegrationPackage Level System Integration

Most of the colored cells are due to cost or thermal management challenges

Automotive PackagingAutomotive PackagingMetric Specification

Automotive Maximum Temperatures

(Ambient Temperatures)

Passenger Compartment

Dashboard, panel +85°C

Hatrack +120°C

Chassis

Isolated areas +85°C

Exposed to heat source +125°C

Transmission

Exposed to heat source +125°C

Exposed to oil/hydraulics +175°C

(today always bare die on ceramic substrate )

Engine Compartment

Moderate areas +125°C

Attached to Engine +155°C

(today always bare die on ceramic substrate )

Storage Range -55°C to 125 °C

Operating Range -40°C to 150°C

-40 to  - 20°C / 300h

-20 to + 20°C / 600h

20 to +130°C / 4000h

130 to +140°C / 1000h

           +150°C / 100h

40g / 10–1000Hz

(depending on customer)

50g / 11ms

(depending on customer)

Typical Mission Profile

Vibration

Mechanical Shock

The rapid growth in hybrid and electric vehicles brings an additional class of electronics and a new subset of environmental conditions that will be addressed in the 2009 Roadmap. This is not reflected in the 2008 table.

Major Changes Planned for Major Changes Planned for 20092009 Expanded coverage of 3D TSV technology

Time table of the introduction of a new generation of materials

Revised warpage treatment to address problems at high temperatures

Expansion of automotive electronics New coverage of packaging problems due to the

transition to 450mm wafers Expanded coverage of new MEMS device types

including a new table Expanded coverage of optical communication, photo

voltaic devices and lighting Increased coordination with other TWGs

THANK YOU THANK YOU