Seoul Korea December 9, 2008 Assembly and Packaging 2008 International Technology Roadmap for Semiconductors

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Seoul Korea December 9, 2008 Assembly and Packaging 2008 International Technology Roadmap for Semiconductors Slide 2 ... 2 Assembly and Packaging Technical Working Group Participants for 2008 W. R. Bottoms, ChairWilliam Chen, Co-chair Abhay Maheshwan - Xilinx George Harman NIST (retired) Luu Nguyen National SemiRyosuke Usui - Sanyo Bernd Appelt- ASEGilles Poupon - LETIMario Bolanos-Avila - TISebastian Liau - ITRI Bernd Roemer- InfineonHarold Hosack - SRCMasao Matsuura - SonyShigeyuki Ueda - Rohm Bob Chylak K&SHenry Utsunomiya Intercon. Tech.Masashi Otsuka - ToshibaShoji Uegaki - ASE Bob Pfahl- iNEMIHirofumi Nakajima - NECMax Juergen Wolf - FraunhoferShuhya Haruguchi - Sharp Carl Chen - SPILHisao Kasuga - NECMichitaka Kimura - RenesasSonjin Cho - Samsung Charles Reynolds - IBMJames Wilcox - IBMMike Hung - ASESouvik Banerjee - Linde Charles Richardson - iNEMIJie Xue - CiscoMuhannad S. Bakir Georgia TechStan Mihelcic - Easic Chi-Shih Chang - RetiredJohn Hunt - ASENamseog Kim - SamsungSteve Bezuk - Kyocera Choon Heung Lee - AmkorJoseph Adam StatsChippakRichard Arnold - TISteve Greathouse - Plexus Clinton Chao - TSMCKeith Newman - SunRichard F. Otte - PromexTakanori Kubo - Kyocera Coen Tak - NXPKishor Desai LSI LogicRicky S W Lee - HKUSTTakashi Takata - Panasonic Debendra Mallik - IntelKlaus Pressel - InfineonRong-Shen Lee - ITRIWeichung Lo ITRI Eiji Yoshida - FujitsuLei Mercado - MedtronicRyo Haruta - RenesasZhiping Yang - Apple 60 Active participants with representation from Europe, Japan, Korea, Taiwan and the United States Slide 3 Major Activities Completed System in Package Paper The next Step in Assembly and Packaging: System Level Integration in the package (SiP) Published on the ITRS web site Held 8 face to face meetings in 6 countries Began work on major revisions required in 2009... 3 Slide 4 Rapid Changes in Package Technology A gap exists between the time CMOS scaling can no longer maintain progress at Moores Law rate and when a new switch is ready. Packaging innovation is enabling: equivalent scaling through functional diversification density increase through 3D packaging A new generation of package architectures are needed to support increase in functional density an d decrease in cost per function. Slide 5 New Package Types are Gaining Market share Slide 6 New Packaging Requirements Stimulate Development of new Technolofies with Difficult Challenges Typical SiP 2010 Slide 7 New Packaging Requirements Stimulate Development of new Technologies with Difficult Challenges remaining Stacked die Wafer level packaging Through silicon vias Embedded components (active and passive) Wafer thinning Wafer to wafer bonding Die to wafer bonding New materials and more Slide 8 IC1 IC2 These Technologies are in Prototype Today WL-Assembly die (TSV) to wafer PCB IC1 with TSV and Front / Backside RDL IC2 with Front Side RDL Tungsten filled TSV: Depth 50 m CuSnCu Interconnects IC2 IC1 PCB Source: Fraunhofer IZM Slide 9 Applications New Materials Applications for New Materials In this decade most, if not all packaging materials will change due to changing functional and regulatory requirements Bonding wire Molding compounds Underfill Thermal interface materials Die attach materials Substrates Solder In the next decade most will change again with the introduction of nanoparticles, new molecules and nanotubes Slide 10 New Materials Cu interconnect Ultra Low k dielectrics High k dielectrics Organic semiconductors Green Materials Pb free Halogen free Many are in use today Many are in development Nanotubes Nano Wires Macromolecules Nano Particles Composite materials Slide 11 Difficult Challenges >22nm 9 Categories identified Impact of BEOL including Cu/low Wafer level CSP Co-design and simulation tools Embedded components Thinned die issues Gap between Chip and Package cost trend High current density packages Flexibility requirements for packages 3D packaging Slide 12 Difficult Challenges Reliability of Low k -Reliability of first level interconnect with low -Interfacial adhesion -Improved fracture toughness of dielectrics EDA Tools -System level co-design needed now -EDA for native area array -Models for reliability prediction Thin Wafers -Reliability -Wafer/die handling -Testability Slide 13 Difficult Challenges -Thermal management -Through wafer via structure and via fill process - Test access for individual wafer/die 3D Packaging -Increased wireability at low cost -Improved planarity and low warpage at higher process temperatures -Increased via density in substrate core Performance at low Cost Slide 14 Difficult Challenges