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REDUNDANT PARALLEL FILTERS
USING ERROR CORRECTION CODES
A PROJECT REPORT
Submitted by
KRISHNA KUMAR.N.S Reg. No.:12BEC065
MOHAN BABU.R Reg. No.:12BEC074
SATHISH KUMAR.A Reg. No.:12BEC237
in partial fulfillment for the award of the degree
of
BACHELOR OF ENGINEERING
IN
ELECTRONICS AND COMMUNICATION
ENGINEERING
KUMARAGURU COLLEGE OF TECHNOLOGY
(An Autonomous Institution Affiliated to Anna University, Chennai)
COIMBATORE-641049
ANNA UNIVERSITY: CHENNAI 600 025
APRIL 2016
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BONAFIDE CERTIFICATE
Certified that this project report titled “REDUNDANT PARALLEL FILTERS
USING ERROR CORRECTION CODES” is the bonafide work of
Mr.N.S.KRISHNA KUMAR [Reg. No.:12BEC065], Mr.R.MOHAN BABU
[Reg. No.:12BEC074], Mr.A.SATHISH KUMAR [Reg. No.: 12BEC237],
who carried out the project work under my supervision. Certified further that to
the best of my knowledge the work reported herein does not form part of any
other project or dissertation on the basis of which a degree or award was
conferred on an earlier occasion on this or any other candidate.
The candidates with Register No.:12BEC065, 12BEC074, 12BEC237 are
examined by us in the Project viva-voce held on............................
INTERNAL EXAMINER EXTERNAL EXAMINER
SIGNATURE
Dr.G.AMIRTHA GOWRI M.E., Ph.D.,
PROJECT SUPERVISOR
Department of ECE
Kumaraguru College of Technology
Coimbatore-641 049
SIGNATURE
Dr.A.VASUKI M.E., Ph.D.,
HEAD OF THE DEPARTMENT
Department of ECE
Kumaraguru College of Technology
Coimbatore-641 049
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ACKNOWLEDGEMENT
We express our sincere thanks to the Management of Kumaraguru College
of Technology and Joint Correspondent Shri.Shankar Vanavarayar for the
kind support and for providing necessary facilities to carry out the project work.
We would like to express our sincere thanks to our beloved Principal
Dr.R.S.Kumar, M.E., Ph.D., Kumaraguru College of Technology, who
encouraged us in the completion of the project.
We would like to thank Dr.A.Vasuki, M.E., Ph.D., Head of the
Department, Electronics and Communication Engineering, for her kind support
and for providing necessary facilities to carry out the project work.
We wish to thank with everlasting gratitude to our Project Coordinator
Mrs.K.Anusha, M.E., AP-I, Department of Electronics and Communication
Engineering for his consistent support throughout the course of this project
work.
We are greatly privileged to express our deep sense of gratitude and
heartfelt thanks to our Project Guide Dr.G.Amirtha Gowri, M.E., Ph.D.,
Department of Electronics and Communication Engineering for his/her expert
counselling and guidance to make this project to a great deal of success and also
we wish to convey our regards to all teaching and non-teaching staff of ECE
Department for their help and cooperation.
Finally, we thank our parents and our family members for giving us the
moral support and abundant blessings in all of our activities and our dear friends
who helped us to endure our difficult times with their unfailing support and
warm wishes.
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ABSTRACT
Filters play a vital role in Digital Signal Processing systems. In data
acquisition and processing applications is common to filter several signals with the
same response. This system uses similar filters with same response. In order to
obtain the reliable operation, the filters are made fault tolerant using the Error
Correction Codes. To achieve the fault tolerance these filters are applied with the
error correction code. The input to the parallel filters is processed with specific
combination using linearity property which in turn produces input for redundant
module. The output of the original filters and the redundant module is checked by
the linearity property for the detection and correction of errors. The output of the
original parallel filters is applied with the same logic as input to recreate another
set of redundant bits which are checked with the output of the actual redundant bits
to detect any error in the system which is corrected by the corresponding equations
to correct the error making the system fault tolerant. However, this system can be
used to correct only single error. The efficient operation in terms provides reduced
processing time with lower power consumption.
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TABLE OF CONTENTS
CHAPTER NO TITLE PAGE NO
ABSTRACT 4
LIST OF FIGURES 6
LIST OF ABBREVIATIONS 7
1 INTRODUCTION 8
2 FIR FILTER 10
2.1 CARRY SELECT ADDER 12
2.2 BAUGH WOOLEY 13
MULTIPLIER
2.3 D FLIP FLOP 14
3 FAULT TOLERANT PARALLEL 15
FILTERS
3.1 ERROR CORRECTION 16
TECHNIQUE
4 IMPLEMNTATION 19
5 RESULTS 21
6 CONCLUSION 23
REFERENCES 24
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LIST OF FIGURES
FIGURE NO TITLE PAGE NO
2.1 Nth
Order FIR Filter 11
2.2 Carry Select Adder 12
2.3 Baugh Wooley Multiplier 13
2.4 D Flip Flop 14
3.1 Block Diagram of Fault Tolerant 15
FIR Filters
4.1 Design Flow 19
4.2 RTL Schematic of 16-tap FIR Filter 20
5.1 Simulation Output 22
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LIST OF ABBREVIATIONS
FIR Finite Impulse Response
DSP Digital Signal Processing
TMR Triple Modular Redundancy
ECC Error Correction Codes
CSA Carry Select Adder
BWM Baugh Wooley Multiplier
FPGA Field Programmable Gate Array
ISE Integrated Simulation Environment
CLB Configurable Logic Block
LUT Look Up Table
ROM Read Only Memory
RAM Random Access Memory
IOB Input Output Block
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CHAPTER 1
INTRODUCTION
Electronic circuits are increasingly present in automotive, medical and space
applications where reliability is critical. In those applications, the circuits have to
provide some degree of fault tolerance. A number of techniques can be used to
protect a circuit from errors. Those range from modifications in the manufacturing
process of the circuits to reduce the number of errors to adding redundancy at the
logic or system level to ensure that errors do not affect the system functionality. To
add redundancy, a general technique known as Triple Modular Redundancy (TMR)
[1] can be used. The TMR, which triplicates the design and adds voting logic to
correct errors, is commonly used. However, it more than triples the area and power
of the circuit, something that may not be acceptable in some applications. When
the circuit to be protected has algorithmic or structural properties, a better option
can be to exploit those properties to implement fault tolerance. Digital filters are
one of the most commonly used signal processing circuits and several techniques
have been proposed to protect them from errors.
Most of them have focused on finite-impulse response (FIR) filters. It is
increasingly common to find systems in which several filters operate in parallel.
This is the case in filter banks and in many modern communication systems. For
those systems, the protection of the filters can be addressed at a higher level by
considering the parallel filters as the block to be protected. Therefore, a significant
cost reduction compared with TMR was obtained. This project provides parallel
filters with redundant module for better fault tolerance. Parallel filters with the
same response that process different input signals are considered. This enables
more efficient implementations when the number of parallel filters is large. This
can also be used to provide more powerful protection using advanced ECCs that
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can correct failures in multiples module.
The parallel FIR filters function on the basis that if any error occurs in any
of the filter structures, the redundant module detects and corrects the error based
on the linearity property. However this project is implemented on correcting one
error. The redundant module consists of another set of parallel filters which
process the different combination of information bits as input which maintains the
properties of specific combination at the output.
The design is implemented in Spartan FPGA XC3S400 kit using Xilinx ISE
13.2. The ISE Design Suite also offers a-la-cart tools to enhance designer
productivity and to provide flexible configurations of the Design Suite Editions.
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CHAPTER 2
FIR FILTER
In signal processing, a finite impulse response (FIR) filter is
a filter whose impulse response (or response to any finite length input) is
of finite duration, because it settles to zero in finite time. The impulse response of
an Nth
order discrete-time FIR filter lasts exactly N + 1 samples (from first non-
zero element through last nonzero element) before it then settles to zero.
FIR filter of order N as shown in fig 2.1, each value of the output sequence
is a weighted sum of the most recent input values as given in equation 2.1
2.1
where,
x[n] is the input signal,
y[n] is the output signal,
N is the filter order; an Nth
order filter has (N+1) terms on the right-hand side,
bi the value of the impulse response at the ith
instant for of an Nth
order
FIR filter.
If the filter is a direct form FIR filter then bi is also a coefficient of the filter.
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Fig 2.1 Nth Order FIR Filter
An FIR filter has a number of useful properties which sometimes make it
preferable to an Infinite Impulse Response (IIR) filter. FIR filters require no
feedback. This means that any rounding errors are not compounded by summed
iterations. The same relative error occurs in each calculation. This also makes
implementation simpler. FIR filters as shown in fig 2.1 are inherently stable, since
the output is a sum of a finite number of finite multiples of the input values, so can
be no greater than times the largest value appearing in the input. FIR filters
can easily be designed to be linear phase by making the coefficient sequence
symmetric. This property is sometimes desired for phase-sensitive applications.
The FIR filters designed uses Carry Select Adder as Adder and Baugh
Wooley Multiplier as Multiplier.
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2.1 CARRY SELECT ADDER
The carry-select adder as shown in fig 2.2 generally consists of two ripple
carry adders and a multiplexer. Adding two n-bit numbers with a carry-select
adder is done with two adders (therefore two ripple carry adders) in order to
perform the calculation twice, one time with the assumption of the carry-in being
zero and the other assuming it will be one. After the two results are calculated,
the correct sum, as well as the correct carry-out, is then selected with the
multiplexer once the correct carry-in is known.
Fig 2.2 Carry Select Adder
The number of bits in each carry select block can be uniform, or variable. In
the uniform case, the optimal delay occurs for a block size of . When variable,
the block size should have a delay, from addition inputs A and B to the carry out,
equal to that of the multiplexer chain leading into it, so that the carry out is
calculated just in time. The delay is derived from uniform sizing, where the
ideal number of full-adder elements per block is equal to the square root of the
number of bits being added, since that will yield an equal number of MUX delays.
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2.2 BAUGH WOOLEY MULTIPLIER
The parallel filters required use of signed multiplication of the filter
coefficients and input data. The concept of a 16 bit 2’s complement Baugh Wooley
multiplier can be shown in fig 2.3
Fig 2.3 Baugh Wooley Multiplier
Older multiplier architectures employed a shifter and accumulator to sum
each partial product, often one partial product per cycle, trading off speed for die
area. Modern multiplier architectures use the Baugh–Wooley algorithm, Wallace
trees, or Dadda multipliers to add the partial products together in a single cycle.
The performance of the Wallace tree implementation is sometimes improved
by modified Booth encoding one of the two multiplicands, which reduces the
number of partial products that must be summed.
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2.2.3 D-FLIP FLOP
The D type flip-flop as shown in fig 2.4 has one data input 'D' and a clock
input. The circuit edge triggers on the clock input. The flip-flop also has two
outputs Q and Q' (where Q' is the reverse of Q).
Fig 2.4 D Flip Flop
The operation of the D type flip-flop is as follows: Any input appearing
(present state) at the input D, will be produced at the output Q in time T+1 (next
state). e.g. if in the present state we have D = 0 and Q = 1, the next state will be D
= anything and Q = 0.
The operation of the D type delays any input by exactly one clock cycle
(given an instantaneous response time i.e. a perfect flip-flop). Cascading several D
type flip-flops together can produce delaying circuits, as used for FIR filter.
The fault tolerance being the key concept is discussed in the next chapter.
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CHAPTER 3
FAULT TOLERANT FIR FILTERS
The parallel filters used are designed to detect multiple errors and correct
single error. The system consists of original module and a redundant module. The
original module comprises of four FIR filters. The redundant module comprises of
three FIR filters. In the original module the applied input gets convoluted by using
its filter coefficients then it generates the convoluted output. The redundant module
is the module used for achieving the reliable operation over the original module.
The redundant module is the parity module which is used to generate the parity
bits[2]. These parity bits are represented as z1, z2, z3 as shown in fig 3.1.
Fig 3.1 Block Diagram of Fault Tolerant FIR Filters
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3.1 Error Correction Technique
This project is based on the use of the Error Correction Codes [ECCs]. A
simple ECC takes a block of k bits and produces a block of n bits by adding n − k
parity check bits[3]. The parity check bits are XOR combinations of the k data bits.
By properly designing those combinations it is possible to detect and correct errors.
As an example, let us consider a simple Hamming code with k = 4 and n = 7. In
this case, the three parity check bits p1, p2, p3 are computed as shown in equations
3.1, 3.2, 3.3 which a function of the data bits d1, d2, d3, d4 as follows:
p1 = d1 ^ d2 ^ d3 3.1
p2 = d1 ^ d2 ^ d4 3.2
p3 = d1 ^ d3 ^ d4 3.3
The data and parity check bits are stored and can be recovered later even if
there is an error in one of the bits. This is done by recomputing the parity check
bits and comparing the results with the values stored. In the example considered,
an error on d1 will cause errors on the three parity checks; an error on d2 only in p1
and p2; an error on d3 in p1 and p3; and finally an error on d4 in p2 and p3.
Therefore, the data bit in error can be located and the error can be corrected. The
single error correction module is used to correct the single bit error in the
generated or convoluted output at the original module. By applying the parity over
the original module the error in the bit at the convoluted output is to be detected
and corrected.
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This is commonly formulated in terms of the generating G and parity check
H matrixes. For the Hamming code considered in the example, the G and H matrix
are given by equations 3.4 and 3.5.
1 0 0 0 1 1 1
G = 0 1 0 0 1 1 0
0 0 1 0 1 0 1 3.4
0 0 0 1 0 1 1
1 1 1 0 1 0 0
H = 1 1 0 1 0 1 0 .
1 0 1 1 0 0 1 3.5
Encoding is done by computing y = x • G and error detection is done by
computing s = y • H T, where the operator • is based on module two addition
(XOR) and multiplication. Correction is done using the vector s, known as
syndrome, to identify the bit in error. The corresponding value of s is to determine
the error position. Once the erroneous bit is identified, it is corrected by simply
inverting the bit.
This ECC scheme can be applied to the parallel filters considered by
defining a set of check filters z j as shown in equations 3.6, 3.7, 3.8. For the case of
four filters
y1, y2, y3, y4 and the Hamming code, the check filters would be
∞
x1[n − l ] + x2[n − l ] + x3[n − l ] · h[l ] 3.6 z1[n] =∑
l=0
∞
x1[n − l ] + x2[n − l ] + x4[n − l ] · h[l ] 3.7 z2[n] =∑
l=0
∞
x1[n − l ] + x3[n − l ] + x4[n − l ] · h[l ] 3.8 z3[n] =∑
l=0
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and the checking is done by testing if
z1[n] = y1[n] + y2[n] + y3[n] 3.9
z2[n] = y1[n] + y2[n] + y4[n] 3.10
z3[n] = y1[n] + y3[n] + y4[n] 3.11
For example, an error on filter y1 will cause errors on the checks of z1, z2,
and z3 as shown in equations 3.9, 3.10, 3.11. Similarly, errors on the other filters
will cause errors on a different group of zi. Therefore, as with the traditional ECCs,
the error can be located and corrected.
For the filters, correction is achieved by reconstructing the erroneous outputs
using the rest of the data and check outputs. For example, when an error on y1, y2,
y3, y4 as given in equations 3.12, 3.13, 3.14 and 3.15 is detected, it can be corrected
by making
yc1[n] = z1[n] − y2[n] − y3[n] 3.12
yc2[n] = z2[n] – y1[n] – y4[n] 3.13
yc3[n] = z3[n] – y1[n] – y4[n] 3.14
yc4[n] = z2[n] – y1[n] – y2[n] 3.15
Similar equations can be used to correct errors on the rest of the data
outputs. The implementation of the design is shown in next chapter.
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CHAPTER 4
IMPLEMENTATION
The design is implemented in Spartan FPGA XC3S400 kit using Xilinx ISE
13.2. Spartan-3 FPGAs [4] are programmed by loading configuration data into
robust reprogrammable static CMOS configuration latches that collectively control
all functional elements and routing resources. Before powering on the FPGA,
configuration data is stored externally in a PROM or some other non-volatile
medium either on or off the board [5]. After applying power, the configuration data
is written to the FPGA using any of five different modes: Master Parallel, Slave
Parallel, Master Serial, Slave Serial, and Boundary Scan. The design flow in Xilinx
is shown in Fig 4.1.
Fig 4.1 Design Flow
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This system consists of four parallel FIR filters which process four 8 bit
words as inputs. The Redundant module consists of three parallel FIR filters which
process three 8 bit inputs that are logic combinations of the inputs of the original
module. Totally seven 8 bit words are obtained as the output of the system. The
four outputs of the original module are used to calculate another set of three 8 bit
redundant words to compare with the outputs of the redundant module. If the
calculated and the obtained redundant bits match, there is no error in the system. If
there is any mismatch in the calculated and the obtained output, then the number of
error equals the number of mismatched bits. The detected 1 bit error is corrected by
corresponding equations which were used to form the redundant combination as
discussed in equations 3.12, 3.13, 3.14, 3.15. The RTL schematic of the 16-tap FIR
filter is shown in fig 4.2.
Fig 4.2 RTL Schematic of 16-tap FIR Filter
However this system is designed to correct only one error and the results are
given in the next chapter.
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CHAPTER 5
RESULTS
The fault tolerant parallel filters are implemented in Spartan FPGA
XC3S400 kit using Xilinx ISE 13.2. Four 8-bit inputs are given and the error is
detected and corrected at the output. The design summary is shown below.
DESIGN SUMMARY
The design summary of the implementation can be given by,
Number of Look Up Tables used - 3523
Number of slice registers used - 1330
Number of Flip flops / Latches used - 246
Number of IOs used - 146
OUTPUT
Four 8-bit data is given as input to the original module which comprises of
four parallel FIR filters. Three 8-bit data are generated by logical combination of
data inputs. Multiplier output is truncated to 16-bit and the following adder is also
truncated to 16 bit. Finally, the output of the FIR filter is 16-bit.
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The output of the Redundant parallel filters is shown in fig 5.1.
Fig 5.1 Simulation Output
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CHAPTER 6
CONCLUSION
This project provides fault tolerance to parallel filters that are commonly
found in modern signal processing circuits. By using linearity property detection
and correction of one error is achieved. In this project, four 8-bit words are given
as input to the system which creates three 8-bit redundant words based on the
linearity property. The output of all the filter structures are checked for errors using
the linearity property with the same combination applied in input. However,
detection and correction of multiple errors is a topic of future work. The approach
is based on applying ECCs to the parallel filters outputs to detect and correct
errors. This project can be used for parallel filters that have the same response and
process different input signals. The technique provides larger benefits when the
number of parallel filters is large. The extension of this project to parallel filters
that have the same input and different impulse responses is future work. The
project can also be combined with the reduced precision replica approach
presented to reduce the overhead required for protection. This will be of interest
when the number of parallel filters is small as the cost of the project is larger in that
case.
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REFERENCES
[1] K.K. Parhi, VLSI Digital Signal Processing systems: Design and
Implementation. New York: Wiley, 1999.
[2] Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, and
Juan Antonio Maestro, “Fault Tolerant Parallel Filters Based on Error Correction
Codes”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems,
1063-8210 © 2014 IEEE.
[3] Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, and Marco
Ottavi, “A Method to Construct Low Delay Single Error Correction Codes for
Protecting Data Bits Only”, IEEE Transactions On Computer-Aided Design Of
Integrated Circuits And Systems, Vol. 32, No. 3, March 2013
[4] Jiang Xiaoyan and Bao Yujun, “FIR Filter Design Based on FPGA”, 2010
International Conference on Computer Application and System Modelling
(ICCASM 2010). [9] Milenko Ciric and Vojkan Radonjic, “Realization of
Multistage FIR Filters Using Pipelining-Interleaving”, Telfor Journal, Vol. 4, No.
2, 2012.
[5] P. Reviriego, C. J. Bleakley, and J. A. Maestro, “Structural DMR: A technique
for implementation of soft-error-tolerant FIR filters,” IEEE Trans. Circuits Syst.,
Exp. Briefs, vol. 58, no. 8, pp. 512–516, Aug. 2011.