Download ppt - Pass Transistor Logic

Presented by-:Diwaker PantME ECE Regular

Introduction.

Advantages of Using pass transistor logics as compared to conventional cmos logic.

Lab work related to Pass transistor logic.

conclusions.

April 10, 2023Pass Transistor Logic 2

In electronics pass transistor logic (PTL) describes several logic families used in the design of integrated circuits.

It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors.

Disadvantage that output levels are always lower than the input level.


In conventional logic families input is applied to gate terminal of transistor but in PTL it is also applied to source /drain terminal.

These circuits act as switches use either NMOS transistors or parallel pair of NMOS and PMOS transistor called Transmission gate.

Here the width of PMOS is taken equal to NMOS so that both transistors can pass the signal simultaneously in parallel.


nMOS passes

• strong ‘0’ • Weak ‘1

pMOS passes

• Strong ‘1’• Weak ‘0’


g

s d

g

s d

g=1 input ‘0’Output Strong ‘0’

g=1 input ‘1’Output weak ‘1’

g=0 input ‘0’Output weak ‘0’

g=0 input ‘1’Output strong ‘1’

Pass transistor logic


g

ba

gb

g=0, gb=1Switch is open

So when g=1

If input is ‘0’ then output will be strong ‘0’.

If input is ‘1’ then output will be strong ‘1’

g=1, gb=0Switch is closed

Fewer devices to implement the logical functions as compared to CMOS.

Example AND gate.


When B is “1”, top device turns on and copies the input A to output F.

When B is low, bottom device turns on and passes a “0”.

Some logical circuits using PTL


This paper compares the use of complementary pass-transistor logic (CPL) as more power-efficient than conventional CMOS design. However, new comparisons performed on more efficient CMOS circuit realizations and demonstrate CPL to be superior to conventional CMOS in most cases with respect to speed, area, and power-delay products. This is basically explained by the fact that CPL gates uses less transistors, have smaller capacitances, and are faster than gates in complementary CMOS. In this paper 2:1 Multiplexer is designed using the conventional CMOS design and CPL logic design and the results are compared using Microwind and DSCH2 CMOS layout tools.

April 10, 2023 10Pass Transistor Logic

VLSI (Very large scale integration) implementation.

Major problems are heat dissipation and power consumptions.

Solutions have been proposed to decrease the power supply voltage, switching frequency and capacitance of transistor.

2:1 MUX by using CMOS and CPL on MICROWIND/ DSCH2.


Any logic function can be realized by NMOS pull-down and PMOS pull-up networks connected between the gate output and the power lines.

Fig. 1 Schematic of 2:1 MUX using CMOS Logic in DSCH2


Timing operation performed on 2:1 MUX conventional CMOS logic design, the rise delay and fall delay calculated is 0.012 ns and 0.012 ns respectively.

Fig.2 Timing diagram and layout structure


PTL has been successfully used to implement digital systems which are smaller, faster, and more energy efficient than static CMOS implementations for the same designs.

Fig.3 Schematic of 2:1 MUX using CPL in DSCH2


Timing operation performed on 2:1 MUX CPL design, the rise delay and fall delay calculated is 0.005 ns and 0.004 ns respectively.

Fig.4 Timing diagram and layout structure


S.N. Parameters Conventional CMOS PASS

TRANSISTOR

LOGIC

1 Width of Layout 21.7 μm (434

lambda)

11.3 μm (226

lambda)

2 Height Of Layout 7.0 μm (140 lambda) 5.8 μm (116

lambda)

3 Surface Area of Layout 151.9 μm2 65.5 μm2

4 Power Consumption 12.204 μW 1.381 μW

5 Rise Delay 0.012 ns 0.005 ns

6 Fall delay 0.012 ns 0.004 ns

7 No. of Transistor

required

12 6



A. P. Chandrakasan and R. W. Brodersen , “Low Power Digital CMOS Design, Kluwer, Norwell MA. 1995.

Neil Weste, Harris & Banerjee, CMOS VLSI Design: A Circuits and

Systems Perspective, 3rd Edition, Pearson Education, Boston, 2005, p1-16.

Zimmermann, R.; Fichtner, W.; “Low-Power Logic Styles: CMOS versus Pass-Transistor Logic” IEEE Transaction on Solid-State Circuits, Volume 32, Page(s) 1079-1090, Publication Year: 1997.

Microwind user manual and DSCH user manual. Retrieved February 2012 from Microwind commercial website: http://www.microwind.net.

Zhou, H.; Aziz, A.; “Buffer Minimization in Pass Transistor Logic”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 20, Page(s ) 693-697, May 2001.


