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Pass Transistor Logic

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Text of Pass Transistor Logic

  • 1. Presented by-:Diwaker PantME ECE Regular

2. IntroductIon. AdvAntAges of usIng pAss trAnsIstor logIcs AscompAred to conventIonAl cmos logIc. lAb work relAted to pAss trAnsIstor logIc. conclusIons. Pass Transistor Logic October 9, 2012 2 3. In electronics pass transistor logic (PTL) describesseveral logic families used in the design of integratedcircuits. It reduces the count of transistors used to makedifferent logic gates, by eliminating redundanttransistors. Disadvantage that output levels are always lower thanthe input level. Pass Transistor Logic October 9, 2012 3 4. In conventional logic families input is applied to gateterminal of transistor but in PTL it is also applied tosource /drain terminal. These circuits act as switches use either NMOStransistors or parallel pair of NMOS and PMOStransistor called Transmission gate. Here the width of PMOS is taken equal to NMOS sothat both transistors can pass the signalsimultaneously in parallel.Pass Transistor Logic October 9, 2012 4 5. nMOS passes g=1 input 0Output Strong 0g g=1 input 1 strong 0 Output weak 1 Weak 1s d pMOS passesg=0 input 0 Output weak 0g Strong 1g=0 input 1s dOutput strong 1 Weak 0Pass Transistor Logic October 9, 2012 5 6. pAss trAnsIstor logIc g g=0, gb=1 g=1, gb=0 Switch is openSwitch is closeda bSo when g=1If input is 0 then output will bestrong 0 .gbIf input is 1 then output will bestrong 1Pass Transistor Logic October 9, 2012 6 7. Fewer devices to implement the logical functions ascompared to CMOS. Example AND gate.When B is 1 , top deviceturns on and copies the inputA to output F.When B is low, bottom deviceturns onand passes a 0 .Pass Transistor Logic October 9, 2012 7 8. Some logical circuits using PTLPass Transistor Logic October 9, 2012 8 9. This paper compares the use of complementary pass-transistor logic (CPL) as more power-efficient than conventional CMOS design. However, new comparisons performed on more efficient CMOS circuit realizations and demonstrate CPL to be superior to conventional CMOS in most cases with respect to speed, area, and power-delay products. This is basically explained by the fact that CPL gates uses less transistors, have smaller capacitances, and are faster than gates in complementary CMOS. In this paper 2:1 Multiplexer is designed using the conventional CMOS design and CPL logic design and the results are compared using Microwind and DSCH2 CMOS layout tools.October 9, 2012 Pass Transistor Logic 10 10. VLSI (Very large scale integration) implementation. Major problems are heat dissipation and power consumptions. Solutions have been proposed to decrease the power supply voltage, switching frequency and capacitance of transistor. 2:1 MUX by using CMOS and CPL on MICROWIND/ DSCH2.October 9, 2012 Pass Transistor Logic 11 11. Any logic function can be realized by NMOS pull-down and PMOS pull-up networks connected between the gate output and the power lines. Fig. 1 Schematic of 2:1 MUX using CMOS Logic in DSCH2October 9, 2012 Pass Transistor Logic 12 12. Timing operation performed on 2:1 MUX conventional CMOS logic design, the rise delay and fall delay calculated is 0.012 ns and 0.012 ns respectively.Fig.2 Timing diagram and layout structureOctober 9, 2012 Pass Transistor Logic 13 13. PTL has been successfully used to implement digital systems which are smaller, faster, and more energy efficient than static CMOS implementations for the same designs.Fig.3 Schematic of 2:1 MUX using CPL in DSCH2October 9, 2012 Pass Transistor Logic 14 14. Timing operation performed on 2:1 MUX CPL design, the rise delay and fall delay calculated is 0.005 ns and 0.004 ns respectively.Fig.4 Timing diagram and layout structureOctober 9, 2012 Pass Transistor Logic 15 15. S.N. Parameters Conventional CMOSPASS TRANSISTOR LOGIC 1Width of Layout21.7 m (434 lambda) 11.3 m (226 lambda) 2Height Of Layout 7.0 m (140 lambda)5.8 m (116 lambda) 3 Surface Area of Layout 151.9 m2 65.5 m2 4Power Consumption12.204 W 1.381 W 5 Rise Delay0.012 ns 0.005 ns 6Fall delay 0.012 ns 0.004 ns 7No. of Transistor required 126October 9, 2012Pass Transistor Logic 16 16. Pass Transistor Logic October 9, 2012 17 17. A. P. Chandrakasan and R. W. Brodersen , Low Power Digital CMOS Design, Kluwer, Norwell MA. 1995. Neil Weste, Harris & Banerjee, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd Edition, Pearson Education, Boston, 2005, p1-16. Zimmermann, R.; Fichtner, W.; Low-Power Logic Styles: CMOS versus Pass-Transistor Logic IEEE Transaction on Solid-State Circuits, Volume 32, Page(s) 1079-1090, Publication Year: 1997. Microwind user manual and DSCH user manual. Retrieved February 2012 from Microwind commercial website: http://www.microwind.net. Zhou, H.; Aziz, A.; Buffer Minimization in Pass Transistor Logic , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 20, Page(s ) 693-697, May 2001.October 9, 2012Pass Transistor Logic 18 18. Pass Transistor Logic October 9, 2012 19 19. Pass Transistor Logic October 9, 2012 20

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