Download ppt - 4x4-bit 2PASCL Multiplier by Nazrul Anuar Nayan

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Two-Phase Clocked Adiabatic Static Two-Phase Clocked Adiabatic Static CMOSCMOS

Logic: Analysis, Application and LSILogic: Analysis, Application and LSIImplementationImplementation

Nazrul Anuar Bin NayanNazrul Anuar Bin Nayan

Sekine and Takahashi Lab.,Sekine and Takahashi Lab.,

Electronics and Information System DivisionElectronics and Information System Division

Graduate School of EngineeringGraduate School of Engineering

Gifu UniversityGifu University

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1.1. IntroductionIntroduction

2.2. Principle of AdiabaticPrinciple of Adiabatic

3.3. Two-Phase Clocked Adiabatic Two-Phase Clocked Adiabatic Static CMOS Logic (2PASCL)Static CMOS Logic (2PASCL)

4.4. Application CircuitsApplication Circuits

5.5. LSI ImplementationLSI Implementation

6.6. Summary and Future WorksSummary and Future Works

Slide 2

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Slide 3

1. Introduction

2. Principle of Adiabatic

3. Two-Phase Clocked Adiabatic Static CMOS Logic (2PASCL)

4. Application Circuits

5. LSI Implementation of 4x4-Bit Multiplier

6. Conclusion and Future Works

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Designer’s dream

1. Portable –increase battery life continuously

2. High-end – avoid cooling packages and reliability issue due to power

Slide 4

Chapter 1 Introduction

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At circuit design levelAt circuit design level Power down the functional blocksPower down the functional blocks Minimize sequential elementsMinimize sequential elements Downsize all non-critical path circuitsDownsize all non-critical path circuits Reduce loading on the clockReduce loading on the clock ParallelismParallelism

To solve dynamic power (drawback: static To solve dynamic power (drawback: static power)power) Process shrinkProcess shrink Voltage scalingVoltage scaling Transistor sizingTransistor sizing

To solve dynamic power (less static power)To solve dynamic power (less static power) Adiabatic (switching) circuitsAdiabatic (switching) circuits

Slide 5


2

2

1ddLr VCw

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Using adiabatic switching

Slide 6


Reduce current flow

Two-phase Clocked Adiabatic Static CMOS Logic (2PASCL)

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Slide 7

charismathics.comtopnews.in

Smart cards

RFIDnec.co.jp

Sensorsnextbigfuture.com

Target:

Low power, low frequency devices


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Static (leakage) ~10%

Short circuit 10~20%

Dynamic 70~80%(>0.18m tech.)

CL

Vdd

Vdd

GND

dynamic current

leakage current

short-circuit current

CL

Vdd

Vdd

GND

dynamic current

leakage current

short-circuit current

Abdollahi, A., Fallah, F., Pedram, M.: Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control. IEEE Transactions on VLSI Systems 12(2), 140–154 (2004)Slide 8


Adiabatic switching --Technology to reduce dynamic power

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CL

VX

Vdd

VY

RP

iP (t)eP (t)

vy(t)

RNiN(t)

vy(0-) = Vdd

Pull-up

Pull-down CL

CL

VX

Vdd

VY

RP

iP (t)eP (t)

vy(t)

RNiN(t)

vy(0-) = Vdd

Pull-up

Pull-down CL

CMOS and its equivalent circuit

Vdd and Vss of CMOS

t0

Vss

eNtVdd

t

eP (t)

Step Voltage

t0

Vss

eNtVdd

t

eP (t)

Step Voltage

Vdd

Vss

Slide 9

Chapter 2 Principle of Adiabatic

cycleclockInput2

1 2

0

2

:T

VC

dt)t(pE

)t(iR)t(p

ddL

Tdiss

PP

en(t)

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0ns 4ns 8ns 12ns 16ns 20ns0.0V

0.5V

1.0V

1.5V

2.0VV(vout2) V(vc)

0ns 4ns 8ns 12ns 16ns 20ns0.0V

0.5V

1.0V

1.5V

2.0VV(vout2) V(vc)

Slide 10


0.18 process 1.2 process

Pull-up network 10 kOhm 3.8 kOhm

Pull-down network

4 kOhm 2.2 kOhm

R14k

C3

1p

C1

1p

PULSE(0 1.8 0n 0.1n 0.1n 50n 100n)

V1

V3

1.8V4

1.8

M1

M2

Vout1

Vout2VX

VC

.tran 0 20n 0n 0.01n

.IC V(VC)=1.8VR14k

C3

1p

C1

1p

PULSE(0 1.8 0n 0.1n 0.1n 50n 100n)

V1

V3

1.8V4

1.8

M1

M2

Vout1

Vout2VX

VC

.tran 0 20n 0n 0.01n

.IC V(VC)=1.8VR1

10k

C3

1p

PULSE(0 1.8 5n 0.1n 0.1n 100n)

V2

C1

1p

PULSE(1.8 0 5n 0.1n 0.1n 50n 100n)

V1

V3

1.8V4

1.8

M3

M4

Vout1

Vout2VX

.tran 0 50n 0n 0.01nR1

10k

C3

1p

PULSE(0 1.8 5n 0.1n 0.1n 100n)

V2

C1

1p

PULSE(1.8 0 5n 0.1n 0.1n 50n 100n)

V1

V3

1.8V4

1.8

M3

M4

Vout1

Vout2VX

.tran 0 50n 0n 0.01n

0ns 10ns 20ns 30ns 40ns 50ns-0.2V

0.3V

0.8V

1.3V

1.8VV(vout1) V(vout2)

0ns 10ns 20ns 30ns 40ns 50ns-0.2V

0.3V

0.8V

1.3V

1.8VV(vout1) V(vout2)

MOS

RN

MOSR1

Pull-up network

Pull-up network

Pull-down network

Pull-down network

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RPiP (t)

eP (t)

vy(t)

RNiN(t)

vy(0-) = Vdd

Pull-up

Pull-down

eN (t)

CL

RPiP (t)

eP (t)

vy(t)

RNiN(t)

vy(0-) = Vdd

Pull-up

Pull-down

eN (t)

CL

Charge transfer without generating heat.

t t

Vdd

eP (t)

t t

Vdd

0

Ramped step voltage

eN (t)

t t

Vdd

eP (t)

t t

Vdd

0

Ramped step voltage

eN (t)

V and V- of adiabatic circuit.

V

Slide 11


V

wr: Energy dissipated at R

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0 2 4 6 8 10

-1

0

1

curr

ent,

i(t)

t[s]

CMOS

ADIABATIC

Pull up Pull down

0 2 4 6 8 100

0.1

0.2

0.3

0.4

0.5

t[s]

Ene

rgy,

w(t

)

wp step

wc step

wr stepwp ramped

wc ramped

wr ramped

Pull up Pull down

Adiabatic charging/discharging reduce the amount of current flow in the circuit

The energy recovery phenomenon is demonstrated in wp ramped voltage supply

t t

Slide 12


tt

wp: Supplied energy at P

wC: Energy accumulated at C

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slow down energy transfer. (t)

Reduce the current flow through transistor

recovering energy from logic (charge recycling)

Slide 13


Clocked AC power supply (height Vdd)

GND of CMOS connected to AC power

Diodes used mainly for recycling charges

Technique

Voltage between current carrying electrodes -> zero when transistor switch on.

Conductor coupling between load capacitor and driver must exist at any time. charges

Requirement

Condition

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During adiabatic switching, all the During adiabatic switching, all the nodes are charged or discharged at nodes are charged or discharged at constant constant current.current.

If the time for the driving voltage to If the time for the driving voltage to change from 0 V to change from 0 V to VddVdd, , ττ is long, is long, power dissipation is nearly power dissipation is nearly zerozero..

Slide 14


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Adiabatic logic

dynamic

2n2p-2n

Method used to create three states;

(released, zero, unity)

static

Differential Operation

QuasiAsymptotically

Split-level pulse driving

1n1p

The approach

1n1p2n2n2pECRL

ADLADCL2PADCL

HCnMOS

2n-2n2DSlide 15


(2PASCL)

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106 107 108

10-8

10-7

10-6

10-5

Pow

er

dis

sip

ati

on [

uW

]V3

1n1p SLP

1n1p quasi

QSERL

2PADCL

2PASCL

CMOS

Transition frequency, 1/T [MHz]106 107 108

10-8

10-7

10-6

10-5

Pow

er

dis

sip

ati

on [

uW

]V3

1n1p SLP

1n1p quasi

QSERL

2PADCL

2PASCL

CMOS

Transition frequency, 1/T [MHz]

Slide 16


Adiabatic inverters which are easily derived from CMOS

T: period of primary signalN: no. of power supplyVP & IP: voltage & current supply

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Slide 17

1. Introduction






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CL

VX

V

V

VY

M3

M4

M2

M1Energy dissipation per

cycle (E2-E1)

E2

E1

Vdd Vdd

0

1

2

0

1

2

Ene

rgy

[fJ]

Ei

V

V

0

1

2

VX

[V

][V

]V

Y [

V]

0 10 20 30-20

0

20

40

Er

Time [ns]

1 cycle

Inverter circuit and the waveforms, simulation using Inverter circuit and the waveforms, simulation using 0.18 0.18 m m CMOS CMOS processprocess

dddd

dddd

VtV

V

VtV

V

4

1)sin(

4

4

3)sin(

4

0

0

Nazrul Anuar, Y. Takahashi, T. Sekine, “Two phase clocked adiabatic staticCMOS logic and its logic family,” J. Semiconductor Technology andScience, vol. 10, no. 1, pp. 1–10, Mar. 2010.

Ei: Energy injected to the circuit

Er: Energy received (recovery)

0.6 / 0.18

0.6 / 0.18

0.6 / 0.18

40 / 40

Split level sinusoidal to reduce the voltage potential of logic while maintaining the Vp-p

Slide 18

Chapter 3 2PASCL

Diodes eliminated at the charging path to increase the amplitude and reduce dissipated energy

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0ns 60ns 120ns 180ns-0.2V

0.8V

1.8V

-0.2V

0.8V

1.8V

-0.2V

0.8V

1.8V

V(y)

V(phi) V(-phi)

V(x)

evaluation hold

evaluation hold

0.0V

0.9V

1.8V1. Evaluation ModeVY LOW - M2 ON CL is charges; output HIGH ( ).

VY HIGH – M1 ON discharging via M1 & M4; output LOW ( ).

2. Hold ModeVY LOW - M2 ON no transition occurs; Y, as

previous state.

VX

VY

V

V

CL

VX

V

V

VY

M3

M4

M2

M1

Vdd Vdd

Slide 19

Chapter 3 2PASCL

Evaluation and Hold Mode

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Slide 20

,5.0

5.05.05.0

2

2

)1,2()1()1(2

tntnpptppptpL

tntnppLtpppLtpL

DMdischrgDd ischrgMchrgP A SC L

VVVVVVC

VVVCVVCVC

EEEE

n : number of power supply,

: constant shape factor

( for sine-shaped current),

T i: period for one cycle.

CL=0.01 pF, Vtp= – 0.58 V, Vtn=0.24 V, V p− p= 0.9 V

Power dissipation without shape factor

(theory) Energy dissipation for triangle

Chapter 3 2PASCL

1 5 10 50 1000.001

0.01

0.1

1

Triangle


Simulation results

Pow

er d

issi

patio

n [

W]

Triangle + Shape factor

22 ddLL VC

T

RCnP

t

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Slide 21

012

(a) Input for 2PASCL and CMOS, VX

0

1

2

Vol

tage

[V

]

(b) Power supply clock, V , V for 2PASCL and for CMOS, V dd

0

1

2

(c) Output waveforms for 2PASCL and CMOS

0 0.1 0.2 0.3 0.40

100

200

(d) Energy supplied and instantaneous energy dissipation for CMOS and 2PASCL. In 2PASCL, energy recovery is shown.

Ene

rgy

diss

. [fJ

]

t [ s]

Supplied Energy (CMOS)

Dissipated Energy (CMOS)

Supplied Energy (2PASCL)

Dissipated Energy (2PASCL)

energy recovery

Chapter 3 2PASCL

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Slide 22

RP

eP (t)

vy(t)

RN

eN (t)

CL

RP

eP (t)

vy(t)

eN (t)

CL

(a) (b)

VDM4 VDM4

Cp-n

W/L is 40/40 W/L is 0.6/0.18

RP

eP (t)

vy(t)

RN

eN (t)

CL

RP

eP (t)

vy(t)

eN (t)

CL

(a) (b)

VDM4 VDM4

Cp-n

W/L is 40/40 W/L is 0.6/0.18

Chapter 3 2PASCL

0

1

2

[V]

VX

0 0.1 0.20

0.20.40.60.8

T [s]

VD

M4

0.51

1.5

VY

V

V

M2

0246

E [

fJ] M4

M1 M3

0

1

2

[V]

VX

0 0.1 0.20.1

0.2

T [s]

VD

M4

0

1

2

VY

V

V

M2

0

5

10

E [

fJ] M1

M3

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Slide 23

a

b

Ｙ

Vdd

V

V

CL

a

Ｙ

b

Vdd

V

V

a

Ｙb

V

Vdd

V

NOR

NAND

XOR

VX

V

V

VY

M3

M4

M2

M1

Vdd Vdd

NOT

Chapter 3 2PASCL

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a

V

V

Ｙ

b

CL

a

b

V

V

ＹCL

a

V

Vb

ＹCL

a

V

V

Ｙ

b

CL

Slide 24

Chapter 3 2PASCL

1st design 2nd design

3rd design 4th design

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Chapter 3 2PASCL

0

1

2

1st

0

1

2

Vp/

0

1

20

1

2

0

1

2

2nd

0

1

2

3rd

4th

0 1 2 3 4 5[10-7]

0

1

2

Time [t]

ab

Vp

[V]

Slide 25

a

V

Vb

ＹCL

4th design

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0 20 40 60 80 1000

2

4NOR

XOR

4-NOT

NAND

4-NOT chain

Pow

er d

issi

pati

on [

W]

CMOS

CMOS

CMOS

CMOS

2PASCL

2PASCL

2PASCL

2PASCL

0

2

4


0

2

4

6

NAND

02468

[10-6]

4-chain NOT4-inverter chain4-NOT4NOTNAND

0 20 40 60 80 1000

2

4NOR

XOR

4-NOT

NAND

4-NOT chainP

ower

dis

sipa

tion

[W

]CMOS

CMOS

CMOS

CMOS

2PASCL

2PASCL

2PASCL

2PASCL

0

2

4


0

2

4

6

NAND

02468

[10-6]

4-chain NOT4-inverter chain4-NOT4NOTNAND

Slide 26

Chapter 3 2PASCL

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Slide 27

1. Introduction






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ObjectivesObjectives

To evaluate the functionality of To evaluate the functionality of 4-bit 4-bit 2PASCL Ripple Carry Adder2PASCL Ripple Carry Adder, and , and 4x4-bit 4x4-bit 2PASCL Multiplier2PASCL Multiplier which has long which has long propagation path.propagation path.

To evaluate their energy dissipation To evaluate their energy dissipation compared to CMOS.compared to CMOS.

Slide 28

Chapter 4 Application Circuits

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S 0S 1S 2S 3

FAFA FA FA CinC2 C1C3C4

b0 a0b1 a1b2 a2b3 a3

M1

1M

12

M1

3M

14

M1

5M

16

M1

7M

18

M1

M2

M3

M4

D2

SIN

E(1

.35

0.4

5 4

0M

EG

-18

.8n

0 0

)

Vp

hi1

D3D

4

M5

M6

M7

M8

M9

M1

0M

19

M2

0

M2

1

M2

2

M2

3

M2

4

D1

D5D

6

M2

5

M2

6M

27

M2

8SIN

E(0

.45

-0.4

5 4

0M

EG

-18

.8n

)

Vp

hi6

D7

D8

M2

9

M3

0

V7

M3

1

M3

2

V8

D9

D1

0

M3

3

M3

4M

35

M3

6

D1

1

D1

2

V1

M3

7M

38

M3

9M

40

M4

1M

42

M4

3M

44

M4

5

M4

6

M4

7

M4

8

D1

3

D1

4

D1

5

M4

9M

50

M5

1M

52

M5

3M

54

M5

5M

56

M5

7

M5

8

M5

9

M6

0

D1

6

D1

7

D1

8

M6

1

M6

2M

63

M6

4

D1

9

D2

0

M6

5

M6

6M

67

M6

8

D2

1

D2

2

M6

9

M7

0M

71

M7

2

D2

3

D2

4

M7

3M

74

M7

5M

76

M7

7M

78

M7

9M

80

M8

1

M8

2

M8

3

M8

4

D2

5

D2

6

D2

7

M8

5M

86

M8

7M

88

M8

9M

90

M9

1M

92

M9

3

M9

4

M9

5

M9

6

D2

8

D2

9

D3

0

M9

7

M9

8

M9

9

M1

00

D3

1

D3

2

M1

01

M1

02

M1

03

M1

04

D3

3

D3

4

M1

05

M1

06

M1

07

M1

08

D3

5

D3

6

M1

09

M1

10

M1

11

M1

12

M1

13

M1

14

M1

15

M1

16

M1

17

M1

18

M1

19

M1

20

D3

7

D3

8

D3

9

M1

21

M1

22

M1

23

M1

24

M1

25

M1

26

M1

27

M1

28

M1

29

M1

30

M1

31

M1

32

D4

0

D4

1

D4

2

M1

33

M1

34

M1

35

M1

36

D4

3

D4

4

M1

37

M1

38

M1

39

M1

40

D4

5

D4

6

M1

41

M1

42

M1

43

M1

44

D4

7

D4

8

C1

0.0

5p

C2

0.0

1p

C3

0.0

1p

ph

i

S

ph

i-

B A

Cin

C o u t

C o u t

S 3

vo

ut

C4

C 3

cin

a

b

s

cout

Full Adder

Spice diagram of 4-bit 2PASCL RCA

Slide 29

4-bit Ripple Carry Adder (RCA)


Spice diagram

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Average of 35% power dissipation reduction in 2PASCL-RCA compared to CMOS-RCA

Slide 30


Input, Power clocks and Output signal 2PASCL-RCA.

0ns 180ns 360ns 540ns0.0V

2.0V0.0V

2.0V0.0V

2.0V0.0V

2.0V0.0V

2.0V0.0V

2.0V

V(s3)

V(c4)

V(phi) V(phi-)

V(c3)

V(b)

V(a)

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HA

HA

HA FA

FA

FA FA

FA

FA HA

FA

FA

a0

b0

a0

b0a1

a2

a3

a3

a3

a0

a2

a0

a1

a1

a2

a1

a3

a2

b2

b3

b0

b1

b1

b1

b1

b2

b2

b3

b3

b2

b3

b0

p2

p3

p4

p5

p6

p1

p0

p7

DFF

DFF

DFF

DFF

DFF

DFF

DFF

DFF


Block diagram. Consists of 16 ANDs, 4 HAs, 8 FAs, and 8 DFFs.Slide 31

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Simulation results using 1.2um CMOS technologySlide 32

02.5

50

2.55

V

02.5

5

Time [ns]

p0p1

p2p3

p4p5

p6p7

a0, b

0a1

, b1

a2, b

2a3

, b3

V[V]

02.5

5

02.5

5

02.5

5

02.5

5

02.5

5

02.5

5

02.5

5

02.5

5

0 100 200 300 400 5000

2.55

1

1

1

1

0

0

0

0

1

1

1

1

(1111)2 X (1111)2

= (11100001)2

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Comparison with CMOS using 1.2 m technology with W/L : 5.0/1.2 mSimulation at 1 to 12 MHz, 2PASCL Multiplier dissipates 55% lower power compared to CMOS.

Slide 33


100 101102

103

104

Transition frequency [MHz]

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uW]

4x4-bit 2PASCL Multiplier

4x4-bit CMOS Multiplier

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Slide 34

1. Introduction






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NORNOT NAND XOR

D-Flip flop 1-bit Half Adder 1-bit Full Adder

Slide 35

Chapter 5 LSI Implementation

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FA

AND

FA

FAFA

FA FA

AND

AND

AND

AND

AND

AND

AND AND AND

AND

HA

HA

HA

AND

AND

AND

AND

FA

HA

FA

DFFs

VV

p0

p1

p2

p3

p4

p5

p6

p7

b0 b1b2 b3

a0

a1

a3

a2

AND

Slide 36


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Slide 37


• ON Semiconductor • 80 I/O • 2.3x2.3 cm Quad Flat

Package (QFP).

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Tech.1.2 μm CMOS 2-metal, 2-polyPower Voltage: 5.0 VCore Size : 1354 (W) × 997 (H) μm2No. of transistors : 992Dynamic Operating : Frequency 50 kHz – 5 MHz Dynamic Power Dissipation: 5.8 mW @ 5 MHz

mulitiplier

4-inverter chain

Slide 38


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Slide 39


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Measurement equipment to examine the functionality of 4x4-bit array 2PASCL Multiplier

Slide 40


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Measurement result to examine the functionality of 4x4-bit array 2PASCL Multiplier @ 1 MHzSlide 41


02.5

5

02.5

5P0

02.5

5P2

02.5

5P3

02.5

5P4

02.5

5

Vol

tage

[V

]

P5

-1 0 10

2.55

T [s]

P7

02.5

5P1

02.5

5P6

(a) Output signals without D-Flipflop (b) Output signals with D-Flip flop

02.5

5 X DFF-CLK

02.5

5 P0

02.5

5 P2

02.5

5 P3

02.5

5 P4

02.5

5

Vol

tage

[V

]

P5

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.80

2.55

T [s]

P7

02.5

5 P1

02.5

5 P6

1

1

1

1

0

0

0

0

1

(1111)2 X (1111)2

= (11100001)2

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Slide 42


0.05 0.1 0.5 1 5 10

0.05

0.1

0.5

1

5

10

CMOS (simulation)

2PASCL (measurement)

2PASCL (simulation)

Input Frequency [MHz]

Pow

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mW

]

2PADCL (measurement) [14]

2PADCL (simulation)

0.05 0.1 0.5 1 5 10

0.05

0.1

0.5

1

5

10

CMOS (simulation)

2PASCL (measurement)

2PASCL (simulation)

Input Frequency [MHz]

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mW

]

2PADCL (measurement) [14]

2PADCL (simulation)

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Slide 43

1. Introduction





6. Summary and Future Works

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From simulation results, 4-bit 2PASCL ripple carry adder (RCA) and From simulation results, 4-bit 2PASCL ripple carry adder (RCA) and 4x4-bit 2PASCL multiplier dissipates 35% and 77% lower power than 4x4-bit 2PASCL multiplier dissipates 35% and 77% lower power than CMOS respectively.CMOS respectively.

As for the measurement results, compared to the 2PADCL As for the measurement results, compared to the 2PADCL multiplier, the 2PASCL multiplier reduces the power dissipation by multiplier, the 2PASCL multiplier reduces the power dissipation by 55%.55%.

Dynamic power dissipation was reduced using 2PASCL topology Dynamic power dissipation was reduced using 2PASCL topology and it is advantageous for low-power digital applicationand it is advantageous for low-power digital application

Slide 44

Chapter 5 Conclusion & Future Works

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Chip design and fabrication using 45nm process to focus on the leakage power dissipation.

Smart card prototype as the application.

Prototype RISC CPU using 0.18 m 2PASCL topology which targeting 0.23 mW/MHz.

Slide 45

Chapter 5 Conclusion & Future Works

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Thank you for your Thank you for your kind attention!kind attention!