4x4-bit 2PASCL Multiplier by Nazrul Anuar Nayan

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Text of 4x4-bit 2PASCL Multiplier by Nazrul Anuar Nayan

  • 1. Two-Phase Clocked Adiabatic Static CMOS Logic: Analysis, Application and LSI Implementation Nazrul Anuar Bin Nayan Sekine and Takahashi Lab., Electronics and Information System Division Graduate School of Engineering Gifu University

2.

  • Introduction
  • Principle of Adiabatic
  • Two-Phase Clocked Adiabatic
  • Static CMOS Logic (2PASCL)
  • Application Circuits
  • LSI Implementation
  • Summary and Future Works

Slide 3. Slide

  • Introduction
  • Principle of Adiabatic
  • Two-Phase Clocked Adiabatic
  • Static CMOS Logic (2PASCL)
  • Application Circuits
  • LSI Implementation of 4x4-Bit Multiplier
  • Conclusion and Future Works

4. Designers dream 1. Portable increasebattery lifecontinuously2. High-end avoidcoolingpackages andreliabilityissue due to power SlideChapter 1 Introduction 5.

  • At circuit design level
    • Power down the functional blocks
    • Minimize sequential elements
    • Downsize all non-critical path circuits
    • Reduce loading on the clock
    • Parallelism
  • To solve dynamic power (drawback: static power)
    • Process shrink
    • Voltage scaling
    • Transistor sizing
  • To solve dynamic power (less static power)
    • Adiabatic (switching) circuits

SlideChapter 1 Introduction 6. SlideChapter 1 IntroductionTwo-phase Clocked Adiabatic Static CMOS Logic (2PASCL)Using adiabatic switchingReduce current flow 7. Slidecharismathics.com topnews.in Smart cards RFID nec.co.jp Sensors nextbigfuture.com Target: Low power, low frequency devices Chapter 1 Introduction 8. Static (leakage) ~10% Short circuit 10~20% Dynamic 70~80% (>0.18 m tech.) Abdollahi, A., Fallah, F., Pedram, M.: Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control. IEEE Transactions on VLSI Systems12 (2), 140154 (2004) SlideChapter 1 IntroductionAdiabatic switching --Technology to reduce dynamic power 9. CMOS and its equivalent circuit V ddand V ssof CMOS V dd V ss SlideChapter 2 Principle of Adiabatic e n (t) 10. SlideChapter 2 Principle of Adiabatic MOS R N MOS R 1 Pull-upnetwork Pull-upnetwork Pull-down network Pull-downnetwork 0.18process 1.2process Pull-up network 10 kOhm 3.8 kOhm Pull-down network 4 kOhm 2.2 kOhm 11. Charge transfer without generating heat. V and V -of adiabatic circuit. V SlideChapter 2 Principle of Adiabatic V w r : Energy dissipated at R 12. Adiabatic charging/dischargingreducethe amount ofcurrent flowin the circuit Theenergy recoveryphenomenon is demonstrated in w pramped voltage supply SlideChapter 2 Principle of Adiabatic w p : Supplied energy at P w C : Energy accumulated at C Pull up Pull down Pull up Pull down 13.

  • slow downenergy transfer.( )
  • Reduce thecurrent flowthrough transistor
  • recoveringenergy from logic (charge recycling)

SlideChapter 2 Principle of Adiabatic

  • ClockedACpower supply (height V dd )
  • GNDof CMOS connected toAC power
  • Diode s used mainly forrecycling charges

Technique

  • Voltagebetween current carrying electrodes ->zerowhen transistorswitch on .
  • Conductorcoupling between load capacitor and driver mustexis t at any time. charges

Requirement Condition 14.

  • During adiabatic switching, all the nodes are charged or discharged atconstantcurrent.
  • If the time for the driving voltage to change from 0 V toVdd ,is long, power dissipation is nearlyzero .

SlideChapter 2 Principle of Adiabatic 15. 2n2p-2n Method used tocreate three states;(released, zero, unity) 1n1p The approach 1n1p 2n2n2p ECRL ADL ADCL 2PADCL HCnMOS 2n-2n2D SlideChapter 2 Principle of Adiabatic (2PASCL) Adiabatic logic dynamic static DifferentialOperation Quasi Asymptotically Split-levelpulse driving 16. SlideChapter 2 Principle of Adiabatic Adiabatic inverters which are easily derived from CMOS T: period of primary signal N: no. of power supply V P& I P : voltage & current supply 17. Slide

  • Introduction
  • Principle of Adiabatic
  • Two-Phase Clocked Adiabatic
  • Static CMOS Logic (2PASCL)
  • Application Circuits
  • LSI Implementation of 4x4-Bit Multiplier
  • Conclusion and Future Works

18.

  • Inverter circuit and the waveforms, simulation using0.18 mCMOS process

Nazrul Anuar , Y. Takahashi, T. Sekine, Two phase clocked adiabatic static CMOS logic and its logic family,J. Semiconductor Technology and Science , vol. 10, no. 1, pp. 110, Mar. 2010. E i : Energy injected to the circuit E r : Energy received (recovery) 0.6 / 0.18 0.6 / 0.18 0.6 / 0.18 40 / 40 Split level sinusoidal to reduce thevoltage potentialof logic while maintaining theVp-pSlideChapter 3 2PASCL Diodes eliminated at the charging path to increase the amplitude and reduce dissipated energy 19.

  • 1.EvaluationMode
  • V YLOW- M2 ONC Lis charges; output HIGH ().
  • V YHIGH M1 ONdischarging via M1 & M4;
      • output LOW ().
  • 2.HoldMode
    • V YLOW- M2 ONno transition occurs; Y, as previous state.

V X V Y V V SlideChapter 3 2PASCL Evaluation and Hold Mode 20. Slide

  • n: number of power supply,
  • : constant shape factor
  • ( for sine-shaped current),
  • T i: period for one cycle.

C L =0.01 pF,V tp =0.58 V,V tn =0.24 V,Vp p = 0.9 V Power dissipation without shape factor (theory) Energy dissipation for triangle Chapter 3 2PASCL 21. SlideChapter 3 2PASCL 22. SlideChapter 3 2PASCL 23. SlideNORNAND XORNOT Chapter 3 2PASCL 24. SlideChapter 3 2PASCL 1 stdesign 2 nddesign 3 rddesign 4 thdesign 25. Chapter 3 2PASCL Slide4 thdesign 26. SlideChapter 3 2PASCL 27. Slide

  • Introduction
  • Principle of Adiabatic
  • Two-Phase Clocked Adiabatic
  • Static CMOS Logic (2PASCL)
  • Application Circuits
  • LSI Implementation of 4x4-Bit Multiplier
  • Conclusion and Future Works

28.

  • Objectives To evaluate the functionality of4-bit 2PASCL Ripple Carry Adder , and4x4-bit 2PASCL Multiplierwhich has long propagation path. To evaluate their energy dissipationcompared to CMOS.

SlideChapter 4 Application Circuits 29. Full Adder Spice diagram of4-bit 2PASCL RCA Slide4-bit Ripple Carry Adder (RCA) Chapter 4 Application Circuits Spice diagram 30. Average of 35% power dissipation reduction in 2PASCL-RCA compared to CMOS-RCA SlideChapter 4 Application Circuits Input, Power clocks and Output signal 2PASCL-RCA. 31. Chapter 4 Application Circuits Block diagram. Consists of 16 ANDs, 4 HAs, 8 FAs, and 8 DFFs. Slide 32. Chapter 4 Application Circuits Simulation results using 1.2um CMOS technology Slide1 1 1 1 0 0 0 0 1 1 1 1 (1111) 2X (1111) 2 = (11100001) 2 33. Comparison with CMOS using 1.2 m technology with W/L : 5.0/1.2 m Simulation at 1 to 12 MHz, 2PASCL Multiplier dissipates55%lower power compared to CMOS. SlideChapter 4 Application Circuits 34. Slide

  • Introduction
  • Principle of Adiabatic
  • Two-Phase Clocked Adiabatic
  • Static CMOS Logic (2PASCL)
  • Application Circuits
  • LSI Implementation of 4x4-Bit Multiplier
  • Conclusion and Future Works

35. NOR NOT NAND XOR D-Flip flop 1-bit Half Adder 1-bit Full Adder SlideChapter 5LSI Implementation 36. SlideChapter 5LSI Implementation 37. SlideChapter 5LSI Implementation

  • ON Semiconductor
  • 80 I/O
  • 2.3x2.3 cm Quad Flat Package (QFP).

38. Tech. 1.2 mCMOS 2-metal, 2-poly Power Voltage: 5.0 V Core Size : 1354 (W) 997 (H) m2 No. of transistors : 992 Dynamic Operating : Frequency 50 kHz 5 MHz Dynamic Power Dissipation: 5.8 mW @ 5 MHz mulitiplier 4-inverter chain SlideChapter 5LSI Implementation 39. SlideChapter 5LSI Implementation 40. Measurement equipment to examine the functionality of 4x4-bit array 2PASCL Multiplier SlideChapter 5LSI Implementation 41. Measurement result to examine the functionality of 4x4-bit array 2PASCL Multiplier @ 1 MHz SlideChapter 5LSI Implementation (a) Output signals without D-Flipflop (b) Output signalswith D-Flip flop 1 1 1 1 0 0 0 0 1 (1111) 2X (1111) 2 = (11100001) 2 42. SlideChapter 5LSI Implementation 43. Slide

  • Introduction
  • Principle of Adiabatic
  • Two-Phase Clocked Adiabatic
  • Static CMOS Logic (2PASCL)
  • Application Circuits
  • LSI Implementation of 4x4-Bit Multiplier
  • Summary and Future Works

44.

  • From simulation results, 4-bit 2PASCL ripple carry adder (RCA) and4x4-bit 2PASCL multiplier dissipates 35% and 77% lower power than CMOS respectively.
  • As for the measurement results, compared to the 2PADCL multiplier