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TRƯỜNG ĐẠI HỌC BÁCH KHOA ĐÀ NẴNG
KHOA ĐIỆN TỬ – VIỄN THÔNG
BÁO CÁO THÍ NGHIỆM
KỸ THUẬT SIÊU CAO TẦN
LAB 3: Transients on Transmission Lines
Student : Nguyễn Thị Bảo Trâm
Group : 09A
Class : 06DT1
Đà Nẵng – 2010
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 2
1. Introduction:
We have thus far focused on techniques for understanding transmission lines under sinusoidal
excitation. Powerful analytic insight is available here, permitting straightforward design of
interesting circuits.
In contrast, the analysis of transients is generally more difficult and less amenable to simple
closed-form analysis, especially when loads are reactive. This laboratory will explore the propagation
of transients on transmission lines with the aid of numerical experiments in SPICE.
2. Purely Resistive Termination:
First, let's use SPICE to investigate the propagation of pulses on a transmission line terminated
by purely resistive loads.
2.1 A step function, matched load
First, create a 50 transmission line with total length (time delay) of 25 ns, and excite it with a
Thevenin source 10u(t), with a source resistance Rg = 50 . With the load resistance RL = 50 ,
run the simulation.
To create the voltage source, use the VPWL source. Using VPWL allows various times and the
voltages at those times to be specified using the T1, T2, T3, ... and V1, V2, V3, ... parameters. The
voltage source will be piece-wise linear, connecting each specified point. Using VPULSE allows
specification of the initial voltage, V1, the voltage of the pulse, V2, the delay time, TD, the rise time,
TR, the fall time, TF, the pulse width, PW, and the period, PER.
The VPWL source is piece-wise linear and allows the user to specify voltages at specific times
using T1, T2, T3… and the corresponding V1, V2, V3 parameters. Please note that the source will
connect each specified point in the most direct way. Additionally, two voltages cannot be specified
for the same time, so that instantaneous changes must be approximated.
For Example: to specify a VPWL source that produces a 10V square pulse starting at t=0 and
lasting for 10 ns, would have the following specified parameters: T1=0, V1=0, T2=0.001n, V2=10,
T3=10n, V3=10, T4=10.001n, V4=0. (Making V3=0 would form a sawtooth wave because of the
reasons stated above.)
T1
TD = 25nsZ0 = 50
Vg
0
0
0
Vload
0
VsourceRg
50
RL
50
Vg
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 3
Using VPULSE allows specification of an initial voltage, V1, the voltage of the pulse, V2, the delay
time, TD, the rise time, TR, the fall time, TF, the pulse width, PW, and the period, PER. Single
pulses can be formed with this source. More complex signals can be formed by combining multiple
sources.
Problem 1 Plot the voltage at the source and load ends of the transmission line for t = 0…50 ns.
Using your understanding of “bounce diagrams”, explain whether this plot makes sense and shows
what you would expect to see in the “exact” answer. Do the two agree? If not, why not? A full
credit answer will describe the bounce diagram until a reasonable (whatever you consider
reasonable) number of bounces, which can explain what exactly is happening in this situation.
Please do the same in any other bounce diagram questions that may follow.
Answer:
- The voltage at the source and load ends of the transmission line for t = 0…50 ns
The reflection coefficient at the source is:
Γ𝑔 =𝑅𝑔 − 𝑍0
𝑅𝑔 + 𝑍0=
50 − 50
50 + 50= 0
The reflection coefficient at the load is:
Γ𝐿 =𝑅𝐿 − 𝑍0
𝑅𝐿 + 𝑍0=
50 − 50
50 + 50= 0
⇒ There is no reflection wave of voltage at the source and the load.
𝑉𝐿 =𝑉𝑔𝑍𝐿
𝑅𝑔 + 𝑍𝐿=
10 .50
50 + 50= 5(𝑉)
Time
0s 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40ns 45ns 50ns
V(VG) V(VSOURCE) V(VLOAD)
0V
5V
10V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 4
VL = 5 (V) after 25ns (time delay of the transmission line.) ⇒ The theory and the plot are the same.
2.2 A step function, mismatched load
Now, change the load impedance in the previous case to 20 .
Problem 2 Plot the voltage at the source and load ends of the transmission line for t = 0…100
ns. Using your understanding of “bounce diagrams”, compare this with what you would expect to
see in the “exact” answer. Do the two agree? If not, why not? How long does it take the answer to
settle to the final answer?
Answer:
- The voltage at the source and load ends of the transmission line for t = 0…100 ns
The reflection coefficient at the source is:
Γ𝑔 =𝑅𝑔 − 𝑍0
𝑅𝑔 + 𝑍0=
50 − 50
50 − 50= 0
Rg
50
RL
20
0
Vg
Vg
0
Vload
0
T1
TD = 25nsZ0 = 50
Vsource
0
Time
0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns
V(VG) V(VSOURCE) V(VLOAD)
0V
5V
10V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 5
The reflection coefficient at the load is:
7
3
5020
5020
0
0
ZR
ZR
L
LL
)(55050
50.10
0
0
1 VZR
ZVV
g
g
At t = T = 25ns, the wave reaches the load (receiving end) z = l, and because 07
3L , the
mismatch generates a reflected wave with the amplitude:
7
15. 11 VV L (V)
So the voltage on line (in this case, the load voltage) is the sum of two waves:
)(86.27
20
7
15511 VVVVL
At t = 2T = 50ns, the wave reaches the sending end z = 0, and because 0g , there is no
reflection wave in form of a wave with voltage amplitude V2+ = 0. Thus, the voltage on line (in this
case, the source voltage) is:
)(86.27
20
7
15511 VVVVS
At t = 3T = 75ns, the wave reaches the load (receiving end) z = l, and because 07
3L , the
mismatch generates a reflected wave with the amplitude: 0. 22 VV L (V)
VL = 2.86 (V) Similarly, we also have: VS = 2.86 (V)
Thus, after 50ns, the voltage at two ends of the transmission line have the same final answers.
t = 0
g
z = 0
t = 0
L
z = l
V1+
T
2T
L V1+
3T
L g V1+
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 6
2.3 A step function, mismatched load and source
Now, change the load impedance in the previous case to RL=20 , and change the source
impedance to Rg=200 .
Problem 3 Plot the voltage at the source and load ends of the transmission line for t = 0…300
ns. Using your understanding of “bounce diagrams”, compare this to the “exact” answer. Do the two
agree? If not, why not? How long does it take the answer to settle down to the final answer?
Answer:
- The voltage at the source and load ends of the transmission line for t = 0…300 ns
6.050200
50200
0
0
ZR
ZR
g
g
g
7
3
5020
5020
0
0
ZR
ZR
L
LL
Rg
200
RL
20
0
Vg
Vg
0
Vload
0
T1
TD = 25nsZ0 = 50
Vsource
0
Time
0s 50ns 100ns 150ns 200ns 250ns 300ns
V(VG) V(VSOURCE) V(VLOAD)
0V
4V
8V
12V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 7
)(250200
50.10
0
0
1 VZR
ZVV
g
g
At t = T = 25ns, the wave reaches the load (receiving end) z = l, and because 07
3L , the
mismatch generates a reflected wave with the amplitude:
86.07
62.)
7
3(. 11 VV L (V)
So the voltage on line (in this case, the load voltage) is the sum of two waves:
)(14.17
8
7
6211 VVVVL
At t = 2T = 50ns, the wave reaches the sending end z = 0, and because 6.0g , there is a
reflection wave in form of a wave with voltage amplitude V2+ =
1Vg . Thus, the voltage on line (in
this case, the source voltage) is:
)(63.0).1( 1211 VVVVVV gLLS
At t = 3T = 75ns, the wave reaches the load (receiving end) z = l, and because 07
3L , the
mismatch generates a reflected wave with the amplitude: 22 .VV L (V)
VL = 0.85 (V)
t = 0
g
z = 0
t = 0
L
z = l V1+
T
2T
L V1+
3T
4T
5T
gL V1+
gL 2
V1+
22
gL V1+
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 8
Calculate like the process above, we have the table:
Time V at sending end V at receiving end
t = 0ns VS = )(2
50200
50.10
0
0
1 VZR
ZVV
g
g
)(0 VVL
t = T =25ns VS = )(2
50200
50.10
0
0
1 VZR
ZVV
g
g
)(14.1
7
8
7
6211 VVVVL
t = 2T = 50ns
)(63.0).1( 1
211
VV
VVVV
gLL
S
)(14.17
8
7
6211 VVVVL
t = 3T=75ns
)(63.0).1( 1
211
VV
VVVV
gLL
S
)(85.0).1( 1
2 VVV gLgLLL
t = 4T=100ns )(98.0).1( 1
222 VVV gLgLgLLS
)(85.0).1( 1
2 VVV gLgLLL
t = 5T =125ns
)(98.0).
1(
1
22
2
VV
V
gL
gLgLLS
)(92.0).
1(
1
23
222
VV
V
gL
gLgLgLLL
T = 6T =150ns VS = 0.98 (V) VL = 0.924(V)
T = 7T =175ns VS = 0.89(V) VL = 0.924(V)
T = 8T =200ns VS = 0.89(V) VL = 0.909(V)
T = 9T =225ns VS = 0.913(V) VL = 0.909(V)
- Thus, the plot and the “exact” answer agree.
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 9
- The final voltage is: )(909.020200
20.10
0
VZR
ZVV
g
Lg
⇒ It takes 225ns to settle down to the final answer.
2.4 A short pulse
Now break the transmission line into two equal pieces, with total length 25 ns (you should now have
two different transmission lines, both with the same 50 characteristic impedance, but each with a
time delay of only 12.5 ns). This permits us to sample “inside” the transmission line. With the same
transmission line, and Rg=200 and RL=20 apply a pulse of duration 10 ns to the transmission
line, namely vg(t) = 10(u(t)- u(t-10ns)).
Problem 4 Plot the voltage at the source, middle, and load ends of the transmission lines for t =
0…100 ns. Sketch the bounce diagram; do you understand the voltage plots? How long before the
“ghost” pulse (the pulse you are seeing at the middle of the transmission line) arrives at the load
end? How large is the “ghost” pulse?
Answer:
- The voltage at the source, middle, and load ends of the transmission lines for t = 0…100ns
T1
Z0 = 50TD = 12.5ns RL
20
Vsource
000
Vg
0
Rg
200
00
VloadVmiddleVgT2
Z0 = 50TD = 12.5ns
Time
0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns
V(VSOURCE) V(VMIDDLE) V(VLOAD)
-2.0V
-1.0V
0V
1.0V
2.0V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 10
6.050200
50200
0
0
ZR
ZR
g
g
g
7
3
5020
5020
0
0
ZR
ZR
L
LL
)(250200
50.10
0
0
1 VZR
ZVV
g
g
- The bounce diagram:
- We have the table of values (by calculating):
Time V at sending end V middle V at receiving end
t = 0+ ns )(2
0
0
1 VZR
ZVVV
g
g
S
Vm = 0 (V) VL = 0 (V)
t = T/2
=12.5ns 0
50200
50.0
0
0
ZR
ZVV
g
g
S Vm = V1
+ (t = 0ns) =
2(V)
VL = 0 (V)
g
z = 0
t = 0
L
z = l V1+
T
2T
L V1+
3T
4T
5T
2lz
gL V1+
gL 2
V1+
22
gL V1+
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 11
t = T = 25ns VS = 0(V) Vm = VS (t = 12.5ns) =
0(V) )(14.1
7
8
7
62
11
V
VVVL
t = 3T/2 =
37.5ns
VS = 0(V)
)(86.07
6
11
V
VVV Lm
)(0 V
VVV mmL
(Vm at t = 2T)
t = 2T = 50ns
)(37.1
).( 1
21
V
V
VVV
gLL
S
)(0 VVV Lm VL = 0 (V)
t = 5T/2 =
62.5ns
)(050200
50.0
0
0
V
ZR
ZVV
g
g
S
)(51.026.07
3
12
V
VVV gLm
VL = 0 (V)
t = 3T=75ns VS = 0(V) Vm = VS (t = 12.5ns) =
0(V) )(29.0).( 1
2
22
VV
VVV
gLgL
L
t =
7T/2=82.5ns
VS = 0(V)
)(22.0
1
2
2
V
VVV gLm
VL = 0 (V)
t = 4T =100ns
)(35.0
).( 1
222
32
V
V
VVV
gLgL
S
)(0 VVV Lm VL = 0 (V)
It takes 12.5ns for the “ghost” pulse to get the load end. The ghost pulse has width of
12.5ns.
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 12
2.5 A longer pulse
In the previous problem, the pulse was brief (10 ns) compared to the length of the transmission line
(25 ns). Now investigate a more complicated system.
Problem 5 Using the same transmission line and source impedance, define a new source for
which vg = +10 V for t = 0 … 20 ns, and gv V for t = 20 … 40ns. Plot the voltage at the
source, center, and load end of the transmission line for t = 0…100 ns. Is the transition from “high”
to “low” perfectly clear at the load end?
Answer:
- The voltage at the source, center, and load end of the transmission line for t = 0…100ns
- From the graph, we can see that the transition from high to low is perfectly clear at the load
end.
2.6 An Impedance Bump
Transmission lines must be protected against damage, or their impedance properties could be
compromised. In this section we’ll “damage” the transmission line by putting a weak load in the
T1
Z0 = 50TD = 12.5ns RL
20
Vsource
000
Vg
0
Rg
200
00
VloadVmiddleVgT2
Z0 = 50TD = 12.5ns
Time
0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns
V(VSOURCE) V(VMIDDLE) V(VLOAD)
-4.0V
-2.0V
0V
2.0V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 13
middle. In particular, at the center of the transmission line, add a shunt resistance of 50 (a shunt
resistance connects the node at the middle to ground).
Problem 6 With the shunt resistance in place, repeat the previous problem. How did the
presence of the “bump” (break in the transition line) affect the voltage plots? Did any new “ghosts”
show up? Looking only at the source and end voltages, could you determine where the “bump” is?
Can you explain what you see in terms of a bounce diagram?
Answer:
- The presence of the impedance “bump” (break in the transition line) reduced the magnitude
of the middle voltage.
3. Reactive Termination
As mentioned in class, it is frequently the case that the loads at the end of a data bus are reactive
(and often capacitive).
3.1 A step into a capacitive load
Vg
T1
Z0 = 50TD = 12.5ns
VmiddleT2
Z0 = 50TD = 12.5ns
0 0
0
Rg
200
00 0
VloadVsource
0
Vg
Rshunt
50
RL
20
Time
0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns
V(VSOURCE) V(VMIDDLE) V(VLOAD)
-4.0V
-2.0V
0V
2.0V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 14
For this exercise, again form a circuit with a source vg(t) = 10u(t), a source impedance Rg=25 ,
and a transmission line with characteristic impedance 50 and length 25ns.
Problem 7 Terminate the transmission line with a 1nF capacitor. Plot the voltage at the source
and load ends of the transmission line for t = 0…400ns. If you see any “exponential” charging or
discharging, estimate the time constant, and solve for the R. You may use the following formulas.
Vinitial = 0V
VFinal = 12.133V
V(t) = 8.4292V
t = (75 – 25) = 50ns
CL
1n0
Vsource
0
Vg
Rg
25
0
0
VloadVgT1
TD = 25nsZ0 = 50
Time
0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns
V(VSOURCE) V(VLOAD)
0V
5V
10V
15V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 15
𝜏 =−𝑡
𝑙𝑛 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙
𝑉𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙
=−50. 10−9
𝑙𝑛 8.4292 − 12.133
0 − 12.133 = 4.214. 10−8
𝜏 = 𝑅𝐶 ⇒ 𝑅 =𝜏
𝐶=
4.214. 10−8
10−9= 42.14(Ω)
Problem 8 Repeat the previous problem, but with a load capacitance of 100pF.
Vinitial = 0V
VFinal = 13.33V
V(t) = 13.244V
t = (50 – 25) = 25ns
𝜏 =−𝑡
𝑙𝑛 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙
𝑉𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙
=−25. 10−9
𝑙𝑛 13.244 − 13.33
0 − 13.33 = 4.956. 10−9
𝜏 = 𝑅𝐶 ⇒ 𝑅 =𝜏
𝐶=
4.956. 10−9
100.10−12= 49.56(Ω)
Vload
CL
100pF0
0
Vg
Rg
25
0
0
VsourceVgT1
TD = 25nsZ0 = 50
Time
0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns
V(VSOURCE) V(VLOAD)
0V
5V
10V
15V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 16
Problem 9 Repeat the previous problem, but with a load capacitance of 10nF.
Vinitial = 0V
VFinal = 10V
V(t) = 8.056V
t = (400 – 25)= 375ns
𝜏 =−𝑡
𝑙𝑛 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙
𝑉𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙
=−375. 10−9
𝑙𝑛 8.056 − 10
0 − 10 = 2.29. 10−7
𝜏 = 𝑅𝐶 ⇒ 𝑅 =𝜏
𝐶=
2.29. 10−7
10.10−9= 22.9(Ω)
Problem 10 Repeat the previous problem, but with a load inductance of 2.5μH.
Vg
Vg
0
0
CL
10nF
T1
TD = 25nsZ0 = 50
0
0
Vsource VloadRg
25
Time
0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns
V(VSOURCE) V(VLOAD)
0V
5V
10V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 17
Vinitial = 13.202V
VFinal = 0V
V(t) = 4.8052V
t = (75 – 25) = 50ns
𝜏 =−𝑡
𝑙𝑛 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙
𝑉𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙
=−50. 10−9
𝑙𝑛 4.8052 − 013.202 − 0
= 4.947. 10−8
𝜏 =𝑅
𝐿 ⇒ 𝑅 =
𝐿
𝜏=
2.5. 10−6
4.947. 10−8= 50.53(Ω)
Problem 11 Repeat the previous problem, but with a load inductance of 0.25μH.
Vg
Vsource
0
L
2.5uH
1
20
VgT1
TD = 25nsZ0 = 50
0
0
VloadRg
25
Time
0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns
V(VSOURCE) V(VLOAD)
0V
5V
10V
15V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 18
Vinitial = 13.3V
VFinal = 0V
V(t) = 1.51V
t = (36 – 25)ns
𝜏 =−𝑡
𝑙𝑛 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙
𝑉𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙
=−11. 10−9
𝑙𝑛 1.51 − 013.3 − 0
= 5.056. 10−9
𝜏 =𝑅
𝐿 ⇒ 𝑅 =
𝐿
𝜏=
0.25. 10−6
5.056. 10−9= 49.44(Ω)
Problem 12 Repeat the previous problem, but with a load composed of a parallel combination of
RL=1000 , L = 1μH and C = 100pF.
L
0.25uH
1
2
Vsource
0
Vg
0
VloadRg
25
0
0
VgT1
TD = 25nsZ0 = 50
Time
0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns
V(VSOURCE) V(VLOAD)
-5V
0V
5V
10V
15V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 19
Problem 13 How important is the value of Rg in these exercises?
Answer:
- Rg is very important since it allows the system to reach steady state. The value of R
g helps us
to determine whether the circuit is matched or not at the input of transmission line.
4. Coupling
Many data buses are in parallel, in close proximity, such as the 32 bit and 64 bit buses found in
computers. These transmission lines will have “mutual impedance” which causes signals on one
transmission line to show up on another one.
In EE571 students analyze this coupling in great detail, but we can simulate a simplified model of a
two-wire data bus using SPICE1:
1 Note that your SPICE library contains a model for coupled lines; you could use this, but it does the modeling with an
explicit form of the Telegrapher’s Equation, and is painfully slow. I tried to use it, but realized that it would take about
one day to run every simulation!
Vg
Vsource
RL
1k
0
L
1uH
1
20
VgT1
TD = 25nsZ0 = 50
0
0
Vload
C
100pF
Rg
25
Time
0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns
V(VSOURCE) V(VLOAD)
-5V
0V
5V
10V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 20
Here T1 and T4 represent the “actual” transmission lines, while T2 and T3 represent the cross
coupling. The coupling is slightly faster (95 ns instead of 100 ns) and has a higher characteristic
impedance.
Connect a Thevenin signal pulse (10 V, 50 ) to A and 50 loads to B, C and D2.
2 To make this model even closer to the real thing, the signal injected into T2 should have opposite sign of that injected
into T1. However, this lab will not require this.
0
0
R3
50
0
A
R4
50
0
B
0
C
0
0
0
D
Vg
0
R2
50
0
T3
Z0 = 200TD = 95ns
T1
Z0 = 50TD = 100ns
0
T2TD = 95nsZ0 = 200
T4TD = 100ns
Z0 = 50
Vg
0
R1
50
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 21
4.1 A simple pulse
Inject a 10ns pulse with the Thevenin source at A. Use a rise and fall time of 1ns.
Problem 14 Simulate the problem for 250 ns, and plot the voltage at A, B, C, and D. Describe
what you observe. How big is the VC compared to VD when the pulse arrives?
Which arrives first?
Answer:
- Plot the voltage at A, B, C, and D
- VC is about 4 times compared to the magnitude of V
D when the pulse arrives.
- VD arrives first.
Problem 15 When does a signal arrive at B? If you change the values of the load resistances at C
and D, can you eliminate the reflection? If so what value should the load have?
Answer:
- A signal arrives at B at 195ns.
- We cannot eliminate the reflection by changing the values of the load resistances at C and
D. We just can reduce VC and VD to zero.
- The plot when the load resistances at C and D are 0.001Ω:
Time
0s 50ns 100ns 150ns 200ns 250ns
V(VG) V(A) V(B) V(C) V(D)
-5V
0V
5V
10V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 22
5. Impedance Matching
5.1. Pre-lab Assignment
5.1. A. Design a quarter-wave transformer to match a 150 Ω load to a source resistance of 75 Ω.
State the length of your transmission line(s) in terms of the wavelength.
Answer:
𝑍𝐿 = 150Ω
𝑍𝑖𝑛 = 75Ω
The input impedance is:
𝑍𝑖𝑛 = Z0
ZL + jZ0tgβl
Z0 + jZLtgβl
With 𝑙 =𝜆
4⇒ 𝛽𝑙 =
2𝜋
𝜆.𝜆
4=
𝜋
2
We can divide the numerator and the denominator by tgβl and take the limit as βl →π
2 to get:
𝑍𝑖𝑛 = 𝑍0
2
𝑍𝐿
The characteristic impedance of the matching section is:
⇒ 𝑍0 = 𝑍𝐿.𝑍𝑖𝑛 = 150.75 = 106.066(Ω)
Time
0s 50ns 100ns 150ns 200ns 250ns
V(VG) V(A) V(B) V(C) V(D)
-5V
0V
5V
10V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 23
5.1. B. Using the Smith Chart, if the characteristic impedance is given as 75 Ω, design a stub-
matching network to match a 150 Ω load to a 75 Ω source. Do this for both a shorted and an open
circuited stub. State the length of your transmission line(s) in terms of wavelength.
Answer:
𝑍0 = 75Ω
𝑍𝑖𝑛 = 75Ω
𝑍𝐿 = 150Ω
- The normalized load impedance is: 𝑧𝐿 =ZL
Z0=
150
75= 2Ω (point A on the Smith chart)
- Construct the appropriate SWR circle through point A. From the Smith chart, the normal load
admittance: yL = 0.5 (at point B l 0 )
- The SWR circle intersects the 1+jb circle at two points, denoted as y1 , y2. Thus the distance
d, from the load to the stub, is given by either of these two intersections. Reading the WTG
scale, we obtain:
d2 = (0.348– 0) = 0.348
At the two intersection points, the normalized admittances are:
y1 = 1 + j0.7
y2 = 1 – j0.7
- Thus, the first tuning solution requires a stub with a susceptance of – j0.7. The length of an
open-circuited stub that gives this susceptance can be found on Smith chart by starting at y
= 0 (the open circuit) and moving along the outer edge of the chart (g=0) toward the
generator to the – j0.7 point. The length is then:
lo1= 0.402
Similarly, the required open-circuited stub length for the second solution is:
lo2= 0.097
- The length of an shorted-circuited stub that gives this susceptance can be found on Smith
chart by starting at y = ∞ (the shorted circuit) and moving along the outer edge of the chart
(g=0) toward the generator to the – j0.7 point. The length is then:
ls1=(0.402 – 0.25) = 0.152
Similarly, the required shorted-circuited stub length for the second solution is:
ls2= (0.25 + 0.097) = 0.347
5.2. Lab Assignment
5.2.A. Find the actual length of the quarter-wave matching network you designed in part 5.1.A if up
= 2E+8 (m/s) and frequency = 1 GHz. Simulate the frequency response of the circuit by sweeping
the frequency from 1 MHz to 3 GHz using a 5Vpp sine wave source with a source resistance of 75 Ω.
Plot the input and load voltage over frequency. Plot the magnitude of the reflection coefficient of
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 24
the matching network and find the bandwidth where |Γ| is less than 0.2. What is the input
impedance of the matching network at 1 GHz?
Answer:
up = 2.108 m
s ; f = 1GHz
)(2.010
10.29
8
mf
u p
)(05.04
2.0
4ml
nsssm
m
u
lT
p
D 25.0)(10.5.2/10.2
05.0 10
8
- The input and load voltage over frequency:
Vload
RL
150
0
0
Vinput
Vs2.5Vac0Vdc
T1
TD = 0.25nsZ0 = 106.066
0
0
Rs
75
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 25
- The magnitude of the reflection coefficient of the matching network:
|Γ| is less than 0.2 from 608.1 MHz to 1.388 GHz and frequencies from 2.607 GHz to 3 GHz
- The input impedance of the matching network at 1 GHz is 75Ω.
Frequency
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
V(VINPUT) V(VLOAD)
1.2V
1.4V
1.6V
1.8V
Frequency
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
(V(VINPUT)/ I(Rs)-75)/(V(VINPUT)/I(Rs)+75)
0
100m
200m
300m
400m
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 26
5.2.B. Using the assumptions of section 5.2.A, simulate your pre-lab design in part 5.1.B and find
the Γ bandwidth (the portion of the signal less than 0.2) of the matching network as well as the
input impedance at 1 GHz. Include the same plots as in section 5.2.A.
Answer:
up = 2.108 m
s ; f = 1GHz
)(2.010
10.29
8
mf
u p
d1 =0.152𝜆 = 0.152×0.2 = 0.0304 (m) ⇒ nsssm
m
u
dT
p
D 152.0)(10.52.1/10.2
0304.0 10
8
1
lo1= 0.402𝜆 = 0.402×0.2 = 0.0804 (m) ⇒ nsssm
m
uT
p
D 402.0)(10.02.4/10.2
0804.0l 10
8
o1
ls1=0.152𝜆 = 0.152×0.2 = 0.0304 (m) ⇒ nsssm
m
uT
p
D 152.0)(10.52.1/10.2
0304.0l 10
8
s1
Open-circuited stub:
Frequency
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
V(VINPUT)/ I(Rs)
50
100
150
(1.0000G,75.000)
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 27
- The input and load voltage over frequency:
- The magnitude of the reflection coefficient of the matching network:
|Γ| is less than 0.2 from 924 MHz to 1.11 GHz.
0
R1
1000G
Vs2.5Vac0Vdc
Vload
T2
TD = 0.402nsZ0 = 75
T1
TD = 0.152nsZ0 = 75
VinputRs
75
RL
150
000
00
0
Frequency
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
V(VINPUT) V(VLOAD)
0V
0.5V
1.0V
1.5V
2.0V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 28
- The input impedance of the matching network at 1 GHz is 75.029Ω.
Shorted-circuited stub:
Frequency
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
(V(VINPUT)/I(Rs)-75)/(V(VINPUT)/I(Rs)+75)
0
0.5
1.0
Frequency
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
V(VINPUT)/ I(Rs)
0
50
100
150
(1.0000G,75.029)
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 29
- The input and load voltage over frequency:
- The magnitude of the reflection coefficient of the matching network:
0
Rs
75
Vinput
T2
TD = 0.152nsZ0 = 75
RL
150
Vload
Vs2.5Vac0Vdc
T1
TD = 0.152nsZ0 = 75
0
0 0
0 0
0
Frequency
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
V(VINPUT) V(VLOAD)
0V
0.5V
1.0V
1.5V
2.0V
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 30
|Γ| is less than 0.2 from 850 MHz to 1.21 GHz and from 2.07 GHz to 2.44 GHz
- The input impedance of the matching network at 1 GHz is 75.029Ω.
Problem 16 Compare the results for the matching networks that you designed in the lab (quarter
wave, open and short stub). Which one is a better choice. Why?
Answer:
- Compare the results for the matching networks that we designed in the lab (quarter wave,
open and short stub), the quarter wave is the best choice among of these. Because: it has
the largest Γ bandwidth (the portion of the signal less than 0.2) about 1.102GHz while the
open and short stub’s are quite less than 1.0GHz. Besides, it also has an input impedance of
exactly 75 ohms.
Frequency
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
(V(VINPUT)/I(Rs)-75)/(V(VINPUT)/I(Rs)+75)
0
0.5
1.0
Frequency
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
V(VINPUT)/ I(Rs)
0
50
100
(1.0000G,75.029)
Báo cáo TN SIÊU CAO TẦN Lab3
Nguyễn Thị Bảo Trâm – 06DT1 Page 31
Problem 17 For stub matching networks compare the performance of an open stub versus a
shorted stub.
Answer:
- For stub matching networks compare the performance of an open stub versus a shorted
stub: Γ bandwidth (the portion of the signal less than 0.2) about 0.186GHz and 0.73GHz
respectively. So the shorted stub circuit is the better one.
Problem 18 Suppose you had a lossless line terminated by a complex load, but wanted to carry
out the match using a quarter-wave transformer. How could you accomplish this?
Answer:
- Suppose we had a lossless line terminated by a complex load, but wanted to carry out the
match using a quarter-wave transformer. To accomplish this we could use a transmission
line with a complex characteristic impedance.