Upload
brianna-nichols
View
217
Download
0
Tags:
Embed Size (px)
Citation preview
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Interconnect Working GroupInterconnect Working Group
2001 Draft
18 July 2001
San Francisco
Christopher Case
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
JapanShinichi OgawaAkihiko Ohsaki
TaiwanCalvin HsuehShin-Puu Jeng
USRobert GeffkenChristopher Case
Europe
Hans Joachim-BarthJoachim Torres
Korea
Hyeon-Deok Lee
Hyun Chul Sohn
ITWG Regional Chairs
Participating at SEMI West 2001 workshop:
Robert Geffken, John Kelly, Jeff Wetzel, Bob Havemann, Harold Hosack, Mike Mills, Shinichi Domae, Christopher Case
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Agenda• Interconnect progression and scope• Difficult challenges• Technology requirements• Section updates:
– Conductors– Dielectrics– Planarization – Etch, Strip and Clean– Reliability– System and performance
• Last words
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Interconnect Progression• 1994 NTRS introduced the need for Cu and low k materials• 1997 NTRS describes adoption of these materials• 1999 ITRS highlighted
– Rapid changes in materials– Materials solutions alone cannot deliver performance -
end of traditional scaling in sight• 2001 Edition
– Materials, integration and interfaces dominate issues– Global wiring concerns require system and design
approaches
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
No Moore Scaling!Relative RC delay by process generation:
Intel process technologies (Bohr RC Model)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
00.10.20.30.40.5
Process Generation (half pitch)
Rel
ativ
e R
C D
elay
line length scales(lower levels)
line length constant(global levels)
Trend
ILD k = 2.7
Cu
Hypothetical materialsinsertions:
ILD k = 2.0
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Interconnect scope• Conductors and dielectrics
– local through global levels
• Associated planarization • Necessary etch, strip and clean• Embedded passives• Reliability and system and performance
issues• Ends at the top wiring bond pads• Predominantly “needs” based
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Wire
ViaGlobal (up to 5)
Intermediate (up to 4)
Local (2)
Passivation
Dielectric
Etch Stop Layer
Dielectric Capping Layer
Copper Conductor with Barrier/Nucleation Layer
Pre Metal DielectricTungsten Contact Plug
Typical chip cross-section illustratinghierarchical scaling methodology
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Difficult Challenges• Introduction of new
materials*• Integration of new
processes and structures*• Achieving necessary
reliability• Attaining dimensional control • Manufacturability and defect
management that meet overall cost/performance requirements
• Dimensional control and metrology
• Patterning, cleaning and filling high aspect ratios features
• Integration of new processes and structures
• Continued introductions of new materials and size effects
• Identify solutions which address global wiring scaling issues*
<65 nm>65 nm
* Top three grand challenges
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Introduction of new materials• Near term
• new barriers and nucleation layers– in situ formed dielectric and metal
• porous dielectrics • ALD potential solutions
– Combination of materials and technologies– Many new reliability challenges
• new materials and interfaces• electrical, thermal and mechanical exposure
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
• Long term– Continued introduction of materials
• barriers/nucleation layers for alternate conductors - optical, low temp, RF, air gap
• alternate conductors, cooled conductors
– More reliability challenges– Microstructural and atom scale effects
Materials Challenges
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Dimensional Control• 3DCD of features
– performance and reliability implications• Multiple levels
– reduced feature size, new materials and pattern dependent processes
– process interactions• CMP and deposition - dishing/erosion - thinning• Deposition and etch - to pattern multi-layer dielectrics
• Aspect ratios for etch and fill
– particularly DRAM contacts and dual damascene
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
• Combinations and interactions of new materials and technologies– interfaces, contamination, adhesion, diffusion, leakage
concerns, thermal budget, ESH, CoO
• Structural complexity– levels - interconnect, ground planes, decoupling caps
– passive elements
– mechanical integrity
– other SOC interconnect design needs (RF)
– cycle time
Process Integration
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Technology Requirement Issues
• Wiring levels including “optional levels”
• Reliability metrics
• Wiring/via pitches by level
• Planarization requirements
• Conductor resistivity
• Barrier thickness
• Dielectric metrics including effective
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
YEAR
TECHNOLOGY NODE
2001 2002 2003 2004 2005 2006 2007
DRAM ½ PITCH (nm) (SC. 2.0) 130 115 100 90 80 70 65
MPU/ASIC ½ PITCH (nm) (SC. 3.7) 150 130 107 90 80 70 65
MPU PRINTED GATE LENGTH (nm) (SC. 3.7) 90 75 65 53 45 40 35
MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) 65 53 45 37 32 28 25
Number of metal levels 8 8 8 9 10 10 10
Number of optional levels—ground planes/capacitors
2 2 4 4 4 4 4
Total interconnect length (m/cm2) –active wiring only, excluding globallevels (footnote for calculation)
4086 4843 5788 6879 9068 10022 11169
FITS/m length/cm2 X 10E-3excluding global levels (fittingfootnote)
1.22 1.03 0.86 0.73 0.55 0.50 0.45
MPU HP Near Term Years
Wiring length per cm2 excludes global levels
Constant reliability still requires improvement in defect density - based on 5 FITS and high performance MPU
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
YEAR
TECHNOLOGY NODE
2001 2002 2003 2004 2005 2006 2007
DRAM ½ PITCH (nm) (SC. 2.0) 130 115 100 90 80 70 65
MPU/ASIC ½ PITCH (nm) (SC. 3.7) 150 130 107 90 80 70 65
MPU PRINTED GATE LENGTH (nm) (SC. 3.7) 90 75 65 53 45 40 35
MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) 65 53 45 37 32 28 25
Local wiring pitch (nm) 350 295 245 210 185 170 150Local wiring A/R (for Cu) 1.6 1.6 1.6 1.7 1.7 1.7 1.7Intermediate wiring pitch (nm) 450 380 320 265 240 215 195Intermediate wiring dualdamascene A/R (Cu wire/via)
1.6/1.4 1.6/1.4 1.7/1.5 1.7/1.5 1.7/1.5 1.7/1.6 1.8/1.6
Minimum global wiring pitch(nm)
670 565 475 460 360 320 290
Global wiring dual damasceneA/R (Cu wire/via)
2.0/1.8 2.0/1.8 2.1/1.9 2.1/1.9 2.2/2.0 2.2/2.0 2.2/2.0
MPU HP Near Term Years
Significant reduction in wiring pitches to match roadmap acceleration
Relaxation of feature aspect ratios - due to benefit of Cu
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
YEAR
TECHNOLOGY NODE
2001 2002 2003 2004 2005 2006 2007
DRAM ½ PITCH (nm) (SC. 2.0) 130 115 100 90 80 70 65
MPU/ASIC ½ PITCH (nm) (SC. 3.7) 150 130 107 90 80 70 65
MPU PRINTED GATE LENGTH (nm) (SC. 3.7) 90 75 65 53 45 40 35
MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) 65 53 45 37 32 28 25
Cu thinning at minimum pitch due to erosion(nm), 10% X height, 50% areal density, 500m square array
28 24 20 18 16 14 13
Cu thinning at minimum intermediate pitchdue to erosion (nm), 10% X height, 50% arealdensity, 500 m square array
36 30 27 23 20 18 18
Cu thinning global wiring due to dishing anderosion (nm), 10% X height, 80% arealdensity, 15 micron wide wire
67 57 50 48 40 35 32
Cu thinning global wiring due to dishing (nm),100 micron wide feature
40 34 30 29 24 21 19
MPU HP Near Term Years
New combined dishing/erosion metric for global wires
Cu thinning due to dishing for isolated lines/pads
No significant dishing at local levels - thinning due to erosion over large areas (50% areal coverage)
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
YEAR
TECHNOLOGY NODE
2001 2002 2003 2004 2005 2006 2007
DRAM ½ PITCH (nm) (SC. 2.0) 130 115 100 90 80 70 65
MPU/ASIC ½ PITCH (nm) (SC. 3.7) 150 130 107 90 80 70 65
MPU PRINTED GATE LENGTH (nm) (SC. 3.7) 90 75 65 53 45 40 35
MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) 65 53 45 37 32 28 25
Conductor effective resistivity(-cm) Cu intermediate wiring*
2.2 2.2 2.2 2.2 2.2 2.2 2.2
Barrier/cladding thickness(for Cu intermediate wiring) (nm)
18 15 13 11 10 9 8
Interlevel metal insulator—effective dielectric constant ()
3.0-3.7 3.0–3.7 2.9–3.5 2.5–3.0 2.5–3.0 2.5–3.0 2.0–2.5
Interlevel metal insulator (minimumexpected)—bulk dielectric constant ()
2.7 2.7 2.7 2.2 2.2 2.2 1.7
MPU HP Near Term Years
Bulk and effective dielectric constants described
Cu at all nodes - conformal barriers
We will not answer the question - Will CVD or spin-on win?
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
YEAR
TECHNOLOGY NODE
2010 2013 2016
DRAM ½ PITCH (nm) (SC. 2.0) 45 32 22
MPU/ASIC ½ PITCH (nm) (SC. 3.7) 45 32 22
MPU PRINTED GATE LENGTH (nm) (SC. 3.7) 25 18 13
MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) 18 13 9.0
Number of metal levels 10 11 11Total interconnect length (m/cm2) – active wiring only,excluding global levels (footnote for calculation)
16063 22695 33508
Local wiring pitch (nm) 105 75 50Local A/R (for Cu) 1.8 1.9 2.0Intermediate wiring pitch (nm) 135 95 65Intermediate wiring dual damascene A/R (Cu wire/via) 1.8/1.6 1.9/1.7 2.0/1.8Minimum global wiring pitch (nm) 205 140 100Global wiring dual damascene A/R (Cu wire/via) 2.3/2.1 2.4/2.2 2.5/2.3Cu thinning global wiring due to dishing (nm),100 micron wide feature
14 10 8
Conductor effective resistivity(-cm) Cu intermediate wiring*
2.2 2.2 2.2
Barrier/cladding thickness(for Cu intermediate wiring) (nm)***
7 5 4
Interlevel metal insulator—effective dielectric constant () 2.0 1.9 1.7
Interlevel metal insulator (minimum expected)—bulk dielectric constant ()
1.6 1.6 1.5
MPU HP Long Term Years
Conductor effective resistivity (red) because of scattering effects -
research required
Zero thickness barrier desirable but not required
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Cu Resistivity vs. Linewidth Without Cu Barrier
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Line Width (um)
Res
isti
vity
(u
oh
m-c
m)
ITRS RequirementWITH Cu Barrier
Effect Of Line Width On Cu Resistivity
Courtesy of SEMATECH
Conductor resistivity increasesexpected to appear around 100 nm linewidth -will impact intermediate wiring first - ~ 2006
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
YEAR
TECHNOLOGY NODE
2001 2002 2003 2004 2005 2006 2007
DRAM ½ PITCH (nm) (SC. 2.0) 130 115 100 90 80 70 65
MPU/ASIC ½ PITCH (nm) (SC. 3.7) 150 130 107 90 80 70 65
MPU PRINTED GATE LENGTH (nm) (SC. 3.7) 90 75 65 53 45 40 35
MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) 65 53 45 37 32 28 25
Number of metal levels 3 3-4 4 4 4 4 4
Contact A/R—stacked capacitor 11.4 11.9 12.4 13.0 13.6 14.3 15.2
Local wiring pitch (nm) noncontacted 260 230 200 180 160 150 130
Specific contact resistance (-cm2) 1.5E-7 1.3E-7 1.0E-7 8.0E-8 7.0E-8 6.0E-8 5.0E-8
Specific via resistance (-cm2) 2E-9 1.4E-9 1.0E-9 9.0E-10 7.0E-10 6.0E-10 5.0E-10
Conductor effective resistivity (-cm)* 3.3 3.3 3.3 2.2 2.2 2.2 2.2
Interlevel metal insulator—effective dielectric constant ()
4.1 3.0–4.1 3.0–4.1 3.0–4.1 2.5–3.0 2.5–3.0 2.5–3.0
DRAM Near Term Years
Contact A/R rises to ~23 in 2016 - a red challenge - associated with 44 nm non-contacted local wiring pitch
Low k introduction is expected to precede Cu by two years
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Barriers/Nucleation Solutions• Barrier engineering
– for porous low k– Cu resistivity control
– atomic layer deposition - ALD
• Next generation ECD– Seed repair– Direct ECD on barriers– electrolyte management– possible electroless applications
• New cleans
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Conductor Potential SolutionsChallenges and changes
Seamless fill W conductor
Low resistivity Cu process needed to address resistivity increases - address the interface issues
CEP combined withCu ECD
Conductors, etch, dielectrics and planarization should address novel/potential cleans
First Year of IC Production 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
Local WiringSeamless Fill W conductor
High A/R CVD W contact fill for DRAM
Other high A/R contact fill for DRAM
Enhanced PVD/CVD Al fill
Intermediate WiringCu ECD CVD Cu
Low resistivity Cu process*
Global WiringCooled conductorsSuperconductorsRFOptical
PassivesElectrode materials for metal-insulator-metal capacitors
Magnetic materials for inductors
Narrow Options
Narrow Options
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
First Year of IC Production2001 2002 2003 2004 2005 2006 2007 2008 2010 2013 2016 2015
IMD k-effective (dielectric + etch stops)
2.9 Kef f2.5 Keff2.2 Kef f
2.0 Kef f
1.8 Kef f
Challenges
Development and integration of ultra low k materials with acceptable mechanical/thermal properties
High k and ferroelectric materials development
Fabricating low-temp low-loss SiO2 optical interconnect to address global wiring issues
Dielectric Potential Solutions
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Etch, Strip and Clean Potential Solutions• Many new low and high k materials - may require
new chemistries - supercritical CO2/solvents, ozone gas/liquid approaches
• Strip/clean compatibility with these new materials
• Dimensional control with small features and high A/R
• Selectivity to etch stops and hard masks
• Low damage
• MRAM, FeRAM applications
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Planarization Solutions
• CEP - chemically enhanced planarization and spin etch approaches
• Porous low k will require either alternative planarization or stopping layer/structural enhancements to be compatible with existing planarization techniques
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
• Material innovation combined with traditional scaling will no longer satisfy performance requirements– Design, packaging and interconnect
innovation needed– Alternate conductors
• optical, RF, low temperature
– Novel active devices (3D or multi-level) in the interconnect
Solutions beyond Cu and low
Work in Progress --- Not for Publication18 July 2001 Work In Progress – Not for Publication
Last words• Continued rapid changes in materials
• Must manage 3DCD
• System level solutions must be accelerated to address the global wiring grand challenge – Cu resistivity increase impact appears ~2006– materials solutions alone cannot deliver
performance - end of traditional scaling – integrated approach with design and packaging