MODULE 4

Sequential circuits• Sequential circuits are constructed using combinational logic

and a number of memory elements with some or all of the memory outputs fed back into the combinational logic forming a feedback path or loop.

• Sequential circuit = Combinational logic + Memory Elements

Memory Element

Sequential Circuit Memory Elements: Latches, Flip-Flops

• Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops.

• Latches: – The output of a latch depends on its current inputs and on its previous inputs and its change of state can happen at any time when its inputs change.

• Flip-Flop: – The output of a flip-flop also depends on current and previous input but the change in output (change of state or state transition) occurs at specific times determined by a clock input.

• Latches:– S-R Latch– S-R Latch With Enable– D-Latch

• Flip-Flops: – Edge-Triggered D Flip-Flop – Master/Slave S-R Flip-Flop – Master/Slave J-K Flip-Flop – Edge-Triggered J-K Flip-Flop – T Flip-Flop With Enable

Latches v/s Registers

Positive Feedback: Bi-Stability• Static memories use positive feedback to create a bi-stable

circuit — a circuit having two stable states that represent 0 and 1.

• The basic idea is shown in Figure, which shows two inverters connected in cascade along with a voltage-transfer characteristic typical of such a circuit.

• Also plotted are the Voltage Transfer Characteristics of the first inverter, that is, Vo1 versus Vi1, and the second inverter (Vo2 versus Vo1).

• The latter plot is rotated to accentuate that Vi2 = Vo1• The resulting circuit has only three possible operation points

(A, B, and C), as demonstrated on the combined VTC

• Under the condition that the gain of the inverter in the transient region is larger than 1, only A and B are stable operation points, and C is a meta-stable operation point.

Bi-Stability and Meta-Stability

Summary

• A bistable circuit has two stable states. • In absence of any triggering, the circuit remains in a single

state (assuming that the power supply remains applied to the circuit), and hence remembers a value.

• A trigger pulse must be applied to change the state of the circuit.

• Another common name for a bistable circuit is flip-flop (an edge-triggered register is also referred to as a flip-flop).

CMOS two-inverter bistable element• At the unstable operating point

– All four the transistor are in saturation – Resulting in maximum loop gain for the circuit – Small voltage perturbation

• Output voltage diverse and eventually settle at VOH and VOL

SR Flip-Flops

• An S-R (set-reset) latch can be built using two NOR gates forming a feedback loop.

• The output of the S-R latch depends on current as well as previous inputs or state, and its state (value stored) can change as soon as its inputs change.

NOR-based SR latch

• Figure shows the circuit structure of the simple CMOS SR latch, which has two such triggering inputs, S (set) and R (reset).

• The SR latch is also called the SR flip-flop, since two stable states can be switched back and forth.

• The circuit consists of two CMOS NOR2 gates. • The SR latch circuit has two complementary outputs, Q and Q . • By definition,

– The latch is said to be in its set state when Q is logic “1” and Q’ is logic “0” (Inputs S=1 and R=0).

– The latch is in its reset state when Q is logic “0” and Q’ is logic “1” (Inputs S=0 and R=1).

– When both inputs S and R are set to logic “0”, the SR latch will operate exactly like the simple cross-coupled bistable circuit and will hold either one of its two stable operating points (states) as determined by the previous inputs.

NAND-based SR latch

D Latch• When CLK = 1, latch is transparent – D flows through to Q like a buffer

• When CLK = 0, the latch is opaque – Q holds its old value independent of D

• a.k.a. transparent latch or level-sensitive latch

D Latch Design

D Latch Operation

D Flip-flop

D Flip-flop Design

D Flip-flop Operation

Race Condition

Non-overlapping Clocks

Typical BiCMOS Technology

1. Buried n+ layer drain2. Buried p+ layer3. Collector tub4. Active area5. Collector sinker6. n-well7. p-well8. Emitter window9. Base oxide/implant10. Emitter implant11. Poly 112. NMOS lightly doped drain

13. PMOS lightly doped14. n+ source/drain15. p+ source/drain16. Silicide protection17. Contacts18. Metal 119. Via 120. Metal 221. Via 222. Metal 323. Nitride passivation

The following steps describes BiCMOS process.

Notation:

• BSPG = Boron and Phosphorus doped Silicate Glass (oxide)

• Kooi Nitride = A thin layer of silicon nitride on the silicon surface as a result of the reaction of silicon with the HN3 generated, during the field oxidation.

• TEOS = Tetro-Ethyl-Ortho-Silicate. A chemical compound used to deposit conformal oxide films.

BiCMOS Process steps for the cross section

BiCMOS Inverter

BiCMOS Inverter

Inverter – Faster Circuit

BiCMOS NAND Gate

BiCMOS NOR Gate