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AT91 ARM Thumb Microcontrollers
Application Note
6320B–ATARM–05-Nov-07
Using the ECC Controller on AT91SAM9260/9263 and AT91SAM7SE Microcontrollers
1. Scope The purpose of this document is to explain how to use the Error Corrected Code(ECC) Controller embedded in the AT91SAM9260/9263 and AT91SAM7SE family ofARM® Thumb®-based microcontrollers. The ECC controller performs 2-bit data erroridentification and single-bit correction to maintain integrity of data stored in NANDFlash and SmartMedia® devices.
2. NAND Flash Device Overview
2.1 Internal Array ArchitectureThe NAND Flash array is organized in a series of blocks which are divided in severalpages. Data is stored either in byte (8 bits) or half-word (16 bits) format depending onthe device type. Each page consists of a main area for storing data and a spare area(physically similar) typically used for data error identification and correction, wear lev-elling, etc...
One particularity of NAND Flash devices is that they may contain a percentage ofinvalid blocks in the memory array. Before delivering the chip, these blocks are identi-fied and marked as “Invalid Blocks” in the first or second page of each block. Theexistence of bad blocks does not affect the good ones because each block is indepen-dent and individually isolated from the bit lines by block select transistors.
Because NAND Flash devices have a finite lifetime (approximately 100 000write/erase cycles), additional invalid blocks may develop while being used. Storingdata requires bad-block management and data error identification and correction.Refer to Section 3. ”Invalid Block Management”.
2.2 Basic Operation PrincipleNAND Flash operations are fully controlled through a multiplexed I/O interface andadditional control signals. Commands, addresses and data are transferred throughthe external input/output bus (8-bit or 16-bit) to the dedicated internal registers. In 16-bit devices, commands, addresses and data use the lower 8 bits (7 - 0), the upper 8bits are only used during data-transfer cycles.
Read and program operations are performed on a per page basis whereas eraseoperations are performed on a block basis. To read or write from NAND Flash, a com-mand sequence is issued to select a block and a page. After this selection, the entirepage can be read or written.
The command sequence normally consists of a Command Latch Cycle, an AddressLatch Cycle and a Data Cycle — either read or write.
The waveforms shown in Figure 2-1 depict the successive accesses: Command Latch, AddressLatch and Data Output. Notice that no command can be sent to the NAND Flash during tR due toit’s busy-state period.
Figure 2-1. Page READ Operation
Please refer to the NAND Flash manufacturer’s datasheet for command sets and full operationdescription.
3. Invalid Block Management
3.1 Invalid Block DefinitionAs mentioned in Section 2.1 ”Internal Array Architecture”, NAND flash devices contain a certainpercentage of invalid blocks at the end of the production process. Invalid blocks are defined asblocks that contain one or more invalid bits.
3.2 Spare Area AssignmentThe invalid block status byte location and the ECC locations within the spare area depend on thedevice type (small/large-page devices and 8/16- bit devices).
The widely used spare area assignment defined by SAMSUNG is illustrated in Figure 3-1, Fig-ure 3-2, Figure 3-3 and Figure 3-4.
tR
tREA
tCEA
ALE
CLE
I/Ox Address (5 cycles)
Commandcycle 1
Commandcycle 2
Address cycles
00h 30h
WE
RE
CE
R/B
Don't Care
26320B–ATARM–05-Nov-07
Application Note
Application Note
Figure 3-1. Small Page 8-bit Device Organization
Figure 3-2. Small Page 16-bit Device Organization
Figure 3-3. Large Page 8-bit Device Organization
Figure 3-4. Large Page 16-bit Device Organization
Abbreviations as used in Figure 3-1 through Figure 3-4 above
LSN0 LSN1 LSN2 Reserved Reserved Reserved Reserved Reserved Reserved ReservedBI ECC0 ECC1 ECC2 S-ECC0 S-ECC1
Cell Array512 Bytes
SpareCell Array16 Bytes
1stB 2ndB 3rdB 4thB 5thB 6thB 7thB 8thB 9thB 10thB 11thB 12thB 13thB 14thB 15thB 16thB
LSN0 LSN1 LSN2 B1ECCa ECCb ECCc S-ECCa S-ECCb
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
Cell Array256 Half Words
SpareCell Array8 Half Words
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1stHalf Word 2ndHalf Word 3rdHalf Word 4thHalf Word 5thHalf Word 6thHalf Word 7thHalf Word 8thHalf Word
BI LSN1LSN0 LSN2Reserved ReservedReservedReserved Reserved Reserved ReservedECC0 ECC1 ECC2 S-ECC0 S-ECC1
Cell Array512 Bytes
Cell Array512 Bytes
Cell Array512 Bytes
Cell Array512 Bytes
Spare CellArea
16 Bytes
Spare CellArea
16 Bytes
Spare CellArea
16 Bytes
Spare CellArea
16 Bytes
1stB 2ndB 3rdB 4thB 5thB 6thB 7thB 8thB 9thB 10thB 11thB 12thB 13thB 14thB 15thB 16thB
BI BI LSN0 S-ECC0ReservedReserved ECC0 ECC1 ECC2
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
LSN1 LSN2 Reserved S-ECC1 Reserved Reserved Reserved
Cell Array256 Half Words
Cell Array256 Half Words
Cell Array256 Half Words
Cell Array256 Half Words
Spare CellArea
8 Half Words
Spare CellArea
8 Half Words
Spare CellArea
8 Half Words
Spare CellArea
8 Half Words
1stHalf Word 2ndHalf Word 3rdHalf Word 4thHalf Word 5thHalf Word 6thHalf Word 7thHalf Word 8thHalf Word
• BI Invalid block information
• ECC ECC code for Cell Array data
• S-ECC ECC code for LSN data
• HW Half Word
• LSN Logical sector number
36320B–ATARM–05-Nov-07
3.3 Invalid Block IdentificationBefore shipping, every NAND Flash device is tested with specific test patterns under differentvoltage and temperature conditions in order to identify memory locations containing errors.When errors are detected, the block to which the invalid memory location belongs is marked asan “Invalid Block”.
All device locations are erased (FFh for 8-bit devices, FFFFh for 16-bit devices) except locationswhere the invalid block information is written.
As illustrated above in Figure 3-1,Figure 3-2, Figure 3-3, and Figure 3-4, the bad block Informa-tion is located in the first byte (8-bit devices) or first half word (16-bit devices) in the spare areafor Large Page devices and in the sixth byte (8-bit devices) or sixth half word (16-bit devices) inthe spare area of Small Page devices.
Manufacturers make sure that every invalid block has non-FFh (8-bit devices) or non-FFFFh(16-bit devices) data in the bad block information location.
Since invalid block information (located in the spare area) written by the manufacturer is notwrite/erase protected, it can be lost and will be almost impossible to recover. In order to preventloosing this information, it is highly recommended to proceed to a block status mapping beforeany write or erase operation.
The flow chart below describes how this can be done by software.
Figure 3-5. Bad Block Identification Flow Chart
Important Note: Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Data = FFhor FFFFh ?
Last Block ?
End
UpdateInvalid Block(s) Table
Increment Block Address
No
No
Yes
Yes
Point to Bad Block Information location
Create Invalid Block(s) Table
46320B–ATARM–05-Nov-07
Application Note
Application Note
4. Error Detection and Correction NAND Flash/SmartMedia devices contain by default invalid blocks which have one or moreinvalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occurwhich can be detected/corrected by ECC code. To ensure data read/write integrity, system errorchecking and correction (ECC) algorithms should be implemented. The AT91SAM9260/9263and AT91SAM7SE microcontrollers provide ECC hardware support. The embedded ECC con-trol ler is capable of single-bit error correction and 2-bit error detection per page(528/1056/2112/4224). When NAND Flash/SmartMedia have more than 2 bits of errors, the datacannot be corrected.
4.1 ECC Calculation AlgorithmFor Single-bit Error Correction and Double bit Error Detection (SEC-DED) hsiao code is used.32-bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit words. Of the 32 ECC bits, 26 bits are for line parity and 6 bits are for column parity. They aregenerated according to the schemes shown in Figure 4-1 and Figure 4-2.
Figure 4-1. Parity Generation for 512/1024/2048/4096 8-bit Words1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P8
P8'
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P8
P8'
P16
P16'
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P8
P8'
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P8
P8'
P16
P16'
P32
P32
1st byte
P322nd byte
3rd byte
4 th byte
Page size th byte
(page size -1 )th byte
PX
PX'
Page size = 512 Px = 2048 Page size = 1024 Px = 4096Page size = 2048 Px = 8192Page size = 4096 Px = 16384
(page size -2 )th byte
(page size -3 )th byte
P1 P1' P1'P1 P1 P1' P1'P1
P2 P2' P2 P2'
P4 P4'
P1=bit7(+)bit5(+)bit3(+)bit1(+)P1 P2=bit7(+)bit6(+)bit3(+)bit2(+)P2 P4=bit7(+)bit6(+)bit5(+)bit4(+)P4P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1'P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2'P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'
56320B–ATARM–05-Nov-07
Figure 4-2. Parity Generation for 512/1024/2048/4096 16-bit Words
1st w
ord
2nd
wor
d
3rd
wor
d
4th
wor
d
(Pag
e si
ze -3
)th
wor
d
(Pag
e si
ze -2
)th
wor
d
(Pag
e si
ze -1
)th
wor
d
Page
siz
e th
wor
d
66320B–ATARM–05-Nov-07
Application Note
Application Note
4.2 ECC Controller Preliminary RequirementsIn order to calculate ECC properly during write/read and read processes, the following con-straints must be respected:
• at least 1 Hold time must be programmed in the RWHOLD field of the SMC_CSRx register (only AT91SAM7SE family is concerned)
• read/write sequence must start at a page boundary
• read/write accesses must be done through the whole main area since ECC is calculated on the main area data
• data accesses must be performed chronologically through the main area
• the appropriate page size must be programmed in the PAGESIZE field of the ECC_MR register
4.3 ECC Controller Functional Description
4.3.1 Page Write SequenceThe ECC controller is automatically reset as soon as the first write command (80h) is performedto the NAND Flash or the SmartMedia device.
The ECC calculation starts only once the required address cycles (the number of address cyclesdepends on the device type) is performed to NAND Flash or the SmartMedia device.
The ECC is refreshed at each write access of the page until the last byte or half word of the mainarea is written.
Once the whole main area has been written, the final ECC result is available in the ECC ParityRegister (ECC_PR) and ECC NParity Register (ECC_NPR) until a new start condition occurs. Itis up to the software application to write the Parity ECC and NParity ECC in the appropriate loca-tions of the device spare area.
Please note that apart from data accesses (ALE = CLE = 0), the ECC controller ignores anyother command which is performed to the NAND Flash or the SmartMedia device.
Figure 4-3 below illustrates a full page write sequence with ECC calculation.
Figure 4-3. ECC Calculation During Page Write Sequence without Random Write Spare Area
I/Ox Address
Write Command 1
Write Command 2
Address cycles
ECC ControllerReset
Main Area Write AccessesAccesses Allowing ECC calculation
Start of ECC Calculation
ECC Result Ready in and Locked
Accesses Ignored by the ECC Controllerfor ECC calculation
Spare Area ECC locations Write Accesses
80h 10h1st 2nd ... n th ECC ECC ECC ECC
Main Area Size
76320B–ATARM–05-Nov-07
Figure 4-4. ECC Calculation During Page Write Sequence with Random Write Spare Area
4.3.2 Page Read SequenceThe ECC controller is automatically reset as soon as the first read command (00h) is performedto the NAND Flash or the SmartMedia device.
The ECC calculation starts only once the required address cycles (the number of address cyclesdepends on the device type) and the second read command (30h) is performed to the NANDFlash or the SmartMedia device.
The ECC is refreshed at each read access of the page until the last byte or half word of the mainarea is read.
Once the whole main area has been read, the next four data read accesses must be performedto the spare area locations where ECC has been previously stored by the software application. Ifthis condition is not respected, the ECC controller will not be able to check data integrity.
Since Parity ECC and NParity has been previously stored in locations of the spare area whichare not contiguous to the main area, it is useful to perform a random read command sequencebefore performing the four ECC data accesses.
Please note that apart from data accesses (ALE = CLE = 0), the ECC controller ignores anyother command which is performed to the NAND Flash or the SmartMedia device.
The ECC controller performs error detection automatically by applying an XOR operationbetween the calculated ECC and the ECC stored in the spare area.
In order to determine if an error has been detected by the ECC controller, the software applica-tion must check the MULERR, ECCERR and RECERR fields in the ECC Status Register(ECC_SR).
4.3.2.1 No ErrorMULERR, ECCERR and RECERR fields in the ECC Status Register (ECC_SR) are all cleared.
XOR between the calculated ECC computation and the ECC code stored in the spare area isequal to 0.
4.3.2.2 Recoverable ErrorOnly the RECERR field in the ECC Status register (ECC_SR) is set. The corrupted word offsetin the read page is defined by the WORDADDR field in the ECC Parity Register (ECC_PR). Thecorrupted bit position in the concerned word is defined in the BITADDR field in the ECC ParityRegister (ECC_PR).
Write Command 2
Spare Area ECC locations Write Accesses
10hECC ECC ECC ECCI/Ox Address
Write Command 1
Address cycles
ECC ControllerReset
Main Area Write AccessesAccesses Allowing ECC calculation
Start of ECC Calculation
ECC Result Ready in and Locked
Accesses Ignored by the ECC Controllerfor ECC calculation
80h 1st 2nd ... n th
Main Area Size
Address
Random Write
Command
Column Addresscycles
85h
86320B–ATARM–05-Nov-07
Application Note
Application Note
4.3.2.3 ECC ErrorThe ECCERR field in the ECC Status Register (ECC_SR) is set. An error has been detected inthe ECC code stored in the Spare area of the device. The position of the corrupted bit can befound by applying an XOR operation between the ECC Parity and the ECC NParity codes previ-ously stored in the spare area of the device.
4.3.2.4 Non Recoverable ErrorThe MULERR field in the ECC Status Register (ECC_SR) is set. Several errors have beendetected in the data stored in the device. The block to which this page belongs should bedeclared as invalid.
Figure 4-5 below illustrates a full page read sequence with ECC error detection.
Figure 4-5. ECC Error Detection During Page Read Sequence with Random Read Spare Area
Figure 4-6. ECC Error Detection During Page Read Sequence without Random Read Spare Area
Main Area Size
I/Ox Address
ReadCommand 1
Read Command 2
Address Cycles
ECC ControllerReset
Data Accesses
Main Area Read AccessesAccesses allowing ECC calculation
Start of ECC Calculation
ECC Result Ready and Locked
Accesses ignored by the ECC Controllerfor ECC calculation
Spare Area ECC locations Read Accesses
00h 30h 1st 2nd ... n th Address
Random Read
Command 1
Random Read
Command 2
Column Address cycles
Accesses ignored by the ECC Controllerfor Error Detection
05h E0h ECC ECC ECC ECC
Start of ECC Error Detection
ECC Error Detection Completed
Main Area Size
I/Ox Address
ReadCommand 1
Read Command 2
Address Cycles
ECC ControllerReset
Data Accesses
Main Area Read AccessesAccesses allowing ECC calculation
Start of ECC Calculation
ECC Result Ready and Locked
Accesses ignored by the ECC Controllerfor ECC calculation
Spare Area ECC locations Read Accesses
00h 30h 1st 2nd ... n th ECC ECC ECC ECC
Start of ECC Error Detection
ECC Error Detection Completed
96320B–ATARM–05-Nov-07
5. High-Level File System Software CompatibilityHigh-level software drivers for managing file systems in NAND Flash devices are available fromdifferent sources. These drivers provide support for wear leveling, bad block management, ECCetc...
File Systems available on the market usually manage ECC as:
• 3 bytes ECC for 256 bytes of data per page
• 3 bytes ECC for 512 bytes of data per page
The AT91SAM ECC controller manages ECC as:
• 4 bytes ECC for 512/1024/2048/4096 bytes of data per page
Since the ECC offset in the spare area and the number of ECC per page is not yet normalized, itis highly recommended to manage ECC by software when using a high-level file system.
6. Software ExampleA software example managing Bad Block Information and ECC error detection for Large PageDevices can be downloaded from the Atmel web site via the following link:
http://atmel.com/dyn/resources/prod_documents/an-nand_flash_sam7se_software_example.zip
106320B–ATARM–05-Nov-07
Application Note
Application Note
7. Revision History
Doc. Rev CommentsChange Request Ref.
6320A First issue
6320BFigure 4-3 and Figure 4-4 updated,
Section 3.2 ”Spare Area Assignment”, updated sentence refering to figures.4440
116320B–ATARM–05-Nov-07
6320B–ATARM–05-Nov-07
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6320B–ATARM–05-Nov-07