USING SHARED MEMORIES WITH MPMC - Xilinx. Using... · Alejandro Cristo García: [email protected] USING SHARED MEMORIES WITH MPMC Create a minimum system with BSB. [X] Base

Alejandro Cristo García: [email protected]

USING SHARED MEMORIES WITH MPMC

Create a minimum system with BSB.

[X] Base System Builder wizard (recommended).OK

Browse...Choose a project folder.OK

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[X] I would like to create a new designNext

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Board Name: Virtex 5 ML507 Evaluation PlatfomNext

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Next

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Next

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DDR2_SDRAM: mpmcxps_bram_if_cntlr_1/Size: 64 KB[X] DIP_Switches_8BitRemove[X] Ethernet_MACRemove[X] IIC_EEPROMRemove[X] LEDs_8BitRemove[X] LEDs_PositionsRemove[X] PCIe_Bridge

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Remove[X] Push_Buttons_5BitRemove[X] RS232_Uart_2Remove[X] SysACE_CompactFlashRemoveNext

Next

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Next

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Finish

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OK

The minimum system should have been built.

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Configuring the memory interface (MPMC)

[DC] Bus Interfaces / DDR2_SDRAM / PPC440MC0

Port1: NPI[C] Memory Interface

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Manufacturer: MicronPart No.: MT4HTF3264H-667Memory Data Width: 32[C] Port Configuration

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[C] NPI WidthNPI Width: 32[C] Advanced[C] Misc

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[C] IDELAYCTRL Constraint Locations (Hyphen separated) (unactivate)[C] Number of IDELAYCTRL Elements (unactivate)OK

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Creating a custom IP to use the MPMC interface

Hardware / Create or Import Peripheral...

Next

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Next

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Next

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Name: memory_writer_readerNext

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Next

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[ ] Include data phase timerNext

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Next

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Number of software accessible registers: 5REG0: RST (Input)REG1: E (Input)REG2: W/R (0: Write, 1: Read) (Input)REG3: Address (Input)REG4: DataInput (Input)REG5: DataOutput (Output)REG6: Done (Output)Next

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Next

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Next

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[V] Generate ISE and XST project files to help you implement the peripheral using XST flow[V] Generate template driver files to help you implement software interfaceNext

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Finish

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The new IP should appear in IP Catalog / Project Local Pcores / User

Open the file: [Workfolder]/pcores/memory_writer_reader_v1_00_a/hdl/vhdl/memory_writer_reader.vhd

Add the following ports under the “-- USER ports added here” line:

XIL_NPI_Addr_Port1: out std_logic_vector(0 to 31);XIL_NPI_AddrReq_Port1: out std_logic;XIL_NPI_AddrAck_Port1: in std_logic;XIL_NPI_RNW_Port1: out std_logic;XIL_NPI_Size_Port1: out std_logic_vector(0 to 3);XIL_NPI_RdModWr_Port1: out std_logic;XIL_NPI_WrFIFO_Data_Port1: out std_logic_vector(0 to 31);XIL_NPI_WrFIFO_BE_Port1: out std_logic_vector(0 to 3);XIL_NPI_WrFIFO_Push_Port1: out std_logic;XIL_NPI_RdFIFO_Data_Port1: in std_logic_vector(0 to 31);XIL_NPI_RdFIFO_Pop_Port1: out std_logic;XIL_NPI_RdFIFO_RdWdAddr_Port1: in std_logic_vector(0 to 3);XIL_NPI_WrFIFO_Empty_Port1: in std_logic;XIL_NPI_WrFIFO_AlmostFull_Port1: in std_logic;XIL_NPI_WrFIFO_Flush_Port1: out std_logic;XIL_NPI_RdFIFO_Empty_Port1: in std_logic;XIL_NPI_RdFIFO_Flush_Port1: out std_logic;XIL_NPI_RdFIFO_Latency_Port1: in std_logic_vector(0 to 1);XIL_NPI_InitDone_Port1: in std_logic;

Add the following port maps under the “-- USER ports mapped here” line:

XIL_NPI_Addr_Port1 => XIL_NPI_Addr_Port1,

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XIL_NPI_AddrReq_Port1 => XIL_NPI_AddrReq_Port1,XIL_NPI_AddrAck_Port1 => XIL_NPI_AddrAck_Port1,XIL_NPI_RNW_Port1 => XIL_NPI_RNW_Port1,XIL_NPI_Size_Port1 => XIL_NPI_Size_Port1,XIL_NPI_RdModWr_Port1 => XIL_NPI_RdModWr_Port1,XIL_NPI_WrFIFO_Data_Port1 => XIL_NPI_WrFIFO_Data_Port1,XIL_NPI_WrFIFO_BE_Port1 => XIL_NPI_WrFIFO_BE_Port1,XIL_NPI_WrFIFO_Push_Port1 => XIL_NPI_WrFIFO_Push_Port1,XIL_NPI_RdFIFO_Data_Port1 => XIL_NPI_RdFIFO_Data_Port1,XIL_NPI_RdFIFO_Pop_Port1 => XIL_NPI_RdFIFO_Pop_Port1,XIL_NPI_RdFIFO_RdWdAddr_Port1 => XIL_NPI_RdFIFO_RdWdAddr_Port1,XIL_NPI_WrFIFO_Empty_Port1 => XIL_NPI_WrFIFO_Empty_Port1,XIL_NPI_WrFIFO_AlmostFull_Port1 => XIL_NPI_WrFIFO_AlmostFull_Port1,XIL_NPI_WrFIFO_Flush_Port1 => XIL_NPI_WrFIFO_Flush_Port1,XIL_NPI_RdFIFO_Empty_Port1 => XIL_NPI_RdFIFO_Empty_Port1,XIL_NPI_RdFIFO_Flush_Port1 => XIL_NPI_RdFIFO_Flush_Port1,XIL_NPI_RdFIFO_Latency_Port1 => XIL_NPI_RdFIFO_Latency_Port1,XIL_NPI_InitDone_Port1 => XIL_NPI_InitDone_Port1,

Save the file.

Open the file: [Workfolder]/pcores/memory_writer_reader_v1_00_a/hdl/vhdl/user_logic.vhd

Add the following ports under the “-- USER ports added here” line:

XIL_NPI_Addr_Port1: out std_logic_vector(0 to 31);XIL_NPI_AddrReq_Port1: out std_logic;XIL_NPI_AddrAck_Port1: in std_logic;XIL_NPI_RNW_Port1: out std_logic;XIL_NPI_Size_Port1: out std_logic_vector(0 to 3);XIL_NPI_RdModWr_Port1: out std_logic;XIL_NPI_WrFIFO_Data_Port1: out std_logic_vector(0 to 31);XIL_NPI_WrFIFO_BE_Port1: out std_logic_vector(0 to 3);XIL_NPI_WrFIFO_Push_Port1: out std_logic;XIL_NPI_RdFIFO_Data_Port1: in std_logic_vector(0 to 31);XIL_NPI_RdFIFO_Pop_Port1: out std_logic;XIL_NPI_RdFIFO_RdWdAddr_Port1: in std_logic_vector(0 to 3);XIL_NPI_WrFIFO_Empty_Port1: in std_logic;XIL_NPI_WrFIFO_AlmostFull_Port1: in std_logic;XIL_NPI_WrFIFO_Flush_Port1: out std_logic;XIL_NPI_RdFIFO_Empty_Port1: in std_logic;XIL_NPI_RdFIFO_Flush_Port1: out std_logic;XIL_NPI_RdFIFO_Latency_Port1: in std_logic_vector(0 to 1);XIL_NPI_InitDone_Port1: in std_logic;

Replace the following code:

SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); slv_reg3 <= (others => '0');

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slv_reg4 <= (others => '0'); slv_reg5 <= (others => '0'); slv_reg6 <= (others => '0'); else case slv_reg_write_sel is when "1000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0100000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0010000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0001000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0000100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0000010" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0000001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when others => null; end case; end if; end if;

end process SLAVE_REG_WRITE_PROC;

With this one (output registers must disappear):

SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin

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if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0');

slv_reg2 <= (others => '0');slv_reg3 <= (others => '0');slv_reg4 <= (others => '0');

else case slv_reg_write_sel is when "1000000" => slv_reg0 <= Bus2IP_Data(0 to C_SLV_DWIDTH-1);

when "0100000" => slv_reg1 <= Bus2IP_Data(0 to C_SLV_DWIDTH-1); when "0010000" => slv_reg2 <= Bus2IP_Data(0 to C_SLV_DWIDTH-1); when "0001000" => slv_reg3 <= Bus2IP_Data(0 to C_SLV_DWIDTH-1); when "0000100" => slv_reg4 <= Bus2IP_Data(0 to C_SLV_DWIDTH-1);

when others => null; end case; end if; end if;

end process SLAVE_REG_WRITE_PROC;

Add the following code under the “User signal declarations added here, as needed for user logic” line:

type state_type is (IDLE, WRITE1, WRITE2, READ1, READ2, READ3, READ4); signal s_Rst, s_E, S_WR, s_Done, s_Done2: std_logic;signal s_Address, s_DataInput, s_DataOutput: std_logic_vector(0 to 31);signal status_Port1: state_type;

Add the following code under the “end process SLAVE_REG_READ_PROC;” line. It is a process that allows to read and write in memory by using the MPMC interface, according to the diagram times provided by Xilinx:

read_write_memory1: process (Bus2IP_Clk) isbegin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' thenif s_Rst = '1' then

XIL_NPI_Addr_Port1 <= "00000000000000000000000000000000";XIL_NPI_AddrReq_Port1 <= '0';XIL_NPI_RNW_Port1 <= '0';XIL_NPI_Size_Port1 <= "0000";XIL_NPI_RdModWr_Port1 <= '0';XIL_NPI_WrFIFO_Push_Port1 <= '0';XIL_NPI_WrFIFO_Flush_Port1 <= '0';XIL_NPI_WrFIFO_Data_Port1 <= "00000000000000000000000000000000";XIL_NPI_WrFIFO_BE_Port1 <= "0000";s_DataOutput <= "00000000000000000000000000000000";s_Done <= '0';status_Port1 <= IDLE;

elsecase (status_Port1) is

when IDLE =>s_Done <= '0';if s_E = '1' then

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if s_WR = '0' thenXIL_NPI_Addr_Port1 <= s_Address;XIL_NPI_AddrReq_Port1 <= '1';XIL_NPI_RNW_Port1 <= '0';XIL_NPI_Size_Port1 <= "0000";XIL_NPI_RdModWr_Port1 <= '1';XIL_NPI_WrFIFO_Push_Port1 <= '0';XIL_NPI_WrFIFO_Flush_Port1 <= '0';XIL_NPI_WrFIFO_Data_Port1(0 to 7) <=

s_DataInput(24 to 31);XIL_NPI_WrFIFO_Data_Port1(8 to 15) <=



s_DataInput(0 to 7);XIL_NPI_WrFIFO_BE_Port1 <= "0000";status_Port1 <= WRITE1;

elseXIL_NPI_Addr_Port1 <= s_Address;XIL_NPI_AddrReq_Port1 <= '1';XIL_NPI_RNW_Port1 <= '1';XIL_NPI_Size_Port1 <= "0000";XIL_NPI_RdFIFO_Pop_Port1 <= '0';XIL_NPI_RdFIFO_Flush_Port1 <= '0';status_Port1 <= READ1;

end if;end if;

when WRITE1 =>if XIL_NPI_AddrAck_Port1 = '1' then

XIL_NPI_AddrReq_Port1 <= '0';XIL_NPI_RNW_Port1 <= '1';XIL_NPI_RdModWr_Port1 <= '0';XIL_NPI_WrFIFO_Push_Port1 <= '1';XIL_NPI_WrFIFO_BE_Port1 <= "1111";status_Port1 <= WRITE2;

end if;when WRITE2 =>

XIL_NPI_WrFIFO_Push_Port1 <= '0';s_Done <= '1';status_Port1 <= IDLE;

when READ1 =>if XIL_NPI_AddrAck_Port1 = '1' then

XIL_NPI_AddrReq_Port1 <= '0';XIL_NPI_RNW_Port1 <= '0';status_Port1 <= READ2;

end if;when READ2 =>

if XIL_NPI_RdFIFO_Empty_Port1 = '0' thenXIL_NPI_RdFIFO_Pop_Port1 <= '1';if XIL_NPI_RdFIFO_Latency_Port1 = "00" then

s_DataOutput(0 to 7) <= XIL_NPI_RdFIFO_Data_Port1(24 to 31);



s_DataOutput(24 to 31) <=

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XIL_NPI_RdFIFO_Data_Port1(0 to 7);end if;status_Port1 <= READ3;

end if;when READ3 =>

XIL_NPI_RdFIFO_Pop_Port1 <= '0';if XIL_NPI_RdFIFO_Latency_Port1 = "00" then

status_Port1 <= IDLE;s_Done <= '1';

else if XIL_NPI_RdFIFO_Latency_Port1 = "01" then





status_Port1 <= IDLE;s_Done <= '1';

elsestatus_Port1 <= READ4;

end if;end if;

when READ4 =>s_DataOutput(0 to 7) <= XIL_NPI_RdFIFO_Data_Port1(24 to

31);s_DataOutput(8 to 15) <= XIL_NPI_RdFIFO_Data_Port1(16 to



7);status_Port1 <= IDLE;s_Done <= '1';

end case;end if;

end if;end process read_write_memory1;

Add the following code under the “end process read_write memory;” line. They are a process and signal assignments to control the outputs after reading or writing a certain value:

done: process (Bus2IP_Clk) isbegin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' thenif s_E = '1' then

s_Done2 <= '0';end if;if s_Done = '1' then

s_Done2 <= '1';end if;

end if;end process done;

s_Rst <= slv_reg_write_sel(0) AND Bus2IP_Data(31);s_E <= slv_reg_write_sel(1) AND Bus2IP_Data(31);

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s_WR <= slv_reg2(31);s_Address <= slv_reg3;s_DataInput <= slv_reg4;slv_reg5 <= s_DataOutput;slv_reg6 <= "0000000000000000000000000000000"&s_Done2;

Save the file.

Hardware / Create or Import Peripheral...

Next

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[X] Import existing peripheralNext

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Next

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Name: memory_writer_readerNext

Yes

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Next

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[X] Use existing Peripheral Analysis Order file (*.pao)BrowseChoose the file 'memory_writer_reader_v1_00_a/data/memory_writer_reader_v2_1_0.pao'.Next

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BrowseChoose all *.vhd and *.vhdl files in the folder 'pcores/memory_writer_reader_v1_00_a/hdl/vhdl'.NextIf syntax errors appear, correct them in the corresponding VHDL file and try again by clicking 'Back' and 'Next' again.

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[V] PLBV46 Slave (SPLB)Next

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Next

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Parameter determine high address: C_HIGHADDRNext

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[ ] Select and configure interrupt(s)Next

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Next

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Next

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Finish

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Connecting the IP to the system

[RC] IP Catalog/Project Local Pcores/USER/memory_writer_reader View MPD

Add the following sentence in the '## Peripheral Options' section:

OPTION ARCH_SUPPORT_MAP = (OTHERS = DEVELOPMENT)

Add the following sentence in the '## Bus Interfaces' section:

BUS_INTERFACE BUS = XIL_NPI_Port1, BUS_TYPE = INITIATOR, BUS_STD = XIL_NPI

Replace the following sentences:

PORT XIL_NPI_Addr_Port1 = "", DIR = O, VEC = [0:31]PORT XIL_NPI_AddrReq_Port1 = "", DIR = OPORT XIL_NPI_AddrAck_Port1 = "", DIR = IPORT XIL_NPI_RNW_Port1 = "", DIR = OPORT XIL_NPI_Size_Port1 = "", DIR = O, VEC = [0:3]PORT XIL_NPI_RdModWr_Port1 = "", DIR = OPORT XIL_NPI_WrFIFO_Data_Port1 = "", DIR = O, VEC = [0:31]PORT XIL_NPI_WrFIFO_BE_Port1 = "", DIR = O, VEC = [0:3]PORT XIL_NPI_WrFIFO_Push_Port1 = "", DIR = O

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PORT XIL_NPI_RdFIFO_Data_Port1 = "", DIR = I, VEC = [0:31]PORT XIL_NPI_RdFIFO_Pop_Port1 = "", DIR = OPORT XIL_NPI_RdFIFO_RdWdAddr_Port1 = "", DIR = I, VEC = [0:3]PORT XIL_NPI_WrFIFO_Empty_Port1 = "", DIR = IPORT XIL_NPI_WrFIFO_AlmostFull_Port1 = "", DIR = IPORT XIL_NPI_WrFIFO_Flush_Port1 = "", DIR = OPORT XIL_NPI_RdFIFO_Empty_Port1 = "", DIR = IPORT XIL_NPI_RdFIFO_Flush_Port1 = "", DIR = OPORT XIL_NPI_RdFIFO_Latency_Port1 = "", DIR = I, VEC = [0:1]PORT XIL_NPI_InitDone_Port1 = "", DIR = I

With these ones:

PARAMETER C_PI_ADDR_WIDTH = 32, DT = INTEGERPARAMETER C_PI_DATA_WIDTH = 32, DT = INTEGERPARAMETER C_PI_BE_WIDTH = 4, DT = INTEGERPARAMETER C_PI_RDWDADDR_WIDTH = 4, DT = INTEGERPORT XIL_NPI_Addr_Port1 = "Addr", DIR = O, VEC = [(C_PI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = XIL_NPI_Port1PORT XIL_NPI_AddrReq_Port1 = "AddrReq", DIR = O, BUS = XIL_NPI_Port1PORT XIL_NPI_AddrAck_Port1 = "AddrAck", DIR = I, BUS = XIL_NPI_Port1PORT XIL_NPI_RNW_Port1 = "RNW", DIR = O, BUS = XIL_NPI_Port1PORT XIL_NPI_Size_Port1 = "Size", DIR = O, VEC = [3:0], BUS = XIL_NPI_Port1PORT XIL_NPI_WrFIFO_Data_Port1 = "WrFIFO_Data", DIR = O, VEC = [(C_PI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = XIL_NPI_Port1PORT XIL_NPI_WrFIFO_BE_Port1 = "WrFIFO_BE", DIR = O, VEC = [(C_PI_BE_WIDTH-1):0], ENDIAN = LITTLE, BUS = XIL_NPI_Port1PORT XIL_NPI_WrFIFO_Push_Port1 = "WrFIFO_Push", DIR = O, BUS = XIL_NPI_Port1PORT XIL_NPI_RdFIFO_Data_Port1 = "RdFIFO_Data", DIR = I, VEC = [(C_PI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = XIL_NPI_Port1PORT XIL_NPI_RdFIFO_Pop_Port1 = "RdFIFO_Pop", DIR = O, BUS = XIL_NPI_Port1PORT XIL_NPI_RdFIFO_RdWdAddr_Port1 = "RdFIFO_RdWdAddr", DIR = I, VEC = [(C_PI_RDWDADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = XIL_NPI_Port1PORT XIL_NPI_WrFIFO_Empty_Port1 = "WrFIFO_Empty", DIR = I, BUS = XIL_NPI_Port1PORT XIL_NPI_WrFIFO_AlmostFull_Port1 = "WrFIFO_AlmostFull", DIR = I, BUS = XIL_NPI_Port1PORT XIL_NPI_WrFIFO_Flush_Port1 = "WrFIFO_Flush", DIR = O, BUS = XIL_NPI_Port1PORT XIL_NPI_RdFIFO_Empty_Port1 = "RdFIFO_Empty", DIR = I, BUS = XIL_NPI_Port1PORT XIL_NPI_RdFIFO_Flush_Port1 = "RdFIFO_Flush", DIR = O, BUS = XIL_NPI_Port1PORT XIL_NPI_RdFIFO_Latency_Port1 = "RdFIFO_Latency", DIR = I, VEC = [1:0], BUS = XIL_NPI_Port1PORT XIL_NPI_RdModWr_Port1 = "RdModWr", DIR = O, BUS = XIL_NPI_Port1PORT XIL_NPI_InitDone_Port1 = "InitDone", DIR = I, BUS = XIL_NPI_Port1

Save and close the MPD file.

Project / Rescan User Repositories

[RC] IP Catalog / Project Local PCores / USER / memory_writer_reader Add IP

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OK

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The NPI connection should have appeared.

Bus Interfaces / DDR2_SDRAM / MPMC_PIM1: memory_writer_reader_0_XIL_NPI_Port1Bus Interfaces / memory_writer_reader_0 / SPLB / SPLB: plb_v46_0Ports

[V] Ports / By Connection / Defaults

All the ports PIM1_* in the 'DDR2_SDRAM' component should be connected to the 'memory_writer_reader_0' component.

Addresses

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Addresses / Unmapped Addresses / memory_writer_reader_0: 64KGenerate Addresses

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----------------------------------------------------------------------------------------------------------

Compiling the hardware system

[DC] Project / Project Files / UCF File: data/system.ucf

Insert '#' before the following lines to comment them:

Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<32> LOC=V29 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<33> LOC=Y27 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<34> LOC=Y26 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<35> LOC=W24 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<36> LOC=V28 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<37> LOC=W25 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<38> LOC=W26 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<39> LOC=V24 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<40> LOC=R24 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<41> LOC=P25 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<42> LOC=N24 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<43> LOC=P26 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<44> LOC=T24 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<45> LOC=N25 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<46> LOC=P27 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<47> LOC=N28 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<48> LOC=M28 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<49> LOC=L28 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<50> LOC=F25 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<51> LOC=H25 | IOSTANDARD = SSTL18_II;

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Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<52> LOC=K27 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<53> LOC=K28 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<54> LOC=H24 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<55> LOC=G26 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<56> LOC=G25 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<57> LOC=M26 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<58> LOC=J24 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<59> LOC=L26 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<60> LOC=J27 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<61> LOC=M25 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<62> LOC=L25 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<63> LOC=L24 | IOSTANDARD = SSTL18_II;

Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=V25 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=P24 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=F26 | IOSTANDARD = SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=J25 | IOSTANDARD = SSTL18_II;

Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<4> LOC=Y28 | IOSTANDARD = DIFF_SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<5> LOC=E26 | IOSTANDARD = DIFF_SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<6> LOC=H28 | IOSTANDARD = DIFF_SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<7> LOC=G27 | IOSTANDARD = DIFF_SSTL18_II;

Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<4> LOC=Y29 | IOSTANDARD = DIFF_SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<5> LOC=E27 | IOSTANDARD = DIFF_SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<6> LOC=G28 | IOSTANDARD = DIFF_SSTL18_II;Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<7> LOC=H27 | IOSTANDARD = DIFF_SSTL18_II;

INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102";INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102";INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256";INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256";INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";

INST "*/u_phy_calib_0/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51;INST "*/u_phy_calib_0/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128;INST "*/u_phy_calib_0/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130;INST "*/u_phy_calib_0/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131;

Save and close the UCF file.

Hardware / Generate Bitstream

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----------------------------------------------------------------------------------------------------------

Creating and compiling the software system

[RC] Applications / Project: TestApp_Memory_ppc440_0Make Project Inactive[RC] Applications / Project: TestApp_Peripheral_ppc440_0Make Project Inactive[RC] Applications / Default: ppc440_0_bootlopMark to Initialize BRAMs[DC] Add Software Application Project...

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Project Name: mpmcOK

Create a new folder in your project folder: 'source'. Inside it, create a new .c file: 'main.c'. The content of this file must be the following:

#include "xparameters.h"

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#include "stdio.h"

#include "xil_testmem.h"#include "xstatus.h"

#include "memory_writer_reader.h"

#define R_RST 0x0#define R_E 0x4#define R_WR 0x8#define R_Address 0xC#define R_DataInput 0x10#define R_DataOutput 0x14#define R_Done 0x18

//====================================================

int main (void) {u32 *memory;int i, data, address, done;

memory=(u32 *)XPAR_DDR2_SDRAM_MPMC_BASEADDR;

MEMORY_WRITER_READER_mWriteReg (XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_RST, 1);

xil_printf ("--------------------------------\r\n");

xil_printf ("Software (writing)...\r\n");for (i=0; i<10; i++) {

memory[i]=i;}

xil_printf ("Software (reading):\r\n");for (i=0; i<10; i++) {

data=memory[i];xil_printf ("M[%d] = %d\r\n", i, data);

}

xil_printf ("Hardware (reading):\r\n");address=0;for (i=0; i<10; i++) {

MEMORY_WRITER_READER_mWriteReg (XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_WR, 1);

MEMORY_WRITER_READER_mWriteReg (XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_Address, address);

MEMORY_WRITER_READER_mWriteReg (XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_E, 1);

do {done=MEMORY_WRITER_READER_mReadReg

(XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_Done);} while (done!=1);data=MEMORY_WRITER_READER_mReadReg

(XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_DataOutput);xil_printf ("M[%d] = %d\r\n", i, data);address=address+4;

}

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xil_printf ("--------------------------------\r\n");

xil_printf ("Hardware (writing)...\r\n");address=0;for (i=0; i<10; i++) {

data=memory[i];data=data+10;MEMORY_WRITER_READER_mWriteReg

(XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_WR, 0);MEMORY_WRITER_READER_mWriteReg

(XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_Address, address);MEMORY_WRITER_READER_mWriteReg

(XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_DataInput, data);MEMORY_WRITER_READER_mWriteReg

(XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_E, 1);do {

done=MEMORY_WRITER_READER_mReadReg (XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_Done);

} while (done!=1);address=address+4;

}

xil_printf ("Software (reading):\r\n");for (i=0; i<10; i++) {

data=memory[i];xil_printf ("M[%d] = %d\r\n", i, data);

}

xil_printf ("Hardware (reading):\r\n");address=0;for (i=0; i<10; i++) {

MEMORY_WRITER_READER_mWriteReg (XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_WR, 1);

MEMORY_WRITER_READER_mWriteReg (XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_Address, address);

MEMORY_WRITER_READER_mWriteReg (XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_E, 1);

do {done=MEMORY_WRITER_READER_mReadReg

(XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_Done);} while (done!=1);data=MEMORY_WRITER_READER_mReadReg

(XPAR_MEMORY_WRITER_READER_0_BASEADDR, R_DataOutput);xil_printf ("M[%d] = %d\r\n", i, data);address=address+4;

}

return 0;}

[DC] Applications / Project: mpmc / SourcesSelect the source/main.c file, just created.

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Software / Build All User ApplicationsIt could show some errors about 'undefined reference to xil_io_out32 or xil_io_out'. To solve this, open the 'mpmc/ppc440_0/include/memory_writer_reader.h' and replace all the occurrences of 'xil_io_out32' with 'XIo_Out32' and all the occurrences of 'xil_io_in32' with 'Xio_In32'. Save the file and compile the software again. The errors should disappear.

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----------------------------------------------------------------------------------------------------------

Testing the system

Connect the FPGA card to Tera Term (console).

Device Configuration / Download BitstreamDebug / Launch XMD...

OK

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OK

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cd mpmcdow executable.elfrun

The output in console must be:

--------------------------------Software (writing)...Software (reading):M[0] = 0M[1] = 1M[2] = 2M[3] = 3M[4] = 4M[5] = 5M[6] = 6M[7] = 7M[8] = 8M[9] = 9Hardware (reading):M[0] = 0M[1] = 1M[2] = 2M[3] = 3M[4] = 4M[5] = 5M[6] = 6M[7] = 7M[8] = 8M[9] = 9--------------------------------Hardware (writing)...Software (reading):M[0] = 10M[1] = 11

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M[2] = 12M[3] = 13M[4] = 14M[5] = 15M[6] = 16M[7] = 17M[8] = 18M[9] = 19Hardware (reading):M[0] = 10M[1] = 11M[2] = 12M[3] = 13M[4] = 14M[5] = 15M[6] = 16M[7] = 17M[8] = 18M[9] = 19

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Documents

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