UNIVERSITY OF CALIFORNIA

College of Engineering

Department of Electrical Engineering and Computer Sciences

Yue Lu Homework 2 EECS 240Solution

1. (a) Solution:The NMOS common-source amplifier circuit is shown below:

For this circuit, we have the following equations for DC gain Av

, bandwidth wbw

, transistor gm

and totalloading cap:

Av

wbw

=gm

Cp

+ CL

(1)

Notice that the loading capacitance Cp

merely comes from the drain capacitance of the transistor and itfollows that:

Cp

= gCgg

= ggm

wT

(2)

Combining (1) and (2) we can get:

gm

=A

v

wbw

CL

1� gAv

wbw

/wT

(3)

Since gm

= 2IDS

/V ⇤, the required bias current IDS

can be expressed as:

IDS

=1

2gm

V ⇤ =1

2

Av

wbw

CL

V ⇤

1� gAv

wbw

/wT

(4)

We can then get the DC power expression as follows:

PDC

= IDS

VDD

=1

2

Av

wbw

CL

V ⇤VDD

1� gAv

wbw

/wT

(5)

(b) Solution:Now we are given the following specs/targets:1) C

L

= 20pF2) Unity-gain band-width = 1GHz -> A

v

wbw

= 2pG rad/s3) A

v

> 504) V

DS

> 0.4V5) Minimize P

DC

We need to optimize our CS amplifier to meets these specs/targets. If we take a closer look at (5), werealize that the design parameters (i.e. parameters you need to decide) are literallyV ⇤, w

T

, g and the implicitdesign choice of a channel length L. It looks like we have a lot of parameters to worry about. However,notice that since w

T

and g are both functions of V ⇤ and L, we really only have two design parameters todecide.

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One important thing to remember here is that neither wT

or g is a function of device widthW 1. Thisindicates that we are able to use a device with an arbitrary width (e.g. the 1mm width we used in HW#1)to extract w

T

and gas a function of V ⇤ and L. Once we get these data, we will be able to plot PDC

as afunction of V ⇤ and L using (5) and therefore find the optimum design parameters.

Now let’s go step by step to implement the design:Step 1 - setup a device characterization bench:We can have a device characterization bench as follows (basically the same as what you have in HW#1):

Notice here we choose W = 1mm as the unit transistor size and set VDS

= 0.4V to meet spec 4). Spec 1)and 2) directly set the values in equation (5), therefore we only need to meet spec 3) and 5).

Step 2 - find the optimum channel length and bias:Now we sweep V

GS

(V ⇤) and L with this setup, we will generate the Av

(= gm

ro

in our case) vs. Vgs

(V ⇤)and L contour and the P

DC

vs. Vgs

(V ⇤) and L contour (using equation (5)):2

1W resides in both the numerator and denominator of the wT and g expression and therefore it is cancelled2Note here we only swpet Vgs up to 0.6V as it gives V ⇤ up to 0.4V in order to make sure the device is in saturation region.

2

Note here the red region in the Pdc

contour actually corresponds to the negative Pdc

values from equation(5) when its denominator becomes negative. It simply means we cannot build our amplifier with thesesettings.

From these plots, we can see that we need >80nm channel length and the optimum bias Vgs

value isbetween 200-300mV. We can further process the P

dc

curve by discarding the data points failing to meet thegain requirement. The new P

dc

contour is shown below:

From this contour, it it easy to find the optimum design point from these data. The minimum power weget is P

DC

= 5.7mW and we achieve a DC gain of Av

= 55.7. The corresponding design parameters are:(

L = 80nm

V ⇤ = 86.1mV (Vgs

= 220mV )

Step 3 - find device width:Now since we know we need a I

DC

= 5.7mA for our design and we know the ids

/mm value from thecharacterization bench, we can then decide the size of the amplifier to be:

W =IDC

ids

/mm= 3436 mm (6)

3

Step 4 - simulation verification:With this bias and sizing, we can set up the following testbench:

Notice here the opamp is used to define the DC gate voltage given the VDS

value we defined and theoptimum I

DC

current and we found. Rbig

and Cbig

are the AC/DC blocks used to isolate the DC bias pathfrom the signal path.

Now we set Vds

= 0.4V, IDC

= 5.7mA and size the transistor to be 3436mm/80nm to conduct AC analysis.We will able to get the following frequenc response:

From the plot, we see that the DC gain is about 55.7 or 35dB and we have a unity-gain (Gain = 0dB)bandwidth of 1GHz. It matches our design!

We can further sweep Vds

from 50mV to 950mV with other parameters unchanged to get the Av0 (V/V,

not dB for this plot) vs. Vds

plot as follows:

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As can be seen, when Vds

becomes too small, the transistor will enter “triode” region where the gain ofthe amplifier starts to drop substatially.

(c) Solution:Repeat the same steps in (b), we will be able to determine the following optimum design parameters for

Vds

= 0.3� 0.8V cases:

Vds(V) 0.3 0.4 0.5 0.6 0.7 0.8L (nm) 80 80 80 80 80 80

V* (mV) 91.2 86.1 86.3 84.3 84.5 84.6IDC(mA) 6.25 5.72 5.70 5.68 5.66 5.65W(mm) 1585 3437 3283 5023 4804 4602

Av0(V/V) 53.2 55.7 56.6 57.3 57.6 57.6

We can verify these design using the same testbench as shown in (b) to get the following gain vs frequencyplot:

Again, the simulated results match our design constraints.The current as a function of output swing is shown below:

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(d) Solution:A single-stage cascode configuration is shown below:

Notice the overall effective transconductance Gm

of the cascode stage is approximately equal to thetransconductance of the input device g

m,in

.3In this particular design, let’s first make the following design choices:41) The size of the cascode device Mcas is identical to the input transistor Min - i.e. W

cas

= Win

, Lcas

=Lin

2) The bias of the cascode device is identical to the input transistor. This means the Vds

of Min is halfof V

out,DC

and Vgcas

= (Vin,DC

+ Vout,DC

/2)3) With 1) and 2), the gain of the cascode stage will simply be A

v0 t A2v0,in = (g

m,in

ro

)2

After making these initial design choices, the new design constraint becomes:Now we are given the following specs/targets:1) C

L

= 20pF2) Unity-gain band-width = 1GHz -> A

v0wbw = 2pG rad/s3) A

v0 > 50 ->Av0,in > 7.07 -> 50nm channel length is enough to meet this requirement!

4) VDS

> 0.3V � 0.8V -> VDS,in

= VDS,cas

> 0.15V � 0.4V5) Minimize P

DC

Now we can use the same design steps in part (b) to find the optimized design parameters for Min (andMcas). The results are shown below:

3A more accurate method is to characterize the overall Gm directly. This requires a different characterization testbench.4Other design choices on the relative sizing and bias for the cascode device are also acceptable.

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Vds(V) 0.3 0.4 0.5 0.6 0.7 0.8L (nm) 50 50 50 50 50 50

V* (mV) 83.3 84.1 84.1 82.7 82.7 83.2IDC(mA) 5.60 5.56 5.56 5.51 5.51 5.50Win,(mm) 3441 2767 2767 3613 3613 3257

Av0,in (V/V) [Av0(V/V)] 10.9 [118.8] 11.7 [136.9] 11.7 [136.9] 11.9 [141.6] 11.9 [141.6] 11.9 [141.6]The testbench used to verify the design is shown below:

Again, the auxiliary opamp is used to define DC bias voltages; large resistors and caps are used to isolatethe DC path from the signal path.

The simulated gain vs. frequency is shown below:

Not too surprisingly, they match both the gain and unity-gain frequency specs. One thing to notice hereis that we actually have a much larger gain ((>100) than required (>50) which is mostly due to the minimumchannel length (>=50nm) constraint.

The current vs. output swing is plotted below:

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(e) Solution:The overlaid plot is shown below:

Notice here for the single-stage cascode design, it actually consumes less power than a common-sourceamplifier. The benifit mostly come from the reduced self-loading C

p

from the use of shorter channel devices.In this particular design, since the required unity-gain bandwidth is not very high, the self-loading termdoesn’t play a large role and thus the power advantage is not obvious. If we keep on increasing the unity-gain bandwidth requirement, you will gradually see larger power savings from using the cascode design dueto the reduced self-loadings.

2. The flicker noise spectral density at the output of the transistor and the total integrated flicker noiseare:

i21/f�f

=K

f

ID

L2Cox

f

i21/f =

ˆf

hi

f

lo

Kf

ID

L2Cox

fdf =

Kf

ID

L2Cox

lnfhi

flo

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The input referred noise is then calculated as

v21/f =K

f

ID

g2m

L2Cox

lnfhi

flo

=K

f

V ⇤2

4ID

L2Cox

lnfhi

flo

From homework1, we have ID

= 0.13mA with V ⇤ = 200mV for device size 1µm/50nm, therefore thecurrent in this problem is roughly 1.3mA. The total input referred noise integrated from 1Hz to 2GHz istherefore

v21/f =1.1⇥ 10�28 ⇥ 0.22

4⇥ 0.0013⇥ (50⇥ 10�9)2 ⇥ 30⇥ 10�3ln(2⇥ 109) = 2.42⇥ 10�10V 2

v1/f,rms

= 15.5µV

If the lower limit of frequency range reduces to 1week�1, the voltage noise increases by a factor ofpln(2⇥ 109 ⇥ 7⇥ 24⇥ 3600)/ln(2⇥ 109) =1.27. The new input referred noise is therefore 19.7µV rms. In

order to maintain the same input referred flicker noise, the current needs to increased by ln(2 ⇥ 109 ⇥ 7 ⇥24⇥ 3600)/ln(2⇥ 109) = 1.62.

3. The total input referred noise is calculated as

v2in

= 4kT�1

gm1

(1 +gm2

gm1

) = 4kT�1

gm1

(1 +V ⇤1

V ⇤2

)

Thus, to minimize the total noise, the V* of M2 should be made much larger than the V* of M1. Inother words, we would want to make the gm of M1 much larger than that of M2.

4. Noise calculation.(a) The output noise density from transistor M1 is

4kT�gm1|

R1gm2R2

(1 + sR1C1)(1 + sR2C2)|2

(b) The output noise density from Rs

is

4kTRs

g2m1|

R1gm2R2

(1 + sR1C1)(1 + sR2C2)|2

The output noise density from R1 is

4kT1

R1| R1gm2R2

(1 + sR1C1)(1 + sR2C2)|2

The output noise density from R2 is

4kT1

R2| R2

1 + sR2C2|2

The output noise density from transistor M2 is

4kT�gm2|

R2

1 + sR2C2|2

(c) The integrated noise can be calculated based on the integral provided in lecture notes as

v2out

= kT (�gm1 +R

s

g2m1 +

1

R1)

g2m2R

21R

22

R1C1 +R2C2+ kT (�g

m2R2 + 1)1

C2

(d) The gain from the supply to the output is

Avdd

= (gm2R2

1 + sR1C1� 1)⇥ 1

1 + sR2C2

Notice the minus sign is due to the inversion from the second stage common source amplifier. The PSRRis therefore

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PSRR = |Asig

Avdd

| = | gm1gm2R1R2

gm2R2 � 1� sR1C1

| = gm1gm2R1R2p

(gm2R2 � 1)2 + !2R2

1C21

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