Unit2 Basic Structures of VHDL

UNIT 2BASIC STRUCTURES OF VHDL

TOPICS

Entities and ArchitecturesCoding StylesIdentifiers, Spaces, Comments, and HeadersSignals and Data TypesOperators

DESIGN UNIT

It is a VHDL construct that can be separately compiled and stored in a design libraryIt consists of a context clause followed by a library unit.

A context clause consists of a library clause and a use clauseExample of a context clause:

library ieee;use ieee.std_logic_1164.all;

Presenter

Presentation Notes

Design Unit It is a VHDL construct that can be separately compiled

LIBRARY UNIT

It is the compilation of specific design units It has 5 kinds:

Entity declarationArchitecture bodyPackage declarationPackage bodyConfiguration declaration

DESIGN ENTITY

It is the basic unit of a hardware design.It has at least one pair of:

An entity declaration that defines the inputs and outputs—the ports—of this design; andAn architecture body that defines what the design actually does, using a single concurrent assignment.

Design Entity

Entity Declaration (external view)

Architecture Body (internal function)

DESIGN ENTITY

ENTITY DECLARATION

It defines the entity’s name and its interface.It includes the ff.:

Entity namePort statement/list

Port namesDirection (either in, out, or inout)TypeGeneric list (optional)

ENTITY DECLARATION

Syntax:entity entity_name is

port(port_name : direction type);end entity [entity_name];

Example:entity Full_Adder is

port(A, B, Cin : in std_logic;Sum, Cout : out std_logic);

end Full_Adder ;

PORT MODES

A port’s mode specifies its direction of information transfer.There are 5 modes, namely:

inoutinoutbufferlinkage (removed)

If no mode is specified, default is in.

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Presentation Notes

Mode linkage Has primarily been used to link VHDL models with models written in other languages or to interface with non-VHDL simulators Not supported for synthesis in IEEE Std 1076.6 and is being considered for removal from future versions

PORT MODES

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Presentation Notes

Port Modes In Input to a design entity Architecture body statements can only read a value from the port; it’s not allowed to assign a value Out Output to a design entity Architecture body statements can only write (assign) a value to the port; it’s not allowed to read a value from it Inout Bidirectional Architecture body statements can read and write the port Buffer An output port that can also be read from inside the architecture body Architecture body statements can read and write the port

ENTITY DIAGRAM

entity(architecture)

Inputs Outputs

ARCHITECTURE BODY

The architecture describes the actual function—or contents—of the entity to which it is bound. It includes the ff.:

Declarative part wherein the components and signals are being declaredStatement part wherein the component instantiation statements, signal assignments, and behavioral constructs (such as process statements) are stated

ARCHITECTURE BODY

Syntax:architecture arch_name of entity_name is

declarative partbegin

statement partend architecture arch_name;

ARCHITECTURE BODY

Example:architecture Structural of Full_Adder is

component Half_Adder isPort ( A, B : in STD_LOGIC;

Sum, Cout : out STD_LOGIC);end component;signal sumsig, coutsig1, coutsig2 : STD_LOGIC;

beginHA1: Half_Adder port map ( A, B, sumsig, coutsig1 );HA2: Half_Adder port map ( A => sumsig,

B => Cin,Sum => Sum,Cout => coutsig2);

Cout <= coutsig1 or coutsig2;end Structural;

CODING STYLES

Architectures can be written in any of the ff:Dataflow

Uses only concurrent signal assignmentsFor low-level (very basic) design entities

BehavioralUses only process statementsFor systems whose function is algorithmic

StructuralUses only component instantiation statementsAppropriate for design entities comprised of several low-level design entities

Mixed

EXAMPLE OF DATAFLOW STYLE

architecture Dataflow of Full_Adder isbegin

Sum <= A xor (B xor Cin);Cout <= (A and B) or (A and (B xor Cin));

end Dataflow;

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Presentation Notes

Dataflow description a concurrent representation of the flow of control and movement of data descriptions cannot serve as an end-user or non-technical documentation media this level is abstract enough for a technically oriented designer slower than the input-to-output mapping of the behavioral descriptions

EXAMPLE OF BEHAVIORAL STYLE

architecture Behavioral of Full_Adder isbegin

process (A, B, Cin)begin

if A = '1' thenSum <= B xnor Cin;Cout <= B or Cin;

elseSum <= B xor Cin;Cout <= B and Cin;

end if;end process;

end Behavioral;

Presenter

Presentation Notes

Behavioral description the most abstract a softwarelike procedural form no detail as for design implementation appropriate for fast simulation of complex hardware units, verification and functional simulation of design ideas, modeling standard components, and documentation accessible to non-engineers as well as to the end-users a good documentation media After the keyword process is a list of signals inside parentheses, called sensitivity list. A sensitivity list enumerates exactly which signals cause the process to be executed. Whenever there is an event on any of the signals in a process’s sensitivity list, the process is executed.

EXAMPLE OF STRUCTURAL STYLE

architecture Structural of Full_Adder iscomponent Half_Adder is

Port ( A, B : in STD_LOGIC;Sum, Cout : out STD_LOGIC);

end component;signal sumsig, coutsig1, coutsig2 : STD_LOGIC;

beginHA1: Half_Adder port map ( A, B, sumsig, coutsig1 );HA2: Half_Adder port map ( A => sumsig,

B => Cin,Sum => Sum,Cout => coutsig2);

Cout <= coutsig1 or coutsig2;end Structural;

Presenter

Presentation Notes

Structural description the lowest and most detailed the simplest to synthesize into hardware includes a list of concurrently active components and their interconnections a gate-level description provides input for detailed timing simulations The lower-level design entities appear as a component in a structural architecture. An easier way to declare a component is to copy the exact entity declaration and change the keyword entity with component. Take note that the signals used to connect between components must also be declared before the keyword begin together with the component declaration. In component instantiation, each instance must be uniquely named (but still understandable). Following the component name is the keyword port map. Port mapping can either be positional association (as shown in instance HA1) or named association (as shown in instance HA2).

PORT MAP

A port map indicates how a design entity is connected in a structural architecture. Each port is associated with either

Signal in the enclosing architectureAn expressionKeyword open to indicate no connection

An input port may be left open only if a default value has been specified in its entity declaration

Two waysNamed associationPositional association

PORT MAP

Positional AssociationSignals are associated based on their relative positions as specified in the entity’s declarationMore concise and applicable for simple systems

Named AssociationEach association is explicit and the listing order is of no concernMore readable and less error prone

SEATWORK 2-1A B C X Y0 0 0 0 10 0 1 1 00 1 0 1 10 1 1 0 01 0 0 1 01 0 1 0 01 1 0 0 01 1 1 1 1

1. Given the following truth table:

a. Write a canonical sum-of-products Boolean equation for each output.

b. Write a complete dataflow VHDL description of the design entity that accomplishes the function defined by the truth table.

SEATWORK 2-1

2. Write a structural VHDL description of the diagram shown. Use named association in the port maps. Assume that components ANDgate, Orgate, and NOTgate already exist.

IDENTIFIERS

A VHDL identifier is used to identify various VHDL objects: design entities, signals, procedures, functions, processes, etc.Rules:

Case insensitiveCan only be made up of alphabetic, numeric, and underscore charactersMust not be a keywordFirst character must be a letter (alphabet)Two underscores in succession is not allowed

IDENTIFIERS

Usual programming rules for identifiers:Meaningful non-cryptic names should be used (based on English words)Use mixed-case consistentlyAvoid using excessively long identifiers Avoid confusing identifiersExtended identifiers may consist of any character as long as it is enclosed in backslashes (‘\’) Strings in extended identifiers are case sensitive and must be used with extreme caution

KEYWORDS

SPACES, COMMENTS, & HEADERS

There’s no difference between one whitespace (space, carriage return) character or manyTwo hyphens (‘—’) are used to indicate line comments. There are no block comments.Each VHDL should include a header, that contains the ff:

the name(s) of the design units in the file;file name;a description of the code;limitations and known errors;any operating system and tool dependencies;the author(s), including a full address;a revision list, including dates.

EXAMPLE OF A HEADER-- Design unit : FullAdder (Entity and Architecture)---- File name : FAdder.vhd---- Description : Dataflow model of full adder circuit. Inputs of type -- STD_LOGIC.---- Limitations : None---- System : VHDL’93---- Author : Christine Bandalan-- : Department of Computer Engineering-- : University of San Carlos-- : Cebu City---- Revision : Version 1.0 07/12/05

OBJECTS

Object is a named item that has a value of a specified typeAn object’s class represents the nature of the object and how it is used.VHDL classes:

Signal – an object with a current and projected value Constant – an object whose value is fixVariable – an object with only a current valueFile – an object that consists of a sequence of values of a specified time

OBJECTS

An object’s type defines the set of values the object can assume and the set of operations that can be performed on those values.Object types:

Scalar – has a single indivisible value (either numeric or enumerated)Composite – consists of a collection of elements each with a valueAccess – provides access to objects of a given type (like pointers)File – provides access to objects containing asequenceof values of a given type (such as disk files)Protected – provides atomic and exclusive access to variables accessible to multiple processes (global)

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Presentation Notes

NOTE: only scalar and composite types are synthesizable

SIGNALS

Signals are objects that are used to connect concurrent elements (such as components, processes and concurrent assignments).It can be declared globally in an external package or locally within an architecture, block or other declarative region.Uses the assignment operator <= in passing value of one signal to anotherUses the assignment operator := in assigning initial values

PREDEFINEDSCALAR TYPES

Scalar

Enumeration

bit

boolean

character

Severity_level

File_open_kind

File_open_status

Integer Integer

Physical time

Floating real

discrete

numeric

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Presentation Notes

Scalar Types A scalar type represents a single indivisible value. Discrete types represent sets of distinct values Numeric types can be specified with a range that constrains the set of possible values. An enumeration type is declared by simply listing all possible values. Type character is an enumeration type that contains a mixture of character literals and identifiers as elements. Type bit is an enumeration type used as a simple representation for a logic signal. A type derived from another type is a subtype. The type from which the subtype is derived is its base type.

STD_ULOGICValue State Strength

U uninitialized noneX unknown forcing0 0 forcing1 1 forcingZ none high impedanceW unknown weakL 0 weakH 1 weak- don’t care none

STD_ULOGIC• It is an unresolved type.• The state value denotes its logic level.• The strength denotes the electrical

characteristics of the source that drives the signal. These driving strengths are:• Forcing – signals driven by active output drivers

(such as that of a CMOS circuit)• Weak – are used to represent signals from resistive

drivers (such as pull-up resistor, or pull-down resistor outputs, or pass transistors)

• High impedance – represents the output of a 3-state buffer when it is not enabled

STD_ULOGIC• The uninitialized value is the default value

given to all std_ulogic signals before the start of simulation.

• The unknown value is used to represent a signal that is being driven, but whose value cannot be determined to be a 0 or a 1.

• Don’t care is interpreted by a synthesis tool as representing common don’t care condition used in logic design.

RESOLVED TYPE

A resolved type is a type declared with a resolution function.A resolution function is a function that defines the resulting (resolved) value of a signal.Std_logic is a subtype of std_ulogic declared in STD_LOGIC_1164.

RESOLUTION TABLE FOR STD_LOGICU X 0 1 Z W L H -

U U U U U U U U U UX U X X X X X X X X0 U X 0 X 0 0 0 0 X1 U X X 1 1 1 1 1 XZ U X 0 1 Z W L H XW U X 0 1 W W W W XL U X 0 1 L W L W XH U X 0 1 H W W H X- U X X X X X X X X

USE OF STD_LOGIC VS STD_ULOGIC

A disadvantage of using std_logic instead of std_ulogic is that signals that ate unintentionally multiply driven will not be detected as an erorduring compilation.IEEE recommends use of std_logic for the reason that the standard expects simulator vendors to design their simulators to optimize the simulation of models using the resolved subtype, but they need to optimize the simulation of models using the unresolved types

SCALAR LITERALS

A literal is a value that is expressed as itselfIt can be directly assigned to a signal or used in an expression that determines the value assigned to a signalLiterals don’t have an explicit typeOnly the ff. literals can be used in synthesizable descriptions:

CharacterEnumerationStringNumeric

SCALAR CONSTANTS

A constant is an object that is assigned a value only once, normally during declaration.Visibility rules are the same as for signals.Uses the keyword constant and the assignment operator :=For example:

constant high_impedance : std_logic := ‘Z’

COMPOSITE TYPESComposite

types

Array types

Unconstrained

Bit_vector string

constrained

Record types

COMPOSITE TYPE

A composite type consists of a collection of related elements that form either an array or a record.It may contain elements that are scalar, composite, or access type.

SOURCE

VHDL for Engineers, Kenneth Short, Pearson Education, Inc., 2009

VHDL Modular Design and Synthesis of Cores and Systems, Zainalabedin Navabi, Mc-Graw-Hill Companies, 2007

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Unit2 Basic Structures of VHDL