Unit2 Arithmetics

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    UNIT 2

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    Addition/subtraction of signed numbers

    si =

    ci+1=

    13

    7+Y

    1

    0

    0

    0

    1

    0

    1

    1

    0

    0

    1

    1

    0

    11

    0

    0

    1

    1

    0

    1

    0

    01

    0

    0

    0

    0

    1

    1

    1

    1

    0

    0

    0

    0

    1

    1

    11

    Example:

    10= = 0

    01 1

    11 1 0 0

    1

    1 1 10

    Legend for stage i

    xi

    yi

    Carry-inci

    Sumsi

    Carry-outci+1

    X

    Z

    + 6 0+xiyi

    si

    Carry-outci+1

    Carry-inci

    xiyici

    xiyici

    xiyici

    xiyici xi yi ci =

    + + +

    yicixicixiyi+ +

    At the ith stage:Input:

    ci is the carry-in

    Output:

    si is the sum

    ci+1 carry-out to (i+1)st

    state

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    Addition logic for a single stage

    Full adder(FA)

    ci

    ci 1+

    si

    Sum Carry

    yixi

    ci

    yi

    xi

    ci

    yi

    x

    i

    xi

    ci

    yi

    si

    ci 1+

    Full Adder (FA): Symbol for the complete circuit

    for a single stage of addition.

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    n-bit adderCascade n full adder (FA) blocks to form a n-bit adder.Carries propagate or ripple through this cascade, n-bit ripple carry adder.

    FA c0

    y1

    x1

    s1

    FA

    c1

    y0

    x0

    s0

    FA

    cn 1-

    yn 1-

    xn 1-

    cn

    sn 1-

    Most significant bit(MSB) position

    Least significant bit(LSB) position

    Carry-in c0 into the LSB position provides a convenient way to

    perform subtraction.

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    K n-bit adderK n-bit numbers can be added by cascading kn-bit adders.

    n-bit c0

    yn

    xn

    sn

    cn

    y0

    xn 1-

    s0

    ckn

    sk 1-( )n

    x0

    yn 1-

    y2n 1-

    x2n 1-

    ykn 1-

    sn 1-

    s2n 1-

    skn 1-

    xkn 1-

    addern-bitaddern-bitadder

    Each n-bit adder forms a block, so this is cascading of blocks.Carries ripple or propagate through blocks, Blocked Ripple Carry Adder

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    n-bit subtractor

    FA 1

    y1

    x1

    s1

    FAc1

    y0

    x0

    s0

    FAcn 1-

    yn 1-

    xn 1-

    cn

    sn 1-

    Most significant bit(MSB) position

    Least significant bit(LSB) position

    RecallXYis equivalent to adding 2s complement ofYtoX.

    2s complement is equivalent to 1s complement + 1.

    XY = X + Y + 1

    2s complement of positive and negative numbers is computed similarly.

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    n-bit adder/subtractor (contd..)

    Add/Subcontrol

    n-bit adder

    xn 1-

    x1

    x0

    cn

    sn 1- s1s0

    c0

    yn 1-

    y1

    y0

    Add/sub control = 0, addition.

    Add/sub control = 1, subtraction.

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    Detecting overflows

    Overflows can only occur when the sign of the two operands isthe same.

    Overflow occurs if the sign of the result is different from the

    sign of the operands.

    Recall that the MSB represents the sign. xn-1, yn-1, sn-1 represent the sign of operand x, operand yand result s

    respectively.

    Circuit to detect overflow can be implemented by the

    following logic expressions:

    111111 nnnnnn syxsyxOverflow

    1 nn ccOverflow

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    Computing the add timeConsider 0th stage:

    x0 y0

    c0c1

    s0

    FA

    c1 is available after 2 gate delays.

    s1 is available after 1 gate delay.

    ci

    yi

    xi

    ci

    yi

    xi

    xi

    ci

    yi

    si

    ci 1+

    Sum Carry

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    Computing the add time (contd..)

    x0 y0

    s2

    FA

    x0 y0x0 y0

    s1

    FAc2

    s0

    FAc

    1

    c3

    c0

    x0 y0

    s3

    FA

    c4

    Cascade of 4 Full Adders, or a 4-bit adder

    s0 available after 1 gate delays, c1 available after 2 gate delays.

    s1

    available after 3 gate delays, c2

    available after 4 gate delays.

    s2 available after 5 gate delays, c3 available after 6 gate delays.

    s3 available after 7 gate delays, c4 available after 8 gate delays.

    For an n-bit adder,sn-1is available after 2n-1 gate delayscnis available after2ngate delays.

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    Fast additionRecall the equations:

    iiiiiii

    iiii

    cycxyxc

    cyxs

    1

    Second equation can be written as:

    iiiiii cyxyxc )(1

    We can write:

    iiiiii

    iiii

    yxPandyxGwhere

    cPGc

    1

    Giis called generate function andPiis called propagate functionGi and Pi are computed only from xiand yi and not ci, thus they canbe computed in one gate delay after Xand Yare applied to the

    inputs of an n-bit adder.

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    Carry lookaheadci1 Gi Pici

    ci Gi1 Pi1ci1

    ci1 Gi Pi(Gi1 Pi1ci1)

    continuing

    ci1 Gi Pi(Gi1 Pi1(Gi2 Pi2ci2 ))

    until

    ci1 Gi PiGi1 PiPi1Gi2 . . PiPi1. .P1G0 PiPi1. ..P0c0

    All carries can be obtained 3 gate delays afterX, Yandc0are applied.

    -One gate delay for Pi and Gi-Two gate delays in the AND-OR circuit for ci+1

    All sums can be obtained 1 gate delay after the carries are computed.Independent of n, n-bit addition requires only 4 gate delays.This is called Carry Lookahead adder.

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    Carry-lookahead adder

    Carry-lookahead logic

    B cell B cell B cell B cell

    s3

    P3

    G3

    c3

    P2

    G2

    c2

    s2

    G1

    c1

    P1

    s1

    G0

    c0

    P0

    s0

    .c

    4

    x1

    y1

    x3

    y3

    x2

    y2

    x0

    y0

    Gi

    ci

    ..

    .

    Pi

    si

    xi

    yi

    B cell

    4-bit

    carry-lookahead

    adder

    B-cell for a single stage

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    Carry lookahead adder (contd..) Performing n-bit addition in 4 gate delays independent ofn

    is good only theoretically because of fan-in constraints.

    Last AND gate and OR gate require a fan-in of (n+1) for a n-bit adder. For a 4-bit adder (n=4) fan-in of 5 is required. Practical limit for most gates.

    In order to add operands longer than 4 bits, we can cascade4-bit Carry-Lookahead adders. Cascade of Carry-Lookaheadadders is called Blocked Carry-Lookahead adder.

    ci1 Gi PiGi1 PiPi1Gi2 ..PiPi1..P1G0 PiPi1...P0c0

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    4-bit carry-lookahead Adder

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    Blocked Carry-Lookahead adder

    c4 G3 P3G2 P3P2G1 P3P2P1G0 P3P2P1P0c0

    Carry-out from a 4-bit block can be given as:

    Rewrite this as:

    P0I

    P3P2P1P0

    G0IG3 P3G2 P3P2G1 P3P2P1G0

    Subscript I denotes the blocked carry lookahead and identifies the block.

    Cascade 4 4-bit adders, c16can be expressed as:

    c16 G3I P3

    IG2

    I P3

    IP2

    IG1

    IP3

    IP2

    IP1

    0G0

    IP3

    IP2

    IP1

    0P0

    0c0

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    Blocked Carry-Lookahead adder

    Carry-lookahead logic

    4-bit adder 4-bit adder 4-bit adder 4-bit adder

    s15-12

    P3

    IG3

    I

    c12

    P2

    IG2

    I

    c8

    s11-8

    G1

    I

    c4

    P1

    I

    s7-4

    G0

    I

    c0

    P0

    I

    s3-0

    c16

    x15-12

    y15-12

    x11-8

    y11-8

    x7-4

    y7-4

    x3-0

    y3-0

    .

    Afterxi, yi and c0are applied as inputs:- Gi and Pi for each stage are available after 1 gate delay.- PI is available after 2 and GI after 3 gate delays.- All carries are available after 5 gate delays.- c16 is available after 5 gate delays.- s15 which depends on c12 is available after 8 (5+3)gate delays

    (Recall that for a 4-bit carry lookahead adder, the last sum bit isavailable 3 gate delays after all inputs are available)

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    Multiplication of unsigned numbers

    Product of 2 n-bit numbers is at most a 2n-bit number.

    Unsigned multiplication can be viewed as addition of shifted

    versions of the multiplicand.

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    Multiplication of unsigned

    numbers (contd..) We added the partial products at end.

    Alternative would be to add the partial products at each stage.

    Rules to implement multiplication are:

    If the ith bit of the multiplier is 1, shift the multiplicand and add the

    shifted multiplicand to the current value of the partial product.

    Hand over the partial product to the next stage

    Value of the partial product at the start stage is 0.

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    Multiplication of unsigned numbers

    ith multiplier bit

    carry incarry out

    jth multiplicand bit

    ith multiplier bit

    Bit of incoming partial product (PPi)

    Bit of outgoing partial product (PP(i+1))

    FA

    Typical multiplication cell

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    Combinatorial array multiplier

    Multiplicand

    m3 m2