Unit II : Memory Management

Memory Management in 80386-Segment Translation, Page Translation, Combining Segment and Page

Translation.

Contents

• Memory Management in 80386-Segment Translation, Page Translation, Combining Segment and Page Translation,

• Operating in Real Mode, Virtual x86 Mode.

• Protection: Need of Protection, Overview of 80386DX protection Mechanism, Privilege levels

Address Spaces of 80386

• There are 3 address spaces of 80386:

– Logical address space

– Linear address space

– Physical address space

Machine language programs use logical address for both

instruction and operand address. Segmentation unit

translates logical address into 32-bit linear address

space.

When paging unit is enabled, paging unit translates the

linear address space into physical address space.

If the paging unit is disabled ,the linear address

corresponds to the physical address.

Logical & Linear Address

• Logical Address: Consists of

a) segment selector

b) offset.

The selector is available in segment register.

The offset is calculated by the processor by adding base, index and displacement fields.

The segmentation unit converts the logical address to linear address using the segment descriptor indicated by the segment selector.

• Linear Address :

o When the paging is disabled the linear address is

actually the physical address .

o When the paging is enabled the linear address is

converted to physical address through paging .

Memory Address Translation

SELECTOR OFFSET Logical Address

DIRECTORY TABLE OFFSET Linear Address

Physical

Address

Segment Translation

• To perform this translation, the processor uses

the following data structures:

–Descriptors

–Descriptor tables

–Selectors

–Segment Registers

A segment selector is loaded into a segment register (cs, ds, etc.) to select one of the regular segments in the system as the one addressed via that segment register.

Segment Selector – 16 bit

Segment Descriptor

• Describes a segment

• Must be created for every segment

• Is created by the programmer

• Determines a base address of the segment

• Determines a size of the segment

• Determines a type of the segment

• Determines a privilege level of the segment

Segment Descriptor Defines followings

• Base address (32-bits)

• Segment limit (20 bits)

• Type of segment (4 bits)

• Privilege level of segment (2 bits)

• Whether segment is physically, present (1 bit)

• Whether segment has accessed before (1 bit)

• Granularity of limit field (1 bit)

• Size of operands within segment (1 bit)

• Intel reserved bit (1 bit)

• AVL bit (1 bit)

• Default size (1 bit)

Segment Descriptor 0 15

Segment Limit ( 0 – 15 )

Base Address ( 0 – 15 )

P DPL S TYPE Base Address(16 – 23)

Base Address

( 24 – 31 ) G

D

/

B

0

A

V

L

Segment

Limit

( 16 – 19 )

1 – Segment is present

in Memory

Descriptor Privilege

Level

0- System Segment

1- Code/Data Segment

Type of Descriptor 0 – data read-only

1 – data read-only, accessed

2 – data read/write

8 – code execute only

9 – code execute only, accessed

A – code execute/read

Granularity bit for limit

field

0 – segment size 64kB

1 – no. of 4KB pages

1 - 32 bit operations

0 - 16 bit operations

unused Available to

Programmer

Base Address: Starting address of the memory segment Limit:

•Length of the segment minus 1. •20-bits allows segments up to 1 MB. •This value is shifted by 12 bits to the left when the G (Granularity bit) is set to 1.

G (Granularity) Bit: When G=0, segments can be 1 byte to 1MB in length. When G=1, segments can be 4KB to 4GB in length.

Segment Descriptor

U bit: User (OS) defined bit. X Bit:

Reserved by Intel D bit: Indicates how the instructions (80386 and up) access register and memory data in protected mode.

When D=0, instructions are 16-bit instructions, with 16-bit offsets and 16-bit registers. Stacks are assumed 16-bit wide and SP is used. When D=1, 32-bits are assumed. Allows 8086-80286 programs to run.

Segment Descriptor

GDT and LDT • Two types of descriptor tables are used by processor when

working in protected-mode.

• GDT (Global Descriptor Table) is used for holding descriptor entries of operating system segments.

• LDT (Local Descriptor Table) contains entries of normal application segments.

• During initialization, the kernel creates a single GDT which is kept in memory until either the operating system terminates or until the processor is switched back to real-mode.

• Whenever new application starts, the operating system creates a new LDT to hold the descriptor entries which represent the segments used by new task. This makes it possible for operating system to isolate each task's address space by enabling a different LDT whenever a task switch occurs.

• GDT – Unique

– Hold segments

– System , non system.

LDT • Is optional

• Extends GDT

• Individual task

• IDT – Descriptors for ISR

• GDTR-

– 48 bit reg.

– LIMIT of GDT –(16bits)

– Max size of GDT-65536 bytes

– IDTR (Same as GDTR)

– LDTR

– 16 bit Reg.

– Specifies address of LDT descr. In GDT

Segment

Selector

Base

Address

Limit Access

Information

32-bit Linear Base Address 16 bit Table Limit

Hidden Part of Segment Selector

GDTR is a 48 bit Register

Segment

Selector

32-bit Linear Base

Address

16 bit Table

Limit

LDTR

2) Local Descriptor Table (LDT):

• Defined on a task basis in a multitasking system.

• Each task has its own LDT, but tasks can also share a

few different LDTs.

3) Interrupt Descriptor Table(IDT):

• It defines interrupt or exception handling routine.

• It is a direct replacement for the interrupt vector table

used in 8086 systems.

• Exactly one GDT and one IDT must be defined for

the 80386 to operate in protected mode.

Segment Translation

University Questions

Q1) What are different types of descriptors? [3]

Q2) What is TSS descriptors? [3]

Q3)

Types of Segment Descriptors

Access Rights for Segments

Expansion Direction for data and stack

segment

Code Segment Descriptor Access Right Byte

Configuration

Non System Descriptor

S=1

Non System

System Descriptor

S=0

System Descripors

Type Defines Type Defines

0 Reserved by Intel 8 Reserved by Intel

1 Available 80286 TSS 9 Available Intel 80286

TSS

2 LDT A Undefined

3 Busy 80286 TSS B Busy Intel 80386DX

4 80286 Call Gate C Intel 80386DX Call

gate

5 Task Gate D Undefined

6 80286 Interrupt Gate E 80386DX Interrupt

Gate

7 80286 Trap Gate F 80386DX Trap Gate

• LDT Descriptors (S = 0, Type = 2):

• The LDT descriptors are present only in the Global Descriptor

Table (GDT).

• They contain the information about the local descriptor tables.

• The local descriptor table contains the segment descriptors,

which are unique to a particular task.

• The DPL (Descriptor privilege field) of this descriptor has

ignored because it can be access with only privilege level 0.

System Segment Descriptor

• TSS Descriptor (S = 0, Type = 1, 3, 9, B) :

• In a multitasking environment computer performs more than one

task at a time, and it also switch between the task.

• A task can be a single program, or it can be a group of related

programs.

• When it switches from task1 to task 2, it stores all the information

necessary to restart the task 1.

• It involves saving the contents of all of ‘the processor registers as

well as any read/write memory variables and the address of next

instruction to be executed. Such information is called state of the

task or context of the task.

• The 80386 uses a special segment called task state segment (TSS)

to store the state/context of the task.

• This segment can be address with the help of task state segment

(TSS) descriptor. The TSS descriptor contains information

about the location, size, and privilege level of a TSS.

System Segment Descriptor

• Gate Descriptors(S=0, TYPE=4-7, C, F):

• A gate is a special of the descriptor. It allows the 80386, which

automatically performs the protection checks. There are

following types of gate descriptors as follows:

• Call Gates:

– It has used to change privilege levels.

• Task gates:

– It has used to perform a task switch.

• Interrupt and trap gates:

– Both have used to specify interrupt service routines.

System Segment Descriptor

PAGING

• A memory-management scheme that permits the physical address space of a process to be non-contiguous.

• Physical memory broken into fixed-sized blocks called FRAMES and break logical memory into blocks of the same size called PAGE

• Every address generated by the CPU is divided into two parts: Page number and Page offset

• Paging translates Linear address to physical address

Physical address space with paging

• Supporting data structures

• PDBR

• PDE descr.

• Page directory table

• PTE descr.

• Page table

• Page frame

Page Directory Entry

Page Frame Address

(12-31)

Avail 0 0 0 A P

C

D

P

W

T

U W P

Base Address of Page Table Available for user

Accessed

Cache Disable

Page Wright through

User Page/System Page

Writable Present

• Accessed bit : Manually resettled

• User/supervisor`: if set : pages covered by this entry are accessible to all users

if clear : only for PL0,1,2

Read/Write bit : If U/S` is clear R/W` has no effect

But if U/S`=1 then pages covered by this entry will be write protected.

If R/W` is set : write privileges are allowed from PL3 code

U/S` R/W` Permitted level Permitted access levels 0,1,2

0 0 None Read/Write

0 1 None Read/Write

1 0 Read-Only Read/Write

1 1 Read/Write Read/Write (PL0)

Page Table Entry

Page Frame Address

(12-31)

Avail 0 0 D A P

C

D

P

W

T

U W P

Dirty

Paging

10 10 12

PDBR

Page Directory

Page Table 4KB Page

Translation Lookaside Buffer or Page

translation Cache:

• The 80386DX paging mechanism has designed to support demand paged virtual memory systems.

• Performance would degrade substantially if the processor was required to access two levels of tables (Page directory and page table) for every memory access.

• To solve this problem, the 80386DX stores the most recently used page table entries in an on-chip cache.

• This cache is called the Translation Lookaside Buffer (TLB).

• The TLB holds up to 32 page table entries.

• The 32-entry TLB coupled with a 4K page size,

results in coverage of 128K bytes of memory

addresses.

• Whenever program generates linear address that maps

to a page table entry (PTE) already in the cache, the

80386DX can use the cached information it has

internally.

• This saves two outside memory references,

improving performance in address translation.

• For many common multi-tasking systems, the TLB

will have a hit rate of about 98%. This means that the

processor will only have to access the two-level page

structure on 2% of all memory accesses.

Translation Lookaside Buffer (TLB)

Use of TLB • A Translation Look-aside Buffer (TLB) simplifies

the process. TLB is a page table cache, which stores the 32 recently accessed page table entries.

• The paging unit receives a 32-bit linear address from the segmentation unit.

• The upper 20 bits of the linear address has compared with all 32-entries in the translation look-aside buffer (TLB) to check if it matches with any of the entries.

• If it matches, the 32-bit physical address has calculated from matching TLB entry and placed on the address bus.

Address translation with segmentation and paging

Comparison of Segmentation in 80386 with 8086

Segmentation in 80386 Segmentation in 8086

1) It has six types of memory

segments, i.e. CS,ES,FS,GS and SS

1) It has four types of memory

segments i.e. CS,DS,ES and SS

2) Size of segments are variable from

1 byte to 4GB

2) Size of segments are variable from

1 byte to 64KB

3) Segment selectors, descriptors,

offset registers, GDT/LDT, page

directory and page tables are used to

generate physical address from logical

address

3) Segment registers and offset

registers are used to generate physical

address from logical address

4) Logical address is converted to

linear and then to physical address

4) Logical address is converted to

physical address

Comparison of Segmentation in 80386 with 8086

Segmentation in 80386 Segmentation in 8086

5) In this protection is provided to

memory segments by giving different

privilege levels from 0 to 3

5) In this protection is not provided to

memory segments

6) Size of physical address is 32-bit 6) Size of physical address is 20 bit

7) 80386 can access 4GB of memory 7) 8086 can access 1MB of memory