Tutorial 2 Test Techniques for RFIC and Embedded Passives · Test Techniques for RFIC and Embedded Passives ... B. Razavi, RF Microelectronics, ... – RF DIB consists of analog and

Tutorial 2 Test Techniques for RFIC and

Embedded Passives

Bruce C. Kim, Ph.D. The University of Alabama, Tuscaloosa, U.S.A.

13th Korea Test Conference, Seoul June 27, 2012 1

Outline

• Introduction to RF communication system • Test Technique Concepts

– RF measurements – SoC testing – RF passive circuit testing – Built-in Self Test (BIST)

• Summary

2

RF Testing

3

Expensive, labor intensive and require experience.

RF Basics

4

Communications System

5 J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, and SiP Devices, Boston: Artech House, 2007.

Components in RF Systems • Radio frequency

– Duplexer – Low noise amplifier (LNA) – Power amplifier (PA) – RF mixer – Local oscillator – Filter

• Intermediate frequency – Variable gain amplifier

(VGA) – Modulator – Demodulator

– Filter • Mixed-signal

– Digital to analog converter (DAC)

– Analog to digital converter (ADC)

• Digital – Digital signal processor

(DSP)

6 B. Razavi, RF Microelectronics, Upper Saddle River, New Jersey: Prentice Hall PTR, 1998.

RF Testing Classifications

7

RF Testing

RFIC Testing RF Load Board Testing

RF Embedded Passives Defect

Testing

Automatic Test Program Generation

Functional Testing

Opens, Shorts, Near-opens and Near-shorts

RF Power Sensor Testing (B. Kim, S.

Kannan)

Multi-tone Dither Testing (B. Kim,

S. Kannan)

RADPro (RF Analyzer and Diagnostic

Program Generation Tool

(B. Kim, S. Kannan)

Loop-back DfT for Transceiver Testing (A. Chatterjee, G.

Srinivasan)

Functional Testing Parametric Variations/Process-

related Defects

Test Level

Test Type

Testing and Diagnosis

Component Level Board Level System Level

Test Automation Performance Specifications

Goal System Performance

and IC Design Specifications

Loop-back Transceiver Testing using

embedded sensors (A. Chatterjee, S. Bhattacharya)

RF-BIST (J. Dabrowski)

B. Kim

Delayed RF test using spectral signal analysis

(S. Ozev)

Low Noise Amplifier (LNA)

• Amplifies received RF signal

• Typical characteristics: – Noise figure 2dB – IP3 – 10dBm – Gain 15dB – Input and output impedance 50Ω – Reverse isolation 20dB – Stability factor > 1

• Technologies: – Bipolar – CMOS


Power Amplifier (PA) • Feeds RF signal to antenna for transmission

• Typical characteristics: – Output power +20 to +30 dBm

– Efficiency 30% to 60%

– IMD – 30dBc

– Supply voltage 3.8 to 5.8 V

– Gain 20 to 30 dB

– Output harmonics – 50 to – 70 dBc

– Power control On-off or 1-dB steps

– Stability factor > 1

• Technologies: – GaAs

– SiGe 9 B. Razavi, RF Microelectronics, Upper Saddle River, New Jersey: Prentice Hall PTR, 1998.

Up/Down Frequency Converters (Mixers) • Translates frequency by adding or subtracting local oscillator (LO)

frequency

• Typical characteristics:

– Noise figure 12dB

– IP3 +5dBm

– Gain 10dB

– Input impedance 50Ω

– Port to port isolation 10-20dB

• Technologies:

– Bipolar

– MOS


Types of Mixers

11

Passive Mixer

Active Mixer

J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, and SiP Devices, Boston: Artech House, 2007.

Phase Splitters • Splits input signal into two same frequency outputs that differ in

phase by 90 degrees. • Used for image rejection.

12 J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, and SiP Devices, Boston: Artech House, 2007.

System-on-Chip (SoC)

• All components of a system are implemented on the same VLSI chip.

• Requires same technology (usually CMOS) used for all components.

• Component not implemented on present-day SoC: – Antenna

13

System-in-Package (SiP) • Several chips or SOC are included in a package. • Routing within SIP may be provided via a semiconductor

substrate. • RF communications system may contain:

– SiP containing SoC consisting of • CMOS digital and mixed-signal components (DSP, ADC,

DAC) • CMOS LNA and mixers • CMOS DDS • Filters

– Power amplifier (PA) – Antenna

14

Testing Concepts

15

Test Concepts

• Definition: Having designed and fabricated a device, testing must determine whether or not the device is free from any manufacturing defect.

• Testing is distinctly different from verification, which checks the correctness of the design.

• Forms of testing: – Production testing – Characterization testing

16

Production Testing

• Applied to every manufactured device • Major considerations

– Reduce cost; minimize test time per device. – Maximize quality; reduce defect level (DL),

defined as fraction of bad devices passing test.

– Time-to-market

17

Production Testing Equipment

• Performed using Automatic Test Equipment. • Has built-in instrumentation and programming

capability to test ICs.

18

Production Test Methodology

19 D. Lupea, et al., “RF-BIST: Loopback Spectral Signature Analysis,” Proc. Design, Automation and Test in Europe Conf., 2003.

ATE Features • Binning: Tested DUTs are grouped as

– Passing the entire test – Failing any of the tests – Failing because of dc test – Failing because of RF Test – Failing speed (maximum clock frequency) test

• Multisite testing: Testing of several DUTs is parallelized to reduce the test cost.

• Test time for a typical device: 1 – 2 seconds. • Testing cost of a device: 3 – 5 cents.

20

Characterization Testing • Performed at the beginning of production phase. • Objective: To verify the design, manufacturability,

and test program. • Method:

– Few devices tested very thoroughly – Failures are often diagnosed – Tests are more elaborate than the production tests – Test time (and testing cost) not a consideration – Test program is verified and corrected in necessary – ATE system and additional laboratory setup may be

used

21

RF Testing

• Basic Specifications – Scattering parameters (S-parameters) – Frequency and gain measurements – Power measurements – Power efficiency measurements – Linearity – Noise Figure

22

S-Parameter Measurements • An RF function is a two-port device with

– Characteristic impedance (Z0): • Z0 = 50Ω for wireless communications devices • Z0 = 75Ω for cable TV devices

– Gain and frequency characteristics • S-Parameters of an RF device

– S11 : input return loss or input reflection coefficient – S22 : output return loss or output reflection coefficient – S21 : gain or forward transmission coefficient – S12 : isolation or reverse transmission coefficient

• S-Parameters are complex numbers and can be expressed in decibels as 20 × log | Sij |

23

S-Parameter of RF Device

24

• S11 measures the input match and S22 determines the output match.

J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, and SiP Devices, Boston: Artech House, 2007.

Power Measurements • Receiver

– Minimum detectable RF power – Maximum allowed input power – Power levels of interfering tones

• Transmitter – Maximum RF power output – Changes in RF power when automatic gain control is

used – RF power distribution over a frequency band – Power-added efficiency (PAE)

• Power unit: dBm, relative to 1mW – Power in dBm = 10 × log (power in watts/0.001 watts)

25

Power Spectrum Measurements

• Spur measurements • Harmonic measurements • Adjacent channel interference

26

Spur Measurements • “Spur” is a spurious or unintended frequency in the output of an RF device. • Example: leakage of reference frequency used in the phase detector of

PLL. • A spur can violate the channel interference standard of a communication

system. • Complete power spectrum measured in characterizing phase to determine

which interfering frequencies should be checked during production testing.

27 D. Lupea, et al., “RF-BIST: Loopback Spectral Signature Analysis,” Proc. Design, Automation and Test in Europe Conf., 2003.

Harmonic Measurements

• Multiples of the carrier frequency are called harmonics.

• Harmonics are generated due to nonlinearity in semiconductor devices and clipping (saturation) in amplifiers.

• Harmonics may interfere with other signals and must be measured to verify that a manufactured device meets the specification.

28

Adjacent Channel Power Ratio

• Ratio of average power in the adjacent frequency channel to the average power in the transmitted frequency channel.

• Also known as adjacent channel leakage ratio (ACLR).

• A measure of transmitter performance.

29

AGC Characteristics to be Verified

• Gain errors and missing levels • Overshoots and undershoots – settling

time • Finite (non-zero) transition times • Varying gain steps – nonlinearity; DNL

(differential nonlinearity) and INL (integral nonlinearity) similar to ADC and DAC

30

RF BIST

31

Advantages of BIST

• Reduce complexity of Testing • Good for production, circuit

characterization and on-chip compensation

• Measurements with hardware implementation

32

Built-in Self Test

• Develop Built-In Self-Test (BIST) approach using direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems

• Provides BIST-based measurement of – Amplifier linearity (IIP3) – Gain and frequency response

• Implemented in hardware – IIP3, gain, and freq. response measured

33

SoC BIST for Transceiver

34

Reference - J. Dabrowski, “BiST Model for IC RF-Transceiver Front-End,” Proc. 18th IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, 2003.

SoC Transceiver BIST • Test implemented at baseband. • Loopback between A/D and D/A converters. • DSP implemented with digital BIST. • Test amplifier (TA) implemented on chip; is disabled during

normal operation. • A test procedure:

– Test DSP using digital BIST. – Apply RF BIST:

• Pseudorandom bit sequence generated by DSP • Up converted by transmitter chain and applied to receiver through TA • Down converted signal compared to input bit sequence by DSP to • analyze bit error rate (BER) • BER correlated to relevant characteristics of SOC components

• Advantage: Low tester cost. Disadvantage: Poor diagnosis.

35

RF BIST for LNA

36

B. Kim, J. Ryu, I. Sylla, “Programmable RF BIST Technique for Low Noise Amplifiers,” Microelectronics Journal: Circuits and Systems, invited paper.

RF BIST Gain Results

37

Programmable RF BIST

38

Used for GSM, Bluetooth, IEEE802.11g

LNA

S1

S2

V T 1

V T2

v in R s =50 Ω

Z L =50 Ω

S3

LNA Under Test

v L

v T

External Board

BIST

v L 1

A/D D SP

D N

PC

CMB

B. Kim, J. Ryu, I. Sylla, “Programmable RF BIST Technique for Low Noise Amplifiers,” Microelectronics Journal: Circuits and Systems, invited paper.

BIST Architecture • BIST-based IP3 measurement

– Reduce circuit by repeating test sequence • BIST-based Gain & Frequency Responses

39 F. Obaldia, et al., “On-Chip Test Mechanism for Transceiver Power Amplifier and Oscillator Frequency,” US Patent No. 20040148121A1, 2004.

Test Technique for RF Embedded Passives

40

RF Passive Circuit Testing

• RF load boards are complex – Multi – sites – Hundreds of passives, Relays, OPAMPS,

discrete transistors, SMA connectors, jumper wires

– Embedded RF circuits made of copper traces • RF Power Sensor Testing. • Multi-tone Dither Testing.

41

Device Interface Board (DIB)

• Provides test input stimulus to the Device Under Test (DUT).

• Two types of DIBs – RF DIB consists of analog and RF circuits

with multiple component types (embedded passives, capacitors, resistors, diodes, filters, baluns and ICs).

– High-Voltage DIB consists of analog circuits with high voltage rating and protection circuits.

42

Typical RF DIB

43

Automatic Test Program Generation Tool

• Automate the troubleshooting process. • Reducing labor cost and time to market

HV ICs.

44

RADPro

Test Translator Automatic Test Equipment

High-Voltage or RF or Mixed Signal DIB

RADPro: RF Analyzer and Diagnostic Program

• Inputs are netlist and Bill of Materials. • Uses unique RF circuit schematic

information and tester resources. • SPICE and ADS simulations are run for

testable circuits. • Output is a pseudocode consisting of test

instructions.

45

Software Architecture Netlist, Bill of

Materials (BOM),

Package File

PARSER

Components Model Library

Pin Map File and Resource

Constraints

Output Pseudocode

ETS Channel

Type Generation

Module

Build Circuit Module

Divide Board

Module

Relay Path

Module

Test Generation

Module

ADS and SPICE

Simulation

Library of

Passive RF Components

Fault Inducer

46

Divide Board Module • DIB is divided into testable sub-circuits. • Sub-circuits are based on availability of terminals for stimulating and

measuring test signals. • Use of partition algorithm.

47

Floating Ground Test Capability

48

100 Ohms 4

8 5

R 100

DUT Pin 1

DUT Pin 2

K_SP2BT_S1

K_SP2PH_S1

Force High

Sense High

Force Low

Sense Low

H6

G6

F6

E6

Pogo pins

8 5

4

High Side

Low Side

Pseudocode – ETS DIBs • Eagle Test System testers perform differential

testing. • Floating ground facilitates differential testing. • Performs high voltage testing.

49

*****POWER TO GROUND ONLY TEST***** CONDITION(VERIFY COMPONENT = JP19-1_2) FCMV(forced current = 1e-4 A, force high pin = CH-J1-I16, sense high pin = CH-J1-H9, type = force high) FCMV(forced current = 1e-4 A, force low pin = LowPin_Num3, sense low pin = LowPin_Ref3, type = force low) COMPARE_LIMITS(lower limit = 0.06 V, upper limit = 1.99 V, nominal value = 0.075 V, tested pwr node = +3P3V_MB)

Test Generation Module

50

Bill of Materials

Divide Board Module

Analog-Digital Circuits

RF Testable sub-circuits

ADS Model Files

Generation of AEL Command Netlist

Batch Simulation File Generation

ADS /SPICE Simulation Module

SPICE Netlist

Generation

ADS/SPICE Simulation Module • Testable circuits under fault free and fault

induced conditions. • SPICE for analog circuits.

– Force Voltage Measure Current (FVMC). – Force Current Measure Voltage (FCMV). – Force Current Measure Voltage with Delay Time

(FCMVDT). • ADS for RF circuits.

– Force Power Measure Voltage (FPMV). – Multi-tone Dither Testing.

51

Fault Modeling

• Built model libraries in ADS and SPICE for testable circuits.

• Fault models built for discrete passive components.

• Opens and short fault model developed for embedded passive RF components.

52

Balun Fault Model – Case Study

53

Position 1

Position 2

Look-up Table • Store results from simulation of fault free and fault

induced testable circuits • Match with ATE measurement results to diagnose the RF

DIBs.

54

Name Power Gain (dB)

Fault Free -40

Open at Position 1 -45

Open at Position 2 -52

Short at Position 1 -54

Short at Position 2 -56

RF Circuit Diagnosis

55

Testable Circuits from Divide Board Module

Fault Model

Fault Inducer

RF Power Sensor

Fault Dictionary

Multi-tone Dither Test

RF Power Sensor Testing • Identify process related defects for embedded RF circuits. • Power loss is measured across the RF path. • Process related defects result in power degradation at DUT terminal.

56

DUT Socket

RF Trace

Power Detector Chip

component

Load Board

SMA

Reference – RADPro: Automatic RF Analyzer and Diagnostic Program Generation Tool, S. Kannan, B. Kim, G. Srinivasan, F. Taenzler, R. Antley, C. Force, and F. Mohammed

Test Setup for Power Sensor

57

DIB with RF Power Sensor


Circuit Under Test

58

Printed LQ Balun

70.7 Ohm Trace

70.7 Ohm Trace

GND

J20

Test Signal Input

50 Ohm Trace

L2

L1

PS 1

PS 2

R159

49.9 Ω 1 pF

C340

C328

15 pF

C332

C333

C34415 pF

15 pF

15 pF

C322

100 pF

L17 22nH

L18 22nH


Experimental Results

59

1.5 GHz 2.0 GHz 2.5 GHz

Type of Fault Power

Sensor 1

Power

Sensor 2

Power

Sensor 1

Power

Sensor 2

Power

Sensor 1

Power

Sensor 2

Fault Free 1.41 0.937 1.24 1.146 1.05 1.04

Open common point(C340) 1.478 0.937 1.24 1.105 1.047 1.042

Open L2 side of Balun 0.598 1.143 0.71 1.2 0.405 0.95

Open LC filter one side (L17 and

C327)

1.41 0.924 1.238 1.15 1.048 1.042

Shorted outputs (70 Ohm Trace) 1.037 0.984 0.808 0.73 0.183 0.2

Open Capacitor (C344) 0.186 0.204 0.183 0.2 0.183 0.199

Shorted L1 side of Balun 1.436 0.841 1.227 1.5 0.999 1.051

Shorted L1 and L2 side Balun 1.178 1.155 0.741 0.652 0.306 0.413

Experimental Validation

60 Reference – RADPro: Automatic RF Analyzer and Diagnostic Program Generation Tool, S. Kannan, B. Kim, G. Srinivasan, F. Taenzler, R. Antley, C. Force, and F. Mohammed

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Diff

eren

tial V

olta

ge, V

Power Sensor Results

2.5 GHz PS1

2.5 GHz PS2

Open L2 side of Balun

Shorted outputs (70 Ohm Trace)

Shorted L1 side of Balun

Shorted L1 and L2 side Balun

Multi-tone Dither Test

• Modulation of RF source signal with multi-tone signal to generate the test signal.

• Gaussian Noise is added to the multi-tone signal.

61

RF Carrier Signal

Multitone Signal with

Noise (AWG)

RF Circuit

Modulation


Test Stimulus – Frequency Domain

62 Reference – RADPro: Automatic RF Analyzer and Diagnostic Program Generation Tool, S. Kannan, B. Kim, G. Srinivasan, F. Taenzler, R. Antley, C. Force, and F. Mohammed

Multi-tone Signal Measurement • Mathematical representation of multi-tone

signal.

• Real valued multi-tone signal is derived from

• Peak-to-average ratio of complex multi-tone signal

63

∑−

=

∆=1

0)(

N

n

tjnnemtm ω

)arg)cos(()(1

0no

N

nn mtnmtm +∆+=∑

−

=

ωω

∫−∞→= τ

τττdttmtmtdBRAP )(2

21lim)(max)(..

Circuit Under Test

• 50 Ω trace at input and output ports

64

50 Ohm Trace 50 Ohm Trace

Port 1

C1

1 pF

Term 1 50 Ω R1 R2 50 Ω 50 Ω

Port 2


Output Power Spectrum

65

0.0 0.5 1.0 1.5 2.0

-300-280-260-240-220-200-180-160-140-120-100-80-60-40-20

Pow

er, d

B

Frequency, GHz

Fault Free Open Defect Short Defect


Simulation Results

66

# of Tones 1 GHz 5 GHz 500 MHz 100 MHz 1 MHz

10 0.6473 1.3068 1.6185 0.7811 0.6142

20 0.6473 1.1464 1.6185 0.7811 0.6727

50 0.1877 0.8123 0.9228 0.396 0.856

100 2.3224 2.5116 0.6735 1.502 1.7382

150 3.19 3.19 3.0572 2.7615 2.6308

200 3.5292 3.5292 3.1057 3.621 2.7931

256 3.6383 3.8473 4.141 4.0462 3.504

• 50 Ω trace at input and output ports • Differential PAR between defect free and open defect measured for varying test

frequencies and number of tones

Hardware Validation – Dither Testing

• Test sample – 20 cm long resistive trace • Compare results with RF power sensor testing. • Input and output short faults induced.

67

long through line input short output short0

1

2

3

4

5

6

7

8P.

A.R,

dB


Opens Test • 1 cm long interconnect

68

0 50 100 150 200 2500.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Diff

eren

tial P

.A.R

, dB

Number of Tones

5 GHz 1 GHz 500 MHz 100 MHz 1 MHz

Reference – Embedded RF Circuit Diagnostic Technique with Multi-Tone Dither, S. Kannan, B. Kim, G. Srinivasan, F. Taenzler, R. Antley, C. Force.

Fault Coverage

69

0

50

100

150

200

250

0 5 10 15 20 25

Sensitivity of Fault Detection %

Num

ber o

f Ton

es

10% Open - Process Defect 20% Open - Process Defect 50% Open - Process Defect 90% Open - Process Defect

Reference – Embedded RF Circuit Diagnostic Technique with Multi-Tone Dither, S. Kannan, B. Kim, G. Srinivasan, F. Taenzler, R. Antley, C. Force.

Summary • Discussed basics of RF communication

system, components and technologies involved.

• Introduced RF test concepts such as RF measurements, and SoC testing.

• RF passive circuit testing using two novel test techniques such as RF power sensor technique and multi-tone dither testing

• BIST for RF SoCs, basic architecture and advantages.

70

Documents

Tutorial 2 Test Techniques for RFIC and Embedded Passives · Test Techniques for RFIC and Embedded Passives ... B. Razavi, RF Microelectronics, ... – RF DIB consists of analog and