TPC / PHOS / HLTReadout Electronics overview

Annual Evaluation Meeting for CERN-related Research in Norway10-11 November, 2004University of Oslo

Kjetil UllalandKjetil Ullaland

TPC & PHOS RCU + HLTReadout Electronics and Firmware Team

Ruprecht-Karls Universität Heidelberg, Germany

• V. Lindenstruth• D. Gottschalk• M. Stockmaier• V. Kiworra• T. Alt• T. Krawutschke

ZTT Worms, Germany• S. Bablock• C. KoflerCERN• L. Musa• R. Campagnolo• C. González Gutiérrez• B. Leitao Mota

University of Bergen• D.Röhrich• K.Ullaland• B. Pommersche• J. Alme (new phD-stipend, 2004)• M. Richter (phD-stipend, 2004)• T. Alt (Marie Currie stipend, 2003-4)• G. Grastveit (MsC, 2003)• K. Aurbakken (MsC-student)• O. Torheim (MSc-student)University of Oslo• B. Skaali• S. Solli (MSc-student)• P. T. Hille (MSc-student)Bergen University College• H. Helstrup• J. Lien (handed in phD thesis, 2004)• K. Røed (MSc 2004, phD-stipend, 2004)• L. E. Danielsen (BSc, 2003)• M. S. Myhre (BSc, 2003)

RCU design, prototyping and test

results (TPC & PHOS)

Radiation tolerance for electronics

HLT overview

Phos test beam results

Config FPGASIU

MezzanineBoard

FEB A FEB BPower

Triggers&

Clocks

DCSMezzanine

Board

DAQSystem

Detector ControlSystem

HLTSystem

Readout Control Unit

TriggerSystem

RCU – FEC Assembly

510 cm

EE

114

556 cm

The ALICE Time Projection Chamber

570132 pads x 1000 samples = 712 Mbytes / event– 2 scenarios:

• Pb – Pb (@ 200 Hz) 142.5 Gbytes / s• p – p (@ 1 KHz) 712 Gbytes / s

– Data compression (zero suppression) in FEE

RCU

Ethernet( 1 MB/s )

Detector Data Link( 200 MB / s )

COUNTING ROOM

ALTRO bus( 200 MB / s )

LocalSlow- Control(I2C-serial link)

ON DETECTORFEC128 ch

1

13

2

14

12

25

DCS int.(Ethernet)

SIU int.(DDL-SIU)

Trigger int.(TTC-RX)

FEC128 ch

FEC128 ch

FEC128 ch

FEC128 ch

FEC128 ch

PASA – ADC – DIG.

DETECTOR

TTC optical Link(Clock, L1 and L2 )

Overall TPC: 4356 Front End Card 216 Readout Control Unit

ALTROBus

Interface

Slow Control

Interface

Dataassembler

Branch A

Branch BRORC(PCI)

DCS

TTC

ALICE Photon Spectrometer (PHOS)

5x3584 XTALs5x112 Front End Cards5x8 Readout Control Units

RCU

Ethernet( 1 MB/s )

Detector Data Link( 200 MB / s )

COUNTING ROOM

ALTRO bus( 200 MB / s )

LocalSlow- Control(I2C-serial link)

ON DETECTORFEC32 ch

0

14

1

15

14

28

DCS int.(Ethernet)

SIU int.(DDL-SIU)

Trigger int.(TTC-RX)

FEC32 ch

FEC32 ch

FEC32 ch

PASA – ADC – DIG.

DETECTOR

TTC optical Link(Clock, L1 and L2 )

Overall PHOS:5x3584 XTALs 5x112 Front End Cards 5x8 Readout Control Units

ALTROBus

Interface

Slow Control

Interface

Dataassembler

Branch A

Branch BRORC(PCI)

DCS

TTC

Debugging Bus(USB-serial link)

Trigger card28 FECs

Trigger card28 FECs

Local Pattern Recognition

High Level Trigger

✔ Commercial off-the-shelf PCs●~300 PCs equipped with FPGA Co-processor cards with Firmware Algorithms●~300-500 compute nodes

✔Fault-tolerant cluster management✔Publisher-Subscriber Interface

HLT data input / output

HLT FEP Architecture

DetectorData Link

Datapointer

List

Pus

h re

adou

t P

oint

ers

FPGAPCI 66/64

PCI

Hostmemory

PCIHostbridge

smallDerandom.Evt. Buffer

CP

U

iCache

dCache

CP

U

iCache

dCache

CP

U

iCache

dCache

CP

U

iCache

dCache

Network Interface

200

MB

/s m

ax. p

er d

esig

n≈

90 M

B/s

typi

cal

RCU Motherboard - Bottom viewALTERA

APEX20KEGTLTransceivers

Backplane readoutconnectors

RCU Motherboard - Top view

DCS interfaceDIMM connector

Power regulators

SIUPMC connectors

TEST and DEBUG connectors

TTC and DCS mezzanine card• Tasks:

– Configuration

– RCU

– FEC

– monitoring / controlling the FEE

– configuration/readout of the TTCrx

– distributing the L1 and L2

• ALTERA Excalibur:– FPGA EP20K100

– ARM922T hardwired processor running Linux

TTCrx chip

(custom)

Ethernet bridge

DDL - SIU mezzanine card