Three-Dimensional Fin-StructuredSemiconducting Carbon Nanotube NetworkTransistorDongil Lee,†,⊥ Byung-Hyun Lee,†,⊥ Jinsu Yoon,‡ Dae-Chul Ahn,† Jun-Young Park,† Jae Hur,†

Myung-Su Kim,† Seung-Bae Jeon,† Min-Ho Kang,§ Kwanghee Kim,§ Meehyun Lim,∥ Sung-Jin Choi,*,‡

and Yang-Kyu Choi*,†

†School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu,Daejeon 34141, Korea‡School of Electrical Engineering, Kookmin University, 77 Jeongneung-ro, Seongbuk-gu, Seoul 02707, Korea§Department of Nano-process, National Nanofab Center (NNFC), Daejeon 34141, Korea∥Test and Package Technology Group, Mechatronics R&D Center, Samsung Electronics, 1-1 Samsungjeonja-ro, Hwaseong-si,Gyeonggi-do 18448, Korea

*S Supporting Information

ABSTRACT: Three-dimensional (3-D) fin-structured car-bon nanotube field-effect transistors (CNT-FETs) withpurified 99.9% semiconducting CNTs were demonstratedon a large scale 8 in. silicon wafer. The fabricated 3-D CNT-FETs take advantage of the 3-D geometry and exhibitenhanced electrostatic gate controllability and superiorcharge transport. A trigated structure surrounding therandomly networked single-walled CNT channel wasformed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm.Additionally, highly sensitive controllability of the threshold voltage (VTH) was achieved using a thin back gate oxide in thesame silicon frame to control power consumption and enhance performance. Our results are expected to broaden thedesign margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentiallyprovide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerginglow-dimensional materials other than CNTs.

KEYWORDS: carbon nanotubes, 3-D structure, fin field-effect transistor (FinFET), wafer-scale, high packing density

Over the past several decades, Moore’s law has driventhe performance enhancement of the integratedcircuit and has guided the scaling of silicon transistors.

However, because of the aggressive downsizing of metal-oxide-semiconductor field-effect transistors (MOSFETs), furtherextending Moore’s law encounters critical problems, such asphysical limitations and short-channel effects (SCEs), affectingthe fabrication process and performance.1,2 To overcome thesechallenges, transistors based on novel materials haveemerged.3−5 Thus, various low-dimensional materials, such ascarbon nanotubes (CNTs), graphene, and other two-dimen-sional (2-D) materials, have recently become highly attractiveas “beyond silicon” materials.6−11 Among these, single-walledCNTs have been reported to be attractive for furtherdownscaling. CNT technology has been predicted to exceedthe performance requirements suggested by the InternationalTechnology Roadmap for Semiconductors by a factor of up to2−3 at the 11 nm node, in contrast to other emerging

materials.12−14 Therefore, the performance enhancement andenergy efficiency of CNT-based FETs (CNT-FETs) have beencarefully researched, and CNT-FETs have been identified assuitable for use in digital logic circuits.12,13,15−18 In particular,although the transfer process-induced defects in emergingmaterials, including 2-D materials, are problematic, CNTs areless sensitive to this issue. Therefore, CNT-FETs are moreappropriate for wafer-scale fabrication than other 2-Dmaterials.19

To date, notable approaches to enhance the performance ofCNT-FETs have been reported, including decreasing thechannel length to below 10 nm, using a gate-all-aroundstructure or achieving size-independent contact resistance,demonstrating that the potential of CNT-FETs exceeds that of

Received: August 12, 2016Accepted: November 10, 2016Published: November 10, 2016

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silicon.20−22 However, achieving higher-level purity andincreasing the packing density of semiconducting CNTs remainthe primary main challenges to improve these materials’practicality. To satisfy the demand for higher-purity semi-conducting CNTs, some groups have employed CNTs withpurities exceeding 99%.23−27 In accordance with suchapproaches, semiconducting enriched CNT solution-processeddevices with 99.9% purity were demonstrated in our previouswork, showing the feasibility using these materials to achievelow power consumption.28,29 However, regarding increasing thepacking density, the conventional limitcommonly consideredto be ∼125 CNTs/μmwas surpassed using varioustechniques, such as ion-exchange chemistry,30 solutionshearing,31 Langmuir−Blodgett,32 and Langmuir−Schaefertechniques.33 Although these techniques have produced CNTdensities of approximately 500 CNTs/μm under idealconditions, combining good scalability and facile processavailability with high density, which is required for the wafer-scale manufacturing of CNT-based nanoelectronics, remainschallenging. In particular, the structural engineering of CNTswith increased packing density is more challenging thanmaterial engineering to exploit a desired electrical property.33

In this regard, the structural innovation of a fin field-effecttransistor (FinFET), a type of three-dimensional (3-D) gatedvertical structure that represents an advancement beyond 2-Dgated planar silicon channel-based devices (MOSFETs) canserve as a guide for the structural engineering of CNT-FET-based devices.34 In the historical evolution of silicon channel-based MOSFETs, the 3-D gated structure was the driving forceunderlying the extension of Moore’s law, resulting in enhancedperformance, improved productivity, reduced fabrication costs,and decreased power consumption.35,36 Considering thesignificance of CNTs with higher packing densities for thefeasibility of high-performance CNT-FETs, using this 3-Dgated structure can be an effective approach to advance beyondMoore’s law, similar to the Si-FinFET with the 3-D gatedstructure. Furthermore, to realize a CNT-FET with improvedpurity and density, the process compatibility with comple-mentary MOS (CMOS) fabrication would lead to synergy viathe fusion of the CNT material and the silicon process-basedoptimal structure.37,38

In this work, 3-D fin-structured CNT-FETs with purified99.9% semiconducting CNTs fabricated based on thecombination of a silicon-CMOS compatible process and atypical solution process are demonstrated on an 8 in. Si wafer.The fabricated CNT-FETs are based on a trigated structuresurrounding the CNT channel formed on a fin-like 3-D siliconframe employing three channel faces, thereby improving theelectrical performance because of the enhanced electrostaticgate controllability and superior charge transport. Moreover,given the fin-structured 3-D silicon frame, the effective packingdensity of the randomly networked CNTs can be increased tonearly 600 CNTs/μm in the same footprint layout area. Thesefeatures prove that silicon process-based structural optimizationis effective for achieving densely packed CNT channels on awafer-scale substrate. The highly reproducible silicon processalso permitted the fabrication of 3-D CNT-FETs with variousdimensions. For example, the channel length (LCH) and finwidth (WFIN) can be varied easily by photolithography, and thefin height (HFIN) is controlled by the etching time of the 3-Dsilicon frame. A 2-D planar-type CNT-FET was also fabricatedas a control device. Compared to the previous report, whichwas based solely on simulated data of the 3-D CNT-FET, our

fabricated 3-D CNT-FET exhibited acceptable electricalperformances: on/off current ratio (ION/IOFF) above 105, asteep subthreshold swing (SS) of 85 mV/dec, and a currentdensity of 3.9 μA/μm.37 Additionally, highly sensitivecontrollability of the threshold voltage (VTH) was achieved byincorporating a thin back gate oxide (BGO) in the samestructure. The dummy fin-structured 3-D silicon frame not onlyprovides mechanical support for the CNTs but also plays therole of the back gate. This tunable VTH, even in the 3-D CNT-FETs, is highly advantageous for customization by end-users viathe enhancement and modulation of the performance. Thus,our work provides a pathway toward the feasible nano-fabrication-based mass production of emerging materialsother than silicon.

RESULTS AND DISCUSSIONThe overall schematic of the 3-D fin-structured CNT-FET isshown in Figure 1a, and the cross-sectional high-resolution

transmission electron microscopy (TEM) image is shown inFigure 1b. First, the Si mesa pattern was etched to fabricate aprotruded fin-like 3-D silicon frame. Then, thermal silicondioxide (SiO2), also known as the isolation oxide, was grown toensure electrical isolation between the CNTs and the 3-Dsilicon frame. The isolation oxide was then functionalized withan amine-terminated group to support the CNTs, even on thesidewall. Subsequently, to fully cover the wafer with CNTs, itwas immersed in a preseparated 99.9% semiconductingenriched CNT solution (provided by NanoIntegris, Inc.) anddried at 60 °C for 7 h. The TEM image shown in Figure 1cshows that the diameter of the CNTs was <2 nm. An opticalimage of the fully processed 8 in. wafer is presented in Figure1d. As shown in Figure 1e, scanning electron microscopy(SEM) images show that CNT networks uniformly cover three

Figure 1. Details of the 3-D CNT-FET, including the formation of afabricated device. (a) Schematic illustration of the 3-D CNT-FETson a bulk silicon substrate. The entire process is fully compatiblewith the silicon-based CMOS process. (b) Cross-sectional TEMimage along the A−A′ direction. The 3-D CNT fin structureconsists of CNTs and dielectric layers surrounding the silicon andsilicon oxide fin structure. (c) TEM image of the CNT on thechannel area with a diameter of <2 nm. (d) Optical image of thefully fabricated 8 in. wafer. (e) SEM images of CNT networksuniformly deposited on three faces: the top and sidewalls of the 3-D silicon frame (top). Close-up view of CNTs with high packingdensity and a small fin width (<50 nm) (middle). 25° tilted SEMimage of fully fabricated device (bottom).

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faces: the top and sidewalls of the 3-D silicon frame.Importantly, using the Monte Carlo simulation method, theeffective packing density of randomly networked CNTs wasestimated to be approximately 600 CNTs/μm on these threefaces at a fin height (HFIN) of 300 nm. The estimated effectivepacking density was normalized by the footprint fin width(WFIN) indicated in Figure 1a, i.e., the number of CNTs perWFIN (Supporting Information, Figure S1). In contrast, thepacking density of the control group, i.e., the 2-D planar-FET,was extracted from the SEM and atomic force microscopy(AFM) data (Supporting Information, Figure S2) and wasapproximately 50−55 CNTs/μm. The remarkable increase inthe effective packing density of CNTs in the 3-D CNT-FEToriginated from its inherently folded 3-D channel without anysacrifice of the channel area. Therefore, increasing HFINimproves the packing density of CNTs. After forming theCNT network channel, source−drain electrodes consisting ofthree sequentially deposited layersTi (1 nm)/Pd (100 nm)/Au (100 nm)were patterned using a typical thermalevaporation and lift-off process. Because the CNTs also existedon the background bottom surface, an additional etching stepusing O2 plasma was utilized to remove the possible leakagepath. Next, a 10 nm-thick Al2O3 gate dielectric layer wasuniformly deposited on the silicon frame by atomic layerdeposition (ALD), as verified by energy-dispersive X-rayspectroscopy (EDS) mapping (Supporting Information, FigureS3). Finally, the gate electrode was fabricated by the sequentialdeposition of 100 nm-thick Pd and Au layers. The fabricationprocesses for the 3-D fin structured CNT-FETs are alsodescribed in detail in the Methods section and SupportingInformation, Figure S4.High-resolution TEM images of the fabricated 3-D fin

structured CNT-FETs with various HFIN values (100, 200, and300 nm) are shown in Figure 2a, representing the gate region ofthe A−A′ direction in the schematic of Figure 1a. Three

different cross-sectional geometric shapes of the 3-D CNT-FETs with the same LCH gate oxide thickness and WFIN wereprepared to investigate the effect of HFIN on the electricalcharacteristics. The maximum HFIN in our work was limited to300 nm to avoid difficulties in the subsequent processing. Thetransfer curves, i.e., drain current−gate voltage (ID−VG) curves,of the 3-D fin-structured CNT-FETs with different HFIN at adrain voltage (VD) of −0.5 V are compared in Figures 2b. A 2-D planar-type CNT-FET (i.e., HFIN = 0) was also characterizedas a control device. Interestingly, as HFIN increased from 0 nm(planar) to 300 nm, the average normalized ION density at VG =−2.5 V increased from 0.35 to 3.95 μA/μm, because of theincreased effective packing density of CNTs. Althoughnormalization of ION by the perimeter of the 3-D siliconframe, i.e.,WFIN + 2HFIN, is the most common approach, it doesnot provide a practically useful prediction. In our work,therefore, ION was normalized by only considering WFIN as−ION/WFIN. Furthermore, the highest ION/IOFF and lowest SSvalues in the 3-D CNT-FETs with a HFIN of 100 nm were 105

and 85 mV/dec, respectively.Statistical data about the SS and normalized ION values for

different HFIN in 3-D CNT-FETs are summarized from the 10total samples measured under each condition in Figure 2c.Compared to the device with HFIN = 0 nm (planar), we foundthat the 3-D CNT-FETs effectively suppress the SCEs andenhance the ION. Specifically, the SS of the 3-D CNT-FET witha HFIN of 100 nm decreased by a factor of 4 relative to that ofthe planar devices; this is the one of the lowest values everreported for CNT-FETs at a channel length (LCH) on this scale.The improved SS is attributed to the better electrostatics in thetrigate structure, which is a relatively ideal geometry forelectrostatics and provides sufficiently strong coupling of thegate bias to the CNT channel (Supporting Information, FigureS5). However, the SS worsens slightly for higher HFIN devicesbecause of the increasing number of CNT-CNT junctions in

Figure 2. Fabricated 3-D CNT-FETs showing ideal fin structure geometry and electric performance with different HFIN values. (a) Cross-sectional TEM images showing the well-defined metal gate (Pd/Au) wrapping the fin with various HFIN values (100, 200, and 300 nm). (b)Transfer (ID − VG) characteristics (log scale) of 3-D CNT-FETs with different HFIN values, LCH = 200 nm and WFIN = 50 nm at a drain voltage(VD) of −0.5 V. (c) Statistical data (ION/W, SS) from the 10 samples tested under each condition based on the geometric dependence of HFIN.(d) Output (ID − VD) characteristics of the 3-D CNT-FETs for different gate voltages ranging from −3 to 0 V in 0.5 V steps.

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the channel.33,39 The most significant feature of Figure 2c isthat the on-state current density of the 3-D CNT-FETsincreased as the HFIN increased without area penalties. For thedevice with HFIN of 300 nm, the on-state current density wasapproximately 1 order of magnitude larger than that of theplanar CNT-FET because of the aforementioned increasedeffective packing density of CNTs. Given the enlarged effectivechannel width (WFIN + 2HFIN), the absolute number of CNTsincreased, enhancing the resulting current drivability, even forthe same footprint layout area. This is the most significantfeature of our work. Figure 2d also presents the outputcharacteristics, i.e., drain current−drain voltage, ID−VD, of a 3-D CNT-FET with LCH = 200 nm, WFIN = 50 nm, and HFIN =300 nm at various VG values ranging from −3 to 0 V. Non-ohmic behavior was observed in the low-field region because ofthe presence of the underlap region in our 3-D CNT-FETsbetween the gate and source/drain electrodes (SupportingInformation, Figure S6).40 To improve the ohmic contactproperties, systematic process optimization should be per-formed, including the utilization of the self-align process andcontinued observation of complete contact processes.20

We also comprehensively investigated the effect of WFIN onthe electrical characteristics of the 3-D fin-structured CNT-FETs, as shown in Figure 3. Figure 3a shows the measured

representative transfer curves of the fabricated 3-D CNT-FETswith the same LCH (200 nm) and HFIN (100 nm) and WFINvalues ranging from 50 to 300 nm at a drain voltage (VD) of−0.5 V. As WFIN increased, all transfer curves exhibitednarrower distributions at similar positions but only a milddegradation of SS. We also statistically compared the electricalcharacteristics of the 3-D CNT-FETs, such as the normalizedon-current density (−ION/W) and SS, for devices with different

WFIN values at VD = −0.5 V (Figure 3b). Whereas thenormalized on-current density was nearly unchanged, the SSimproved as WFIN decreased, even though the gate insulatorthickness is identical among the devices. This trend wasobserved because a narrower WFIN leads to more enhancedelectrostatic effects. To determine the exact origin of theimproved electrical characteristics for narrow WFIN values, theelectric field distribution in a 3-D CNT-FET was simulatedusing a 3-D numerical simulator (COMSOL) based on thefinite element method (FEM) (Figure 3c). All devicedimensions used in the simulation were obtained frommeasurements made using the actual TEM image (Figure2a); other important parameters were taken from previousstudies.41−44 The detailed simulation conditions and parame-ters are provided in the Supporting Information, Figure S5. Inthe simulation, a common gate voltage (VG) of −2 V wasapplied to the gate electrode of the 3-D CNT-FET withdifferent WFIN values (50, 150, and 300 nm), and the peakelectric field at the CNTs adhering to the 3-D frame wasextracted. Because of the screening effects arising from thethicker 3-D frame, devices with larger WFIN show weakerelectric fields than those with narrower WFIN. Therefore,decreasing the WFIN width can further increase the energyefficiency of circuit-level devices by improving the SS andsignificantly decreasing the area of the CNT-FETs.Finally, we examined whether the 3-D CNT-FETs can

operate properly with the back gate bias (VBG) (Figure 4). Inour structure, the back gate bias provided via the silicon finsurrounded by the BGO can modulate the VTH, therebyenabling the dynamic management of power and performance.

Figure 3. Determination of the effect of WFIN on the electricalperformances of the 3-D CNT-FETs. (a) ID−VG transfer curve ofthe 3-D CNT-FETs with various WFIN at LCH = 200 nm, HFIN = 100nm, and VD = −0.5 V. (b) Statistical data (ION/W, SS) about theWFIN dependence. Decreasing the WFIN significantly affects the SSbehavior. (c) Numerical simulated map of the electric fielddistribution around 3-D CNT-FETs depending on the WFIN,including zoomed-in electric fields of single CNTs with differentWFIN behaviors (right). (d) Plot of the calculated electric field atsingle CNTs as a function of the WFIN. Compared with the electricfield for a device with a narrower WFIN, those with larger WFINexhibit a lower electric field because of the screening effects of thebarrier arising from the thicker 3-D frame.

Figure 4. Dependence of the threshold voltage adjustment on the 3-D CNT-FETs on the BGO thickness. (a) Cross-sectional TEMimages showing well-defined BGO with a 10 and 50 nm SiO2 layers.(b) ID−VG transfer curve of the 3-D CNT-FETs with a 10 nm BGOlayer. Varying the back gate bias can dramatically impact the VTHadjustment. (c) Plots of back gate bias verves VTH for 10 and 50 nmthick BGO. The VTH of devices with thin BGO (10 nm) layers ismodulated by as much as 0.25 V by changing VBG by ±1 V.

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The cross-sectional TEM images of the fabricated 3-D CNT-FETs with different BGO thicknesses are shown in Figure 4a.Well-defined BGOs with thicknesses of 10 and 50 nm wereclearly observed. Figure 4b,c shows the transfer curves andVTH−VBG characteristics. For a thin BGO (10 nm), the VTH of a3-D CNT-FET can be modulated by as much as 0.25 V bychanging VBG by ±1 V, resulting in a body factor (γ) of 0.25.Here, we define the absolute value of the slope in Figure 4c asγ; that is, γ = |ΔVTH/ΔVBG|. Compared to a device with a thickBGO, a 294% improvement of γ was obtained. Therefore,relative to the work function engineering method and thecomplex chemical doping method, our 3-D CNT-FET structureprovides a simple and CMOS compatible method for VTHmodulation.45,46 As a result of adopting the device structures,our 3-D CNT-FETs based on high-density CNTs exhibitedsuperior performance, requiring lower operating voltage and asteeper SS than other FETs.13 Further enhancement of deviceperformance is expected by employment of techniques suitablefor parallel assembly of CNTs (such as ion-exchangechemistry,30 solution shearing,31 Langmuir−Blodgett,32 andLangmuir−Schaefer method,33 and Joule heating of removal ofm-SWNTs),47 using the method proposed here, with a highlypurified semiconducting CNT solution, thereby providing asuitable alternative to silicon-FETs.In summary, 3-D CNT-FETs on a large (8 in.) silicon wafer

are demonstrated. The fabricated 3-D CNT-FETs, which arebased on 99.9% purified semiconducting CNTs with highpacking density (approximately 600 CNTs/μm), showed highprocess uniformity and a high on/off ratio after large-scaleprocessing for circuit fabrication; such high packing density isdifficult to accomplish in conventional 2-D CNT-FETs. As aresult, the 3-D CNT-FETs showed a steep SS of 85 mV/dec,corresponding to outstanding switching capability, and anenhanced current drivability of 3.9 μA/μm, leading to fastspeed. In addition, easily controllable VTH was achieved viaback gate engineering, thereby enabling selective control tosuppress IOFF to enhance the power efficiency and ION andleading to high performance. Thus, this approach can broadenthe design margin for customized circuit architectures withCNT-FETs. This work demonstrates the feasibility of usingmass-producible CNT-FETs in practical applications and,simultaneously, the possibility of advancing beyond the silicontransistor-based Moore’s law. More specifically, this workrepresents a milestone in the pathway toward the utilization ofemerging low-dimensional materials as the most promisingcandidates for postsilicon transistors.

METHODSFabrication Process of 3-D CNT-FETs. The entire fabrication

process of the 3-D CNT-FETs is illustrated in Figure S2. A boron-doped bulk silicon (Bulk-Si) wafer (8 in.) was used as the substrate.The high-density plasma oxide, which serves as the hard mask (HM)to etch the Si, was deposited using plasma-enhanced chemical vapordeposition (PECVD). The 3-D fin structure was defined on the HMusing krypton fluoride laser-based photolithograph, followed by deepreactive ion etching, thereby creating the frame for the 3-D CNT FET.Silicon dioxide (SiO2) layers, with a thickness of 10 and 50 nm, werethermally grown on the fabricated Si frame to facilitate CNT adhesionand were then functionalized to form amine-terminated adhesionlayers (poly-L-lysine aqueous solution, 0.1% w/v in water; Sigma-Aldrich) and enhance the adhesion capability. Samples were immersedin highly purified 99.9% semiconducting CNT solution (0.01 mg/mL)(provided by NanoIntegris, Inc.) and dried at 60 °C for 7 h using aconventional solution process. To form the source and drain (S/D)

electrodes, a negative photoresist (PR)-based photolithographyprocess was performed using the mask used for the fin patterning.The stacksTi (1 nm)/Pd (100 nm)/Au (100 nm)were depositedusing thermal evaporation, and then, a lift-off process was performedto form the S/D electrodes. The CNTs excluding the channel regionwere removed by implementing proper patterning processes, includinga photolithography process using the same fin mask and a sequentialoxygen plasma etching process. An ALD-based Al2O3 layer (10 nm)was deposited as the gate dielectric, and then, metal layers equivalentto the formation of the S/D electrode were thermally evaporated toform the gate electrode. Finally, gate patterning was conducted via anegative PR-based photolithography process and a subsequent lift-offprocess.

Instrumentation. SEM (model S-4800) was used to analyze thecross-sectional images of the 3-D CNT-FET structure. AFM imageswere acquired with an AFM (model XE-100) in tapping mode. Toprepare the sample for TEM, a focused ion beam (FIB, model HeliosNano lab) process was conducted after passivation using a PECVD-based nitride layer and platinum to protect the fabricated samples fromphysical damage during the FIB process. The cross-sectional image ofthe fabricated 3-D CNT-FET was obtained using high-resolution TEM(model JEM-ARM200F). The component analyses and cleardefinitions of each layer in the 3-D CNT-FET were achieved withthe aid of EDS mapping (model Quantax 400). All electricalmeasurements were collected using a HP4156 semiconductorparameter at room temperature without any device encapsulation.

ASSOCIATED CONTENT

*S Supporting InformationThe Supporting Information is available free of charge on theACS Publications website at DOI: 10.1021/acsnano.6b05429.

Detailed information regarding the dependence of thenanotube density on the height was obtained usingMATLAB, SEM and AFM images of the depositedCNTs on a SiO2 surface, component analysis of thefabricated 3-D CNT-FET devices, the fabrication processof the 3-D CNT-FETs and top view SEM images of eachsteps; the electric field distribution profile of a 3-D CNT-FET was obtained using the COMSOL package viaFEM; and output characteristic under back-gate oper-ation in the 3-D CNT-FET were also measured (PDF)

AUTHOR INFORMATION

Corresponding Authors*E-mail: sjchoiee@kookmin.ac.kr*E-mail: ykchoi@ee.kaist.ac.kr.

Author Contributions⊥D. L and B.-H.L equally contributed to this work.

NotesThe authors declare no competing financial interest.

ACKNOWLEDGMENTS

This work was supported by the Center for Integrated SmartSensors funded by the Ministry of Science, ICT & FuturePlanning as Global Frontier Project (CISS-2011-0031848) andby the National Research Foundation of Korea under grants2 013R1A1A1057870 , 2 0 16R1A2B4011366 , a nd2016R1A5A1012966. This research was partially supportedby the Pioneer Research Center Program through the NationalResearch Foundation of Korea funded by the Ministry ofScience, ICT & Future Planning (grant 2012-0009600).

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