This material exempt per Department of Commerce license exception TSU

Reading Reports

Reports 2

Objectives

After completing this module, you will be able to:• Determine whether a design met your area goals• Determine whether a design met your performance goals

Reports 3

Outline

• Introduction

• Area Goals• Performance Goals• Summary

Reports 4

Introduction

• After you have implemented your design, how can you tell whether the implementation was successful?

• First and foremost, how do you define a successful design?• Answer: A successful design:

– Fits into the device– Achieves performance goals

Reports 5

Outline

• Introduction• Area Goals

• Performance Goals• Summary

Reports 6

Area Goals

• How do we know whether the design fits into the device?• How do we know whether there is enough room in the device for

more logic? If there is enough room, exactly how much space is available?

• If the design fits into the device, was it able to route completely?

Reports 7

Area Goals

• How do we know whether the design fits into the device?– Information can be found in the Design Summary, Map Report, or the Place

& Route Report

• How do we know whether there is enough room in the device for more logic? If there is enough room, exactly how much space is available?– Information can be found in the Design Summary, Map Report, or the Place

& Route Report

• If the design fits into the device, was it able to route completely?– Information can be found in the Place & Route Report

Reports 8

Determining Whether Area Goals Were Met

Reviewing the Map Report

• Map Report– <design>.mrp

Read the Map Report to See How Your Design Will Fit into the FPGA

Reviewing the Place & Route Report

<design>.par

Read the Place & Route Report: Errors, Warnings, Timing Summary

Reports 13

Outline

• Introduction• Area Goals• Performance Goals

• Summary

Reports 14

Determining Whether Performance Goals Were Met

Reports 15

The Post-Map Static Timing Report Indicates Reasonable Constraints

Reports 16

What is Reasonable?

• Use the 60/40 rule:– If less than 60 percent of the timing budget is used for logic delays, the

Place & Route tools should be able to meet the constraint easily– Between 60 to 80 percent, the software run time will increase– Greater than 80 percent, the tools may have trouble meeting your goals

Reports 17

Evaluate and Handle Unreasonable Constraints

Slack: 0.828ns (requirement - (data path - clock path skew + uncertainty)) Source: pn_correlator_inst/pn_correlation_fsm_inst/pn_addr_cntr_1 (FF) Destination: pn_correlator_inst/pn_correlation_fsm_inst/pn_addr_cntr_9 (FF) Requirement: 3.000ns Data Path Delay: 2.172ns (Levels of Logic = 3) Clock Path Skew: 0.000ns Source Clock: clk_bufr_BUFGP rising at 0.000ns Destination Clock: clk_bufr_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Data Path: pn_correlator_inst/pn_correlation_fsm_inst/pn_addr_cntr_1 to pn_correlator_inst/pn_correlation_fsm_inst/pn_addr_cntr_9 Delay type Delay(ns) Logical Resource(s) ----------------- ----------- ------------------- Tcko 0.258 pn_correlator_inst/pn_correlation_fsm_inst/pn_addr_cntr_1 net (fanout=8) e 0.100 pn_correlator_inst/pn_correlation_fsm_inst/pn_addr_cntr<1> Tilo 0.146 pn_correlator_inst/pn_correlation_fsm_inst/_n002312 net (fanout=3) e 0.100 pn_correlator_inst/pn_correlation_fsm_inst/_n0023_map1085 Tif5x 0.428 pn_correlator_inst/pn_correlation_fsm_inst/_n0027_1_G pn_correlator_inst/pn_correlation_fsm_inst/_n0027_1 net (fanout=2) e 0.100 pn_correlator_inst/pn_correlation_fsm_inst/_n00271 Tilo 0.146 pn_correlator_inst/pn_correlation_fsm_inst/_n0005<9>76 net (fanout=1) e 0.100 pn_correlator_inst/pn_correlation_fsm_inst/_n0005<9>_map1059 Tsrck 0.794 pn_correlator_inst/pn_correlation_fsm_inst/pn_addr_cntr_9 --------------- ------------- --------------------------- Total 2.172ns (1.772ns logic, 0.400ns route) (81.6% logic, 18.4% route)

Use the Timing Analyzer to View Timing Reports

ConstraintHierarchy

CurrentConstraintView

Detailed constrainedPath

Reading Timing Reports

Reports 20

Were the Constraints Met?

Post-Place & Route Static Timing Report: Were Constraints Met?

<design>.twx

Reviewing the Post-Place & Route Static Timing Report

Reports 23

Pinout Information

• Where can I get pinout information to start the board layout?– Answer: Pad Report

Read the Pad Report to Get Pinout Information

• Plain text Pad Report– <design>_pad.txt

• Pad Report– <design>.pad,

<design>_pad.csv

Reports 25

Outline

• Introduction• Area Goals• Performance Goals• Summary

Reports 27

Review Questions

• How do you determine whether your timing constraints are reasonable? (Hint: which report do you review?)

• To estimate the amount of available resources you have left, do you need to fully implement your design? Why or why not?

Reports 28

Answers

• How do you determine whether your timing constraints are reasonable? (Hint: which report do you review?)– Use the Post-Map Static Timing Report– You must double-click the Generate Post-Map Static Timing process to

create this report (it is not created by default)– This process is underneath the Map process

• To estimate the amount of available resources you have left, do you need to fully implement your design? Why or why not?– No. You have to implement through the Translate and Map processes

because the Design Summary or the Map Report shows you the available resources

Reports 29

Summary

• A successful implementation means that your design meets your area and performance objectives

• The Map Report and Place & Route Report provide resource utilization and availability

• The Post-Map Static Timing Report gives you information to create reasonable timing constraints

• The Post-Place & Route Static Timing Report informs you whether or not your timing constraints were met

• The Design Summary screen provides quick access to many reports

Reports 30

Where Can I Learn More?

• Development System Reference Guide– www.xilinx.com Documentation Software Manuals