The Semiconductor Industry‟s Nanoelectronics Research Initiative:Motivation and Challenges

Dr. Jeff Welser

Director, SRC Nanoelectronics Research Initiative

IBM Almaden Research Center

April, 2009

2

Semiconductor Research Corporation: Collaboratively Sponsored University Research

The Semiconductor Industry Association (SIA) members have recognized that collaboration among industry, government and academia is the most efficient means of advancing university research capabilities

Strong university research is critical to maintain technology innovation

Research in new concepts, breakthrough ideas and solutions to problems for which no currently known solutions exist

Development of talent pool of scientists and engineers

Semiconductor Research Corporation (SRC) has been established to facilitate collaboratively sponsored university research

Manages full spectrum of research related to CMOS and beyond technology

Awarded the 2005 National Medal of Technology

“For building the world‟s largest and most successful universityresearch force to support the … semiconductor industry ...”

Focus Center

Research

Program

Breaking down

barriers to

extend CMOS to

its limits

Attracting and

educating the

next generation

of innovators and

technology

leaders

Global Research

Collaboration

Ensuring vitality

of current

industry

Nanoelectronics

Research

Initiative

Beyond CMOS –

identify next

information

element

Topical Research

Collaborations

Topic(s) chosen

by participants

TRC‟s

Semiconductor Research CorporationA Family of Distinct, Related Program Entities

3

4

Moore‟s LawL

og

of

the

Nu

mb

er

of

Co

mp

on

en

ts

Per

Inte

gra

ted

Fu

ncti

on

Year

Electronics, Volume 38, Number 8, April 19, 1965

5

Moore‟s Law: Transistors per chipBinary Information Throughput (BIT)

Why scaling? – To

increase the Binary

Information Throughput

(BIT)1.00E+16

1.00E+17

1.00E+18

1.00E+19

1.00E+20

1.00E+21

2000 2005 2010 2015 2020

Year

BIT

(b

its

/s/c

m2)

What is the ultimate number of

binary transitions per second in

a 1cm2 chip area?

nbit – the number of binary states

f – switching frequency

- a measure of

computational

capability on

device level

fnBIT bit

Motivation: density

speed

functionality

6

RESULTS:Higher Density:

Higher Speed:

Lower Power: 1

per circuit

Power Density: Constant

Lxd

GATE

n+ source n+ drain

WIRINGVoltage, V

W

p substrate, doping NA

tox

L/xd/

GATE

n+ source n+ drain

WIRINGVoltage, V /

W/

p substrate, doping *NA

tox /

Transistor ScalingDennard, et al., 1974

S

G

D

7

0.010.11

0.001

0.01

0.1

1

10

100

1000

Gate Length (microns)

Active Power

Passive Power

1994 2005

S

G

D

CMOS Power Issue:Active vs. Passive Power

Power components:

Active power

Passive power

• Gate leakage

• Source - Drain leakage

10S Tox=11APolysilicon Gate

S

G

D

Silicon (SOI) Gate Oxide

Po

wer

Den

sit

y (

W/c

m2)

Gate Length (microns)

Gate Leakage

Air Cooling limit

8

Has This Ever Happened Before?

Year of Announcement

1950 1960 1970 1980 1990 2000 2010

Mo

du

le H

ea

t F

lux(w

att

s/c

m2)

0

2

4

6

8

10

12

14

Bipolar

CMOS

?

Start of

Water Cooling

2005 ~ 2020: New utilization of technology• Multi-core, 3D integration, new memory devices, sensors, etc.

> 2020?: New technology Nanoelectronics Research Initiative

9

Key Systems Transitions

CMOS

Frequency & density

Power 5

1990’s – 2000’s

CPU 1

CPU 2

L2 Cache

CMOS SoC

2004 & Beyond

Integration & density

Blue Gene LMulti-core microprocessor,

ASIC library, design tools

BipolarFrequency

Multi-Chip Module (MCM)

1980’s

(Note: Figures not to scale)

CostPower

CostPower

10

Chip(2 processors)

Compute Card(2 chips, 2x1x1)

Node Board(32 chips, 4x4x2)

16 Compute Cards

System(64 cabinets, 64x32x32)

Cabinet(32 Node boards, 8x8x16)

2.8/5.6 GF/s4 MB

5.6/11.2 GF/s0.5 GB DDR

90/180 GF/s8 GB DDR

2.9/5.7 TF/s256 GB DDR

180/360 TF/s16 TB DDR

System Integration Example: BlueGene/L

11

Cell Processor

~250M transistors

~235mm2

Top frequency >4GHz

9 cores, 10 threads

> 256 GFlops (SP) @4GHz

> 26 GFlops (DP) @4GHz

Up to 25.6GB/s memory B/W

Up to 75 GB/s I/O B/W

Large design investment (time & money)

12

Heterogeneous Multi-Core Architectures

General

Purpose

Processor

MF1 MF2 MF3 MF4

MF5

MF6

MF7MF10

MF11

MF9 MF8

MF12

A possible ultimate evolution of on-chip architectures is Asynchronous

Heterogeneous Multi-Core with Flexible Processors Organization

MF(n) – application-specific processor

implementing a specific macro-function

(may need specialized devices)

• General-purpose CMOS CPU

• Several application-specific

processors/systems

• May be CMOS hybrids and/or

• Operate in multiple physical domain

Key Challenge:

Software Applications

13

New Device Types

3D, heterogeneous

integration

Time

Double-Gate / FinFET

Source Drain

Gate

Embedded

memory

Molecular devices

Spintronics

Quantum

cascade

Nanowire

Nanotube

Dra

in C

urr

en

t (l

og

(ID))

Gate Voltage (VGS)

S < kT/q

Fine-grain PLA

14

2007 ITRS Risk Assessmentof Potential Future Memory Devices

Scalability PerformanceEnergy

EfficiencyOff/On Ratio

Operational Reliability

Operation Temp.

CMOS Technology

Compatibility

CMOS Architecture Compatibility

Engineered Tunnel Barrier

2.4 2.3 2.2 2.0 2.2 2.7 2.7 2.5

Fuse /

Anti-fuse2.6 1.9 2.0 2.2 1.8 2.8 2.7 2.5

Nano-Mechanical

1.7 1.9 2.4 2.5 1.9 2.9 2.2 2.2

Electronic Effects

2.3 2.2 2.3 2.1 2.0 2.4 2.3 2.4

Ionic 2.6 2.0 2.4 2.1 1.7 2.5 2.1 2.5

Ferroelectric FET

1.8 2.0 1.9 2.1 1.7 2.6 2.3 2.3

Macro-molecular

2.1 1.8 2.1 1.8 1.4 2.2 1.9 2.3

Molecular 2.4 1.7 2.4 1.4 1.3 2.2 1.8 1.9

http://www.itrs.net/Links/2007ITRS/Home2007.htm (Emerging Research Devices, Table ERD9)

15

2007 ITRS Risk Assessmentof Potential Future Logic Devices

Scalability PerformanceEnergy

EfficiencyGain

Operational Reliability

Operation Temp.

CMOS Technology

Compatibility

CMOS Architecture Compatibility

1D Structures 2.4 2.2 2.5 2.3 2.0 2.5 1.8 2.3

Channel Replacement

Materials2.0 2.9 2.3 2.4 1.9 2.3 1.8 2.5

Single Electron

Transistors2.4 1.1 2.3 1.2 1.3 1.4 1.6 1.5

Molecular Devices

2.5 1.5 2.2 1.5 1.3 1.8 1.6 1.7

Ferromagnetic Devices

1.2 1.3 1.7 1.5 2.0 2.1 1.2 1.3

Spin Transistors

1.7 1.4 2.3 1.7 1.4 1.3 1.3 1.3

http://www.itrs.net/Links/2007ITRS/Home2007.htm (Emerging Research Devices, Table ERD10)

Emerging Research Devices Message: No good options for new logic devices – except for FET extensions! (Several options for new memory devices)

What is Information?

Source: IBM

Information is measure of distinguishability

manifested in physical form

17

Particle Location is an Indicator of State

1 1 0 0 1 0

18

Electronic switches can be of different nature, but they all have similar fundamentals

M V M

n n

p

19

What are the requirements/limitations

on the height and width the barrier?

Basic Equations of Two-well Bit

Eba

“Heisenberg constraints”

on minimum barrier width

2px

2htE

“Boltzmann constraint” on

minimum barrier height

Tk

E

B

bB exp

20

Classic Distinguishability: The Boltzmann constraint

bbit EE min

a

a

Eb

Eb

How small could the energy barrier height be ?

OR

Eb

2ln

)exp(5.0

)exp(

min TkE

Tk

E

Tk

E

Bb

B

b

B

berror

Distinguishability requirement: The

probability of spontaneous

transitions(errors) error<0.5 (50%)

Barrier control (gate)

21

Summarizing, what we have learned so far from fundamental physics

1) Minimum energy per binary transition 2lnmin TkE Bbit

2

13

2

min

106.41

cm

gate

xn4) Maximum gate density

)300(1042ln

14 KskT

tst

3) Minimum state switching time

tE Heisenberg

)300(5.12ln2

min KnmmkT

ax

2) Minimum distance between two distinguishable states

pxHeisenberg

Boltzmann

22

Total Power Dissipation (@Ebit= kTln(2))

2

61074.4cm

WPchip

T=300 K

The circuit would vaporize when it is turned on!

JTkE

s

Jcm

t

EnP

Bbit

bitchip

21

14

21213

1032ln

][104

][103][106.4

- A Catastrophe!

23

FETs approach the “kT” limit

Data compiled by

R. Keyes,

IBM Research Emeritus

24

Can we operate FETs near or below “kT”?

1. Conventional Logic:

Reduce ½CV2 toward the “kT” limit, accept the reduction in switching speed, and use redundancy and error correction to keep the error rate in bounds.(Refrigeration is allowed, but this makes economic sense only if total power dissipation is reduced.)

2. Reversible Logic:

Maintain ½CV2 well above kT, implement adiabatic switching, energy-conserving reversible logic circuits, and energy-recovering (i.e. resonant circuit) power supply to reduce energy losses per switching event to ~ kT or below.

25

How much energy must be dissipated to charge a capacitor?

Adiabatic Charging

( T >> RC)

26

Reversible Logic: Implementation with FETs

It is conceptually possible to build general purpose reversible computers with energy dissipation per operation going asymptotically to zero as frequency goes to zero.

But, frequency must be reduced by about 1/1000 to achieve benefits with respect to conventional approaches to CMOS logic.

Dissipation of 4 bit ripple counter (D. J. Frank, 1995) Need to find right device – system architecture combination that results in improved computation / sec / cm2 / watt

27

Devices for Nanoelectronics Circuits

Power / Heat Generation is the main limiting factor for scaling of device speed and switch circuit density

Scaling to molecular sizes may not yield performance increases Forced to trade-off between speed and density

Optimal dimensions for electronic switches should be ~5-50nm Achievable with Si – easily within the scope of ITRS projections

Going to other materials for FETs will likely achieve only “one-time” percentage gains

Need a new device mechanism or computation architecture to enable a new scaling path

28

Beyond CMOS Logic: What to look for?

Required characteristics:

Scalability

Performance

Energy efficiency

Gain

Operational reliability

Room temp. operation

Preferred approach:

CMOS process compatibility

CMOS architectural compatibility

Alternative state variables

Spin–electron, nuclear, photon

Phase

Quantum state

Magnetic flux quanta

Mechanical deformation

Dipole orientation

Molecular state

To beat the power problem requires:

A device with a lower energy, room temperature switching mechanism

or

A system that operates out of equilibrium or recovers operation energy as part of the logic computation

29

Nanoelectronics Research Initiative Milestones

2001-2004: Defining Research Needs ITRS-Emerging Research Device Technical Working Group NSF-SRC Ind-Academia-Govt “Silicon Nanoelectronics and Beyond” Workshops SIA Technology Strategy Committee workshops

Defined 13 Research Vectors for finding the “next switch”SIA Board passes resolution for formation of NRI

Current Member Companies:

Sep 2005: First NRI and NRI-NSF Solicitations released Jan 2006: Research Programs started

Sep 2007: NIST joins NRI

NRI partnership model highlighted in as sidebar in the National Nanotechnology Initiative (NNI) Strategic Plan (NNCO, 1/08)

30

NRI Mission Statement

NRI Mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe.

These devices should show significant advantage over ultimate FETs in power, performance, density, and/or cost to enable the semiconductor industry to extend the historical cost and performance trends for information technology.

To meet these goals, NRI pursues five research vectors, focused on discovering and demonstrating new devices and circuit elements for doing computation.

Finally, it is desirable that these technologies be capable of integrating with CMOS, to allow exploitation of their potentially complementary functionality in heterogeneous systems and to enable a smooth transition to a new scaling path.

31

NRI Primary Research Vectors

NEW DEVICEDevice with alternativestate vector

NEW WAYS TO CONNECTDEVICESNon-charge data transfer

NEW METHODS FOR COMPUTATIONNon-equilibrium systems

NEW METHODS TO MANAGEHEATNanoscale phonon engineering

NEW METHODS OF FABRICATIONDirected self-assembly devices

A

B

C

Out

A

B

C

Out

Columbia

Harvard

Purdue

UVA

Yale

UC Santa Barbara

Stanford

Notre Dame

U. Nebraska/Lincoln

U. Maryland

Cornell

Illinois-UC

Caltech

NRI Funded Universities

UC Los Angeles

UC Berkeley

UC Irvine

UC Santa Barbara

Stanford

U Denver

Portland State

U Iowa

Notre Dame Purdue

Illinois-UC Penn State

Michigan UT-Dallas

Cornell GIT

UT-Austin Rice Texas A&M

UT-Dallas ASU Notre Dame

U. Maryland NCSU Illinois UC

SUNY-Albany GIT Harvard

Purdue RPI Columbia

Caltech MIT NCSU

Yale UVA

Over 30 Universities in 18 States

NRI Research Centers

Leveraging industry, university, and both state & fed government funds, and driving university nanoelectronics infrastructure

WINWestern Institute of Nanoelectronics

INDEXInstitute for Nanoelectronics Discovery & Exploration

SWANSouthWest Academy for Nanoelectronics

MIND

Midwest Institute for Nanoelectronics Discovery

UCLA, UCSB, UC-Irvine, Berkeley, Stanford, U Denver, Iowa, Portland State

SUNY-Albany, GIT, RPI, Harvard, MIT, Purdue, Yale, Columbia, Caltech, NCSU, UVA

UT-Austin, UT-Dallas, TX A&M, Rice, ASU, Notre Dame, Maryland, NCSU, Illinois-UC

Notre Dame, Purdue, Illinois-UC, Penn State, Michigan, UT-Dallas, Cornell, GIT

Theme 1: Spin devicesTheme 2: Spin circuitsTheme 3: Benchmarks

& metricsTheme 4: Spin

Metrology

Task I: Novel state-variable devices

Task II: Fabrication & Self-assembly

Task III: Modeling & ArchTask IV: Theory & SimTask V: RoadmapTask VI: Metrology

Task 1: Logic devices with new state-variables

Task 2: Materials & structsTask 3: Nanoscale thermal

managementTask 4: Interconnect & ArchTask 5: Nanoscale

characterization

Theme 1: Graphene device: Thermal, Tunnel, and Spin

Theme 2: Interband Tunnel Devices

Theme 3: Non-equilibrium Systems Model / Meas.

Theme 4: Nanoarchitecture

34

Spin Wave Device ResearchMultiple PI‟s

35

Multiferroic Materials

Achievement: Demonstrated control of ferromagnetism with an electric field applied to a multiferroic.

Importance: First step in device development so that control of correlated properties is possible via a simple electric field.

R.Ramesh (UC Berkeley)

J. Orenstein (UC Berkeley)

Next: Electric

Field control

of spin waves

(linked with

UCLA and

UCSB efforts)

36

INSTITUTE FOR NANOELECTRONICSINSTITUTE FOR NANOELECTRONICS

DISCOVERY AND EXPLORATIONDISCOVERY AND EXPLORATION

INSTITUTE FOR NANOELECTRONICSINSTITUTE FOR NANOELECTRONICS

DISCOVERY AND EXPLORATIONDISCOVERY AND EXPLORATION

Spintronic SET. Device Operation

Global RF Magnetic Field Hoe-i t

In Resonance

= ER

Out of Resonance

ER= ER=

OFF State

Vgoff

OFF StateOFF State

Vgoff

ON State

Vgon

ON StateON State

Vgon

Single Electron Spin

DevicesRaynolds et al (UAlbany)

Quantum Dot DevicesOktyabrsky et al (UAlbany)

Ballistic Spin DevicesLabella et al (UAlbany)

Post CMOS Switches

S→ TS pump

A B

Z

A

BZ

Molecular Excitons

SpintronicsBaldo et al (MIT)

Logical Switches based on Complex OxidesAhn et al (Yale)

-100 -50 0 50 100

0.0

0.5

1.0

1.5

Field (Oe)

GM

R (

%)

NiFe6/Cu6/Co8

2 m, 200 nm

S2

S2R

S1

S3

Multi bits logic

Magnetoelectronic DevicesRoss et al (MIT)

Graphene Nanowire SwitchesMurali and DeHeer (GT)

The Molecular Conformational Switch: The Molecular Conformational Switch: Operating PrincipleOperating Principle

• Employ metal ion location as a “gate” for switching of charge transport across a self-aligned molecular system

• Ion location is modulated by interaction between ion-bearing moiety and external “signal” Configuration and switching

paradigm for interleaved metal/arene “atomic relay” system

Molecular Nanowire SwitchesKaloyeros et al (UAlbany)

Reconfigurable One-Dimensional (1D)

Switch (R1DS)

Ji Ung Lee (UAlbany)

Graphene based Quantum DevicesCharles Marcus (Harvard)

Quantum Dot ModelingShur et al (RPI)

37

New idea: Utilizing excitons on molecules for logic Attributes:

Easy to generate and convert singlet or triple optically or electrically Decays produce photons, not phonons (less heat generation; recoverable? interconnect?) Long lifetime (seconds)

Challenges: Excitons are neutral – transport is diffusive Strong spin-dependent exciton interactions

Exciton Fission Provides “Gain” Light Emission is Spin Dependent

Concept for a Programmable Logic Operation: NOR gate

singlet

triplet

tripletS1

T1FluorescenceFluorescence

Molecular ground stateS0

Spin disallowedSpin disallowed

Triplet propagates to output (Z).

Diffuse to input of next gate

Singlet quenched by triplet at A. Triplet is excited.

Excited triplet decays. No output at Z

A or B = 1

S→TS pump

A B

Z S→TS pump

A B

Z

A = B = 0

MOLECULAR EXCITON SPINTRONICS M. Baldo, MIT

INSTITUTE FOR NANOELECTRONICSINSTITUTE FOR NANOELECTRONICS

DISCOVERY AND EXPLORATIONDISCOVERY AND EXPLORATION

INSTITUTE FOR NANOELECTRONICSINSTITUTE FOR NANOELECTRONICS

DISCOVERY AND EXPLORATIONDISCOVERY AND EXPLORATION

38

Pseudospintronics in Bilayer GrapheneA. MacDonald, UT-Austin

Giant Electro-resistance

V

Pola

riza

tion

“Collective” FET?

E

p

New theory: Utilize collective behavior of electrons in bilayer graphene to create a switch Theory shows carriers can tunnel

as coherent collection betweenlayers at very small voltages Potential for large changes in

resistance for small energy Hysteresis for potential latching

logic

39

“Bilayer pseudoSpin Field Effect Transistor (BiSFET): a proposed new logic device”

S.K. Banerjee, L.F. Register, E.Tutuc, D.Reddy and A. Macdonald., EDL

Bi-layer pseudoSpin FieldEffect Transistor (BiSFET)

Simulated devices and basic logic gates (SPICE) Inverter with complementary BiSFET design simulated at 100 GHz with

25mV operation at just 2x Landauer limit

Schematic

Device

Wire

Gate

Inverter

Experimental

i1

i3

i2

Inverted

output

0 1

i o

i o

0

1

R. Cowburn, M. Welland, “Room temperature magnetic

quantum cellular automata,” Science 287, 1466, 2000

A. Imre, “Experimental Study of Nanomagnets for Magnetic

QCA Logic Applications,” U. of Notre Dame, Ph.D.

Dissertation.

MA

C1

0

1

0

0

0

1

1

1

1

1

1

0

0

0

1

1

1

0

0

0

0

0

0

1

1

1

0

0

1

0

1

1

0

B MMA

C1

0

1

0

0

0

1

1

1

1

1

1

0

0

0

1

1

1

0

0

0

0

0

0

1

1

1

0

0

1

0

1

1

0

1

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

1

1

0

0

0

1

1

1

0

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

1

1

0

0

1

1

0

0

1

0

1

1

0

0

1

1

0

B

A. Imre, et. al.

“Magnetic Logic

Devices Based on

Field-Coupled

Nanomagnets,”

NanoGiga 2007.

A. Imre, et. al., “Majority logic gate for Magnetic

Quantum-Dot Cellular Automata,”

Science, vol. 311, No. 5758, pp. 205–208,

January13, 2006.

A. Imre, et. al., “Majority logic gate for Magnetic Quantum-

Dot Cellular Automata,” Science, vol. 311, No. 5758, pp.

205–208, January13, 2006.

Magnetic Quantum Cellular Automata (MQCA)M. Niemier, Notre Dame

41

2005 ITRS Energy / Cost / Area / Delay

42

Computing with Alternate State Variables

Many different device ideas being considered –some „likely‟ attributes compared to CMOS:

Slower

Denser / 3D

Local interconnect focused

Uniform arrays / sea-of-gates

Variability still an issue

Architecture / System Question:

How to get high computation throughput with these attributes?

Proof of concept?

„Switch‟ ~ msecs

~108 MIPs

~30W

43

Two Take-aways

Power will continue as the principal scaling issue for all IC applications

CMOS will continue to scale over at least the next decade, with emphasis on utilizing increasing transistor density over increasing frequency

Any new technology must overcome the power / performance limits of a charge-based FET to continue the scaling trend of increased function / dollar

Does it offer the prospect of lower energy operation / storage?

Does it offer the prospect of non-equilibrium (e.g. ballistic) operation?

Does it offer the prospect of energy recovery?

44Source: Kurzweil 1999 – Moravec 1998

1900 1920 1940 1960

IE-5

IE-3

IE+0

IE+3

IE+6

IE+9

IE+12

Co

mp

uta

tio

ns p

er

se

co

nd

IntegratedCircuit

DiscreteTransistor

VacuumTube

Electro-Mechanical

Mechanical

202020001980

Nanotechnology

NRI Goal: Continue the Curve . . .

$1000 Buys:

45

Nanoelectronics Research Initiative

Jeff Welser, Directorjeff.welser@src.org

Allison Hilbert, Executive Assistantallison.hilbert@src.org