The EKV MOSFET Model for Circuit Simulation · PDF fileThe EKV MOSFET Model for Circuit Simulation October, 1998 Matthias Bucher, Fabien Théodoloz, François Krummenacher Electronics

The EKV MOSFET Model for Circuit Simulation

October, 1998

Matthias Bucher, Fabien Théodoloz, François Krummenacher

Electronics Laboratories (LEG)

Swiss Federal Institute of Technology, Lausanne (EPFL), Switzerland

[email protected], [email protected], [email protected]

© M. BUCHER 1998 The EKV MOSFET Model for Circuit Simulation 2

Motivation & Outline

☞ Motivation: analog and mixed analog-digital circuit design:

✔need for a continuous, physics based MOSFET model

✔must represent weak and moderate inversion correctly

✔a model that allows designers to go from hand-calculation to full-circuit simula-tion (hierarchical structure)

✔need for meaningful statistical circuit simulation

☞ Outline:

✔the EKV MOSFET model structure

✔modelled effects and parameters

✔parameter extraction and results

✔model benchmarks and comparisons

✔outlook on future developments


Model Structure (1/4) : Bulk Reference

☞ Bulk-reference, symmetric model structure.

☞ Drain current expression including drift and diffusion:

(1)

x

y

L

n+ n+p+

S

G

DB

VS

VG

VD

ID

p substrate

Leff

tox

ID VD

VS

VG

G

S

D

B

ID W µ Q′I–( )Vchd

xd-----------⋅ ⋅ ⋅=


Model Structure (2/4) : Drain Current

☞ Integration of from source to drain:

(2)

Vch

VPVDVS

n VP⋅

Q′I–

C′ox-----------

ID

β-----

ID IF IR–=

gmd

β---------

gms

β---------

weak inversion

A

B

CD

E

β µ C′ox

Weff

Leff----------⋅ ⋅=strong inversion

Inve

rsio

n C

harg

e D

ensi

ty

Channel Voltage

Q′I

ID βQ′I–

C′ox-----------

Vchd⋅VS

VD

∫β

Q′I–

C′ox-----------

Vchd⋅VS

∞

∫

IF VP VS–( )

βQ′I–

C′ox-----------

Vchd⋅∞

VD

∫

IF VP VD–( )

–= =


Model Structure (3/4) : Pinch-off Voltage

☞ Current normalization using the Specific current :

(3)

☞ Pinch-off voltage accounts for...

✔threshold voltage and substrate effect

(4)

☞ Slope factor :

(5)

IS

ID IF IR– IS i f i r–( )⋅ 2nβUT2

i f i r–( )⋅= = =

VP

VTO γ 2qεsNsub( ) C′ox⁄=

VP VG VTO γ VG VTO Ψ0γ2---+

2+– Ψ0

γ2---+

–⋅––=

n

nVG∂

∂VP1–

1γ

2 Ψ0 VP+---------------------------+= =


Model Structure (4/4) : Normalized G MS/ID Ratio

☞ Coherent model for static, dynamic and noise aspects.

✔derived from the normalized transconductance-to-current ratio:

✔common variable to the entire model: normalized currents if and ir (forward and reverse)

Static Model

if (V), ir (V)

Dynamic Model

QI,G,D,S,B (if, ir)

Noise Model

SNth (QI(if, ir))

Mobility Model

µs (QB,QI(if, ir))

gms Ut⋅ID

-------------------Transconductanceto current ratio

gms VS∂∂ID–≡


Normalized Transconductance vs. Current

☞ Normalized GMS/ID vs. ID✔in saturation, from weak to strong inversion, compared to a numerical solution of the Poisson equation

2

4

68

0.1

2

4

68

1

2

g ms·

UT /

I D

0.001 0.01 0.1 1 10 100 1000

if = ID / IS

asymptotes analytical numerical

(GAMMA=0.7 √ V)

1/ √ if


Normalized Transconductance vs. Current

☞ Three different CMOS technologies:✔universal behaviour, almost independent of technology✔therefore, the EKV model is well adapted for a large range of technologies

☞ Excellent match in the weak and moderate inversion regions.

1.0

0.8

0.6

0.4

0.2

0.0

g ms·

UT /

I D

0.001 0.01 0.1 1 10 100 1000

ID / IS

analytic interpolation measured characteristics for:

0.5 µm, GAMMA=0.64 √V 0.7 µm, GAMMA=0.75 √V 1 µm, GAMMA=0.72 √V


Modelled Effects: Long-Channel

☞ Physics-based modelling of weak, moderate and strong inver-sion.

☞ Relation with geometrical and process variables as:

✔oxide thickness, junction depth

✔effective channel length and width

☞ Effects of substrate doping level, substrate effect.

☞ Vertical field dependent mobility.


Modelled Effects: Short-Channel

☞ Common short-channel effects:

✔velocity saturation

✔channel length modulation (CLM)

✔two-dimensional bulk charge-sharing for short-and narrow-channel effects

✔reverse short-channel effect (RSCE)

✔substrate current effects on drain conductance

☞ Short-distance matching for statistical circuit simulation.

✔area- and bias-dependent device matching for:

threshold voltage

gain factor (mobility)

substrate effect

✔a unique feature which is commonly unavailable in other public-domain models!


EKV v2.6: 18 Intrinsic Model Parameters

☞ Completed with 2 noise, 4 temperature and 3 matching parameters.

Purpose NAME DESCRIPTION UNITS EXAMPLE

Processparameters

COX gate oxide capacitance per unit area 3.45E-3

XJ junction depth m 0.15E-6

DW channel width correction m -0.05E-6

DL channel length correction m -0.1E-6

Doping & Mobilityrelated parameters

VTO long-channel threshold voltage V 0.55

GAMMA body effect parameter 0.7

PHI bulk Fermi potential (*2) V 0.8

KP transconductance parameter 160E-6

E0 vertical characteristic field for mobility reduction 80E6

UCRIT longitudinal critical field 4.0E6

Short- & narrow-channeleffect parameters

LAMBDA depletion length coefficient (channel length modulation) - 0.3

WETA narrow-channel effect coefficient - 0.1

LETA short-channel effect coefficient - 0.3

Q0 reverse short-channel effect peak charge density 500E-6

LK reverse short-channel effect characteristic length m 0.34E-6

Substrate currentrelated parameters

IBA first impact ionization coefficient 1 / m 260E6

IBB second impact ionization coefficient V / m 350E6

IBN saturation voltage factor for impact ionization - 1.0

F m2⁄

V

A V2⁄

V m⁄

V m⁄

A s⋅ m2⁄


Statistical Circuit Simulation Including Matching

☞ Area related mismatch model (Pelgrom e.a.):

(6)

(7)

(8)

✔during Monte-Carlo statistical circuit simulation, the parameters are individually varied for each matched transistor.

☞ Leads to an important reduction of simulation effort!

✔no need to create individual parameter sets for each geometry

NAME DESCRIPTION UNITS Example

AVTO area related threshold voltage mismatch parameter Vm - DEV=15E-9

AKP area related gain mismatch parameter m - DEV=25E-9

AGAMMA area related body effect mismatch parameter - DEV=10E-9Vm

VTOa

VTOAVTO

Weff Leff⋅---------------------------+=

GAMMAa

GAMMAAGAMMA

Weff Leff⋅---------------------------+=

KPa

KP 1 AKP

Weff Leff⋅---------------------------+

⋅=


Vertical Field Dependent Mobility

☞ Local effective field dependence on depletion and inversion charges:

(9)

☞ Local mobility dependence on vertical field:

(10)

✔ for n-channel, for p-channel

✔the parameter E0 is the vertical critical field across the oxide

☞ Local mobility expression is integrated along the channel.

Eeff x( )Q'B x( ) η Q'I x( )⋅+

ε0εsi

---------------------------------------------=

µ x( )µ0'

1Eeff x( )

E0----------------+

--------------------------=

η 1 2⁄= η 1 3⁄=


Mobility Model (0.5um CMOS)

☞ Good behaviour for mobility reduction for n- and p-channels.

☞ Substrate effect is correctly accounted for.

☞ No back-bias dependence required!

14x10-6

12

10

8

6

4

2

0

I D

3.02.52.01.51.00.50.0

VGS

n-channelW=L=10µmVDS=0.05 V

Measured SimulatedVB=0

VB=-1.5V

4x10-6

3

2

1

0

I D

-3.0-2.5-2.0-1.5-1.0-0.50.0

VGS

p-channelW=L=10µmVDS=0.05 V

Measured SimulatedVB=0

VB=1.5V

n-channel p-channel


Reverse Short-Channel Effect

☞ Measured/simulated change of threshold voltage vs.

(0.5µm n-channel).

50

40

30

20

10

0

-10

-20

∆VT [m

V]

0.1 1 10

Ldrawn [µm]

Measure Simulation

Ldrawn


Charge-Based Dynamic Model

☞ Integration of inversion charge density along the channel:

(11)

☞ Integration of is performed in terms of normalized current.

☞ Channel charge partitioning and gate charge:

(12)

☞ Derivation of transcapacitances:

(13)

QI W QI ′ y( ) yd⋅0

L

∫⋅=

QI

QD WyL--- QI ′ y( ) yd⋅ ⋅

0

L

∫⋅= QS QI QD–= QG QI QB––=

CXYZ VYZ∂∂± QX i f i r,( )( )=


Charges vs. Gate Voltage

☞ Continuous node charges from weak to strong inversion.

✔allows charge conservation in transient simulation

-1 0 1 2 3 4 5-0.3

0.6

-0.2

0.5

-0.1

0.4

0

0.3

0.1

0.2

QS & QD (VD=0V)

QS, QD (VD=2V)

QG (VD=2V)

QG (VD=0V)

VG [V]

QB

Charges normalized to WLCox [V]


Capacitances vs. Gate Voltage

☞ Capacitances are valid in all operating regions:✔correct weak-to-strong inversion behaviour✔continuous, and symmetric at VDS=0

-1 0 1 2 3 4 5-0.2

1.2

0.0

1.0

0.2

0.8

0.4

0.6

CGBCGS & CGD (VD=0V)

CGS (VD=2V)

CGD (VD=2V)CBS (VD=2V)

CBS & CBD (VD=0V)

CBD (VD=2V)

VG [V]

Normalized intrinsic capacitan


Capacitances vs. Drain Voltage

☞ Smooth behaviour from conduction to saturation.

✔comparison between new charge-based and former capacitances-only models

0 1 2-0.1

0.8

0

0.7

0.1

0.6

0.2

0.5

0.3

0.4

CGS (VG=2V)

CGD (VG=2V)

CGB (VG=2V)

CGB (VG=0.8V)

CGS (VG=0.8V)

CGD (VG=0.8V)

CBD (VG=2V)

CBD (VG=0.8V)

VDB [V]

No

rmal

ized

intr

insi

c ca

pac

itan

ces


Dynamic Model - Summary

☞ Charge-based for charge conservation in transient simulation.

☞ Charges and transcapacitances are “smooth”:

✔valid from weak to strong inversion and from conduction to saturation

☞ Symmetric operation in terms of and .

☞ Short-channel effects are included through the pinch-off volt-age (charge-sharing, RSCE).

☞ Extensions are under development:

✔velocity saturation and space-charge effects on capacitances

✔bias dependent overlap capacitances

VD VS

VP


Parameter Extraction Method

☞ Hierarchical structure allows separation of physical effects and parameters.

☞ Mixed direct extraction and local optimization is used.

☞ Dedicated parameter extraction method:

✔based on pinch-off voltage measurement technique [1] to determine substrate effect, including for charge-sharing and RSCE.

☞ Uses array of transistors in the W/L plane.

☞ Sequential task that can be automated.

✔well suited for statistical purposes


Parameter Extraction Sequence (DC)

☞ Extraction sequence using direct extraction and optimization.

VP vs. VG

VTO, GAMMA, PHI

ID vs. VG

KP, E0

WIDELONG

specific current measurement

VP vs. VG LETA

ID vs. VDUCRIT, LAMBDA

WIDESHORT

VP vs. VG WETA

NARROWLONG

PRELIMINARYEXTRACTION

Extraction ofDL, DW, RSHfrom several geometries

final checkand fine tuning

NARROWSHORT

VP vs. VG LETAVP vs. VG

LETA, Q0, LK

L

IB vs. VG

IBA , IBB , IBN



(EKV v2.6)


Pinch-off Voltage Measurement Method

☞ Constant current bias for the VP vs. VG measurement.

✔used for different channel lengths and widths

☞ Direct parameter extraction for threshold voltage and sub-strate effect parameters.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5543210

n-channelVTO=0.752 VGAMMA=0.755 ÃVPHI=0.576 VLETA=0.503WETA=0.256

simulated measured

W=20µmL=20µm

W=20µmL=0.7µm

W=0.8µmL=20µm

IBVG

VS=VP

IB

IS2-----≅ n β UT

2⋅ ⋅=VG

VS


Submicron (0.5um) CMOS: Long-Channel Characteristics

☞ Weak-to-strong inversion continuity.

☞ Accuracy of weak inversion slope and substrate effect.

✔no additional parameters used for adapting weak inversion slope

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

I D [

A]

3.02.52.01.51.00.50.0

VG [V]

VS=0V 0.5V 1V 1.5V

n-channelW=10 µmL=10 µmVD=3V

IS

300x10-6

250

200

150

100

50

0

I D [A

]

3.02.52.01.51.00.50.0

VD [V]

10-8

10-7

10-6

10-5

10-4

10-3

g ds

[A/V

]

1V

VG=3V

2.5V

2V

1.5V

n-channelW=10 µmL=10 µmVS=0 V


Submicron (0.5um) CMOS: Intermediate Channel-Length Characteristics

☞ Correct threshold voltage.

☞ Demonstrates good scaling behaviour.

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

I D [

A]

3.02.52.01.51.00.50.0

VG [V]

VS=0V 0.5V 1V 1.5V

n-channelW=10 µmL=1 µmVD=3V

IS

2.5x10-3

2.0

1.5

1.0

0.5

0.0

I D [A

]

3.02.52.01.51.00.50.0

VD [V]

10-6

10-5

10-4

10-3

10-2

g ds

[A/V

]

1V

VG=3V

2.5V

2V

1.5V

n-channelW=10 µmL=1 µmVS=0 V


Submicron (0.5um) CMOS: Short-Channel Characteristics

☞ Accurate output conductance for shortest channel transistor.

☞ Includes CLM, velocity saturation, substrate current.

☞ Single model card is used for all geometries.

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

I D [A

]

3.02.52.01.51.00.50.0

VG [V]

VS=0V 0.5V 1V 1.5V

n-channelW=10 µmL=0.5 µmVD=3V

IS

3.5x10-3

3.0

2.5

2.0

1.5

1.0

0.5

0.0

I D [

A]

3.02.52.01.51.00.50.0

VD [V]

10-6

10-5

10-4

10-3

10-2

gd

s [A

/V]

1V

VG=3V

2.5V

2V

1.5V

n-channelW=10 µmL=0.5 µmVS=0 V


Deep-Submicron (0.25um) CMOS

☞ EKV v2.6: results for 0.25um CMOS technology.

Long-channel Short-channel (0.25um)


Benchmark: EKV vs.

☞ EKV model exhibits qualitatively correct behaviour.

✔no particular parameter adaptation is required

gms UT⋅ ID⁄ ID

1.0

0.8

0.6

0.4

0.2

0.0

gm

s*U

T/I D

10-10 10-9 10-8 10-7 10-6 10-5 10-4

ID

Measured Simulated (EKV v2.6)

n-channelW=L=10µmVG=1.5 VVD=2 V


Benchmark: BSIM3v3 vs.

☞ BSIM3v3 exhibits qualitatively poor behaviour in weak and moderate inversion.

✔parameter adaptation is required (VOFF, NFACT)

gms UT⋅ ID⁄ ID

1.0

0.8

0.6

0.4

0.2

0.0

gm

s*U

T/I D

10-10 10-9 10-8 10-7 10-6 10-5 10-4

ID

n-channelW=L=10µmVG=1.5VVD=2V

MeasuredSimulated (BSIM3v3)


Benchmark: Substrate Effect, EKV v2.6

☞ Adequate behaviour over the whole bias range for EKV.

☞ Accurate prediction of slope factor .

2.0

1.5

1.0

0.5

0.0

-0.5

VS

3.02.52.01.51.00.50.0

VG

n-channelW=L=10 µm


1.7

1.6

1.5

1.4

1.3

1.2

1.1

n

3.02.52.01.51.00.50.0

VG

n-channelW=L=10 um


VP vs. VG n vs. VG

n


Benchmark: Substrate Effect, BSIM3v3

☞ Inadequate behaviour for negative VSB

✔possible origin of error: source reference!

2.0

1.5

1.0

0.5

0.0

-0.5

VS

3.02.52.01.51.00.50.0

VG

n-channelW=L=10 µm

Measured Simulated (BSIM3v3)

1.7

1.6

1.5

1.4

1.3

1.2

1.1

n

3.02.52.01.51.00.50.0

VG

n-channelW=L=10 um

Measured Simulated (BSIM3v3)

VS vs. VG n vs. VG


Benchmark: D/A Converter Circuit

☞ A typical current divider circuit used in D/A converters [2].✔each stage divides the reference current by a factor of 2

✔principle of an R-2R ladder circuit

☞ Expected behaviour: perfect current divider!

✔ratio-based circuit technique (aspect ratios used: S, 2S)

I

I I/2 I/4 I/8 I/16 I/16

M1 M2 M4 M6 M8 M10 M12

M3 M5 M7 M9 M11I I/2 I/4 I/8 I/16

2SS S S S S S

2S 2S 2S 2S 2S


Benchmark: D/A Converter, EKV v2.6

☞ EKV model exhibits adequate ratio-based circuit behaviour

✔the converter works as should be expected according to circuit principle

1e-07 1e-041e-06 1e-05 1.00

1.10

1.01

1.09

1.02

1.08

1.03

1.07

1.04

1.06

1.05

W(I1) W(I2) W(I3) W(I4) W(I5) W(I6)

Nor

mal

ized

cur

rent

(MS

B-L

SB

)

Reference current

<5% max error for LSB


Benchmark: D/A Converter, BSIM3v3

☞ BSIM3v3 exhibits inadequate ratio-based circuit behaviour

✔a serious error in the circuit is predicted

✔behaviour is unrelated to small geometry effects (long and wide MOS are used)

1e-07 1e-041e-06 1e-05 0.9

1.5

1.0

1.4

1.1

1.3

1.2

W(I1) W(I2) W(I3) W(I4) W(I5) W(I6)

Nor

mal

ized

cur

rent

(M

SB

-LS

B)

Reference current

40% max error for LSB


Benchmarks - Summary

☞ A MOSFET model should provide “safe limits” for fundamen-tal physical aspects

✔reliance on parameter extraction can be troublesome

☞ Source-reference may result in non-physical behaviour.

☞ Physical limits are not guaranteed by the BSIM3v3 model in particular for the characteristic.

☞ Number of intrinsic model parameters used:

✔EKV v2.6: 18

✔BSIM3v3: >65

✔Philips MOS Model 9: >55

gms Ut⋅ ID⁄


EKV v2.6 Model Availability in Simulators

☞ Implementations available:

✔ELDO (Mentor Graphics)

✔PSPICE (OrCad)

✔SABER (Analogy)

✔SMARTSPICE (Silvaco)

☞ Implementations in progress (autumn ‘98):

✔APLAC (Nokia, University of Helsinki)

✔HSPICE/CMI (Avant!)

✔SMASH (Dolphin Integration)

✔SPECTRE (Cadence)

✔SPICE3F5 (UC Berkeley)

☞ ...check exact state of implementation with simulator vendors.


EKV v2.6 Model Parameters & Extraction Availability

☞ Extraction tools:

✔UTMOST (Silvaco)

✔IC-CAP (HP), custom parameter extraction through EPFL

☞ Support of EKV model parameters:

✔uEM Marin, Switzerland

✔announced: MOSIS (US)/EUROPRACTICE (EU)

✔evaluation in several European foundries


EKV Model - Summary

☞ Need for a model dedicated to low-voltage, low-power analog and mixed analog-digital design and simulation

✔technology trends and scaling of supply voltage increase the importance of weak and moderate inversion regions

☞ EKV v2.6: a model with unique features and capabilities:

✔first-order hand-calculation possible!

✔excellent weak and moderate inversion modelling

✔major physical effects modelled, good adaptation to current CMOS technolo-gies, acceptable results for deep sub-micron CMOS

✔dedicated charge-based dynamic model and thermal noise model ; valid from weak to strong inversion, extensions for short-channel are being addressed

✔uses only 18 intrinsic “core” parameters, simple parameter extraction method

✔well suited for statistical circuit simulation including matching


Outlook

☞ Current and future model developments include:

✔further refined mobility model

✔weak inversion slope degradation for very short channel devices

✔improved short-channel dynamic model

✔polydepletion and quantum-mechanical effects

☞ Current research in the context of the EKV MOSFET model:

✔RF modelling

✔Low-temperature modelling

✔Non-quasistatic modelling

✔SOI modelling


References

[1] M. Bucher, C. Lallement, C. Enz, “An Efficient Parameter Extraction Methodology for the EKV MOST Model”, Proc.1996 IEEE Int. Conf. on Microelectronic Test Structures, Vol. 9, pp. 145-150, March 1996

[2] C. Enz, E. Vittoz, “CMOS Low-Power Analog Circuit Design”, Tutorial Int. Symp. Circ. Syst., Atlanta, May, 1996.

[3] C. C. Enz, F. Krummenacher and E. A. Vittoz, “An Analytical MOS Transistor Model Valid in All Regions of Opera-tion and Dedicated to Low-Voltage and Low-Current Applications,” Analog Integrated Circuits and Signal Processing,8, pp. 83-114, July 1995

[4] M. Bucher, C. Lallement, C. Enz, F. Théodoloz, F. Krummenacher, “The EPFL-EKV MOSFET Model Equations forSimulation, Model Version 2.6”, Technical Report, Electronics Laboratories, Swiss Federal Institute of Technology(EPFL), Lausanne, Switzerland, June, 1997.

[5] M. Bucher, C. Lallement, C. Enz, F. Théodoloz, F. Krummenacher, “Scalable GM/I Based MOSFET Model”, Proc.Int. Semicond. Device Research Symp., pp. 615-618, Charlottesville, VA, December 10-13, 1997.

[6] C. Lallement, C. Enz and M. Bucher, “Simple solutions for modelling the non-uniform substrate doping”, in Proc.IEEE Int. Symp. Circuits Syst., vol. 4, Atlanta, pp. 436-439, May 1996

[7] C. Lallement, M. Bucher, C. C. Enz, “Modelling and Characterization of the Non-Uniform Substrate Doping,” SolidState Electron., Vol. 41, No. 12, pp. 1857-1861, 1997.

[8] M. Bucher, C. Lallement, C. C. Enz and F. Krummenacher, “Accurate MOS Modelling for Analog Circuit SimulationUsing the EKV Model,” Proc. IEEE Int. Symp. Circuits Syst., pp. 703-706, May 1996.

[9] C. C. Enz, “MOS Transistor Modeling Dedicated to Low-Current and Low-Voltage Analog Circuit Design and Simu-lation,” in Low-power HF Microelectronics: A Unified Approach, Ed. by G. Machado, IEE Book Publishing, Ch. 7,1996, pp. 247-299, ISBN 0 85296 874 4.

[10]G. A. S. Machado, C. C. Enz, M. Bucher, “Estimating Key Parameters in the EKV MOST Model for Analogue Designand Simulation”, Proc. IEEE Int. Symp. Circuits Syst., pp. 1588-1591, Seattle, Washington 1995.

Documents

The EKV MOSFET Model for Circuit Simulation · PDF fileThe EKV MOSFET Model for Circuit Simulation October, 1998 Matthias Bucher, Fabien Théodoloz, François Krummenacher Electronics