TDA8929T Controller class-D audio amplifier Sheets/NXP PDFs...DATA SHEET Preliminary speciﬁcation File under Integrated Circuits, IC01 2001 Dec 11 INTEGRATED CIRCUITS TDA8929T Controller

DATA SHEET

Preliminary specificationFile under Integrated Circuits, IC01

2001 Dec 11

INTEGRATED CIRCUITS

TDA8929TController class-D audio amplifier

2001 Dec 11 2

Philips Semiconductors Preliminary specification

Controller class-D audio amplifier TDA8929T

CONTENTS

1 FEATURES

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 ORDERING INFORMATION

5 QUICK REFERENCE DATA

6 BLOCK DIAGRAM

7 PINNING

8 FUNCTIONAL DESCRIPTION

8.1 Controller8.2 Pulse width modulation frequency8.3 Protections8.3.1 Diagnostic temperature8.3.2 Diagnostic current8.3.3 Start-up safety test8.4 Differential audio inputs

9 LIMITING VALUES

10 THERMAL CHARACTERISTICS

11 QUALITY SPECIFICATION

12 DC CHARACTERISTICS

13 AC CHARACTERISTICS

14 SWITCHING CHARACTERISTICS

14.1 Minimum pulse width

15 TEST AND APPLICATION INFORMATION

15.1 Test circuit15.2 BTL application15.3 Mode pin15.4 External clock15.5 Reference designs15.6 Reference design bill of material15.7 Curves measured in reference design

16 PACKAGE OUTLINE

17 SOLDERING

17.1 Introduction to soldering surface mountpackages

17.2 Reflow soldering17.3 Wave soldering17.4 Manual soldering17.5 Suitability of surface mount IC packages for

wave and reflow soldering methods

18 DATA SHEET STATUS

19 DEFINITIONS

20 DISCLAIMERS

2001 Dec 11 3



1 FEATURES

• Operating voltage from ±15 to ±30 V

• Very low quiescent current

• Low distortion

• Fixed gain of 30 dB Single-Ended (SE) or 36 dBBridge-Tied Load (BTL)

• Good ripple rejection

• Internal switching frequency can be overruled by anexternal clock

• No switch-on or switch-off plop noise

• Diagnostic input for short-circuit and temperatureprotection

• Usable as a stereo Single-Ended (SE) amplifier or as amono amplifier in Bridge-Tied Load (BTL)

• Start-up safety test, to protect for short-circuits at theoutput of the power stage to supply lines

• Electrostatic discharge protection (pin to pin).

2 APPLICATIONS

• Television sets

• Home-sound sets

• Multimedia systems

• All mains fed audio systems

• Car audio (boosters).

3 GENERAL DESCRIPTION

The TDA8929T is the controller of a two-chip set for a highefficiency class-D audio power amplifier system. Thesystem is divided into two chips:

• TDA8929T; the analog controller chip in a SO24package

• TDA8926J/ST/TH or TDA8927J/ST/TH; a digital powerstage in a DBS17P, RDBS17P or HSOP24 powerpackage.

With this chip set a compact 2 × 50 W or 2 × 100 W audioamplifier system can be built, operating with high efficiencyand very low dissipation. No heatsink is required, ordepending on supply voltage and load, a very small one.The system operates over a wide supply voltage rangefrom ±15 up to ±30 V and consumes a very low quiescentcurrent.

4 ORDERING INFORMATION

TYPE NUMBERPACKAGE

NAME DESCRIPTION VERSION

TDA8929T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

2001 Dec 11 4



5 QUICK REFERENCE DATA

Note

1. VP = ±25 V.

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

General; note 1

VP supply voltage ±15 ±25 ±30 V

Iq(tot) total quiescent current − 20 30 mA

Stereo single-ended configuration

Gv(cl) closed-loop voltage gain 29 30 31 dB

Zi input impedance 45 68 − kΩVn(o) noise output voltage − 220 400 µV

SVRR supply voltage ripple rejection 40 50 − dB

αcs channel separation − 70 − dB

VOO DC output offset voltage − − 150 mV

Mono bridge-tied load configuration


Zi input impedance 23 34 − kΩVn(o) noise output voltage − 280 − µV

SVRR supply voltage ripple rejection − 44 − dB

VOO DC output offset voltage − − 200 mV

2001 Dec 11 5



6 BLOCK DIAGRAM

handbook, full pagewidth

MGW148

STABILIZER

SGND

SGND

SGND

SGND

4

1 3

5

2

7

6

11

8

9

12 10

17

14

13

16

22

15

19

23

24

21

20Rfb

Rfb

mute

mute

mute

V/I

V/I

SGND

TDA8929TSGND

OSCILLATOR

WINDOWCOMPARATOR

WINDOWCOMPARATOR

MODE

MANAGER

18

VSS1

SGND1

VDD1

IN1−

IN1+

MODE

OSC

IN2+

IN2−

VDD2

SGND2

VSS2(sub)

SW1

REL1

DIAGCUR

EN1

STAB

VSSD

PWM1

PWM2

EN2

DIAGTMP

REL2

SW2

Fig.1 Block diagram.

2001 Dec 11 6



7 PINNING

SYMBOL PIN DESCRIPTION

VSS1 1 negative analog supply voltagechannel 1

SGND1 2 signal ground channel 1

VDD1 3 positive analog supply voltagechannel 1

IN1− 4 negative audio input channel 1

IN1+ 5 positive audio input channel 1

MODE 6 mode select input(standby/mute/operating)

OSC 7 oscillator frequency adjustment, ortracking input

IN2+ 8 positive audio input channel 2

IN2− 9 negative audio input channel 2

VDD2 10 positive analog supply voltagechannel 2

SGND2 11 signal ground channel 2

VSS2(sub) 12 negative analog supply voltagechannel 2 (substrate)

SW2 13 digital switch output channel 2

REL2 14 digital control input channel 2

DIAGTMP 15 digital input for temperature limiterror report from power stage

EN2 16 digital control output for enablechannel 2 of power stage

PWM2 17 input for feedback from PWMoutput power stage channel 2

VSSD 18 negative digital supply voltage;reference for digital interface topower stage

STAB 19 pin for a decoupling capacitor forinternal stabilizer

PWM1 20 input for feedback from PWMoutput power stage channel 1

EN1 21 digital control output for enablechannel 1 of power stage

DIAGCUR 22 digital input for current error reportfrom power stage

REL1 23 digital control input channel 1

SW1 24 digital switch output channel 1

handbook, halfpageVSS1

SGND1

VDD1

IN1−

IN1+

MODE

OSC

IN2+

IN2−

VDD2

SGND2

VSS2(sub)

SW1

REL1

DIAGCUR

EN1

STAB

VSSD

PWM1

PWM2

EN2

DIAGTMP

REL2

SW2

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

TDA8929T

MGW149

Fig.2 Pin configuration.

2001 Dec 11 7



8 FUNCTIONAL DESCRIPTION

The combination of the TDA8926J and the TDA8929Tproduces a two-channel audio power amplifier systemusing the class-D technology (see Fig.4).

In the TDA8929T controller device the analog audio inputsignal is converted into a digital Pulse Width Modulation(PWM) signal. The digital power stage (TDA8926) is usedfor driving the low-pass filter and the loudspeaker load. Itperforms a level shift from the low-power digitalPWM signal, at logic levels, to a high-power PWM signalthat switches between the main supply lines.A second-order low-pass filter converts the PWM signalinto an analog audio signal across the loudspeaker.

For a description of the power stage see the specificationof the TDA8926.

The TDA8926 can be used for an output power of2 × 50 W. The TDA8927 should be used for a higheroutput power of 2 × 100 W.

8.1 Controller

The controller contains (for two audio channels) two PulseWidth Modulators (PWMs), two analog feedback loopsand two differential input stages. This chip also containscircuits common to both channels such as the oscillator, allreference sources, the mode functionality and a digitaltiming manager.

The pinning of the TDA8929T and the power stage devicesare designed to have very short and straight connectionsbetween the packages. For optimum performance theinterconnections between the packages must be as shortas possible.

Using this two-chip set an audio system with twoindependent amplifier channels with high output power,high efficiency (90%) for the system, low distortion and alow quiescent current is obtained. The amplifiers channelscan be connected in the following configurations:

• Mono Bridge-Tied Load (BTL) amplifier

• Stereo Single-Ended (SE) amplifier.

The amplifier system can be switched in three operatingmodes via the mode select pin:

• Standby: with a very low supply current

• Mute: the amplifiers are operational, but the audio signalat the output is suppressed

• On: amplifier fully operational with output signal.

For suppressing pop noise the amplifier will remainautomatically for approximately 220 ms in the mute modebefore switching to operating mode. In this time thecoupling capacitors at the input are fully charged.

Figure 3 shows an example of a switching circuit for drivingpin MODE.

MGW150

handbook, halfpage

R

R

MODE

SGND

mute/onstandby/mute

+5 V

Fig.3 Mode select switch circuitry.

2001D

ec11

8

Philips S

emiconductors

Prelim

inary specification

Controller class-D

audio amplifier

TD

A8929T

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hand

book

, ful

l pag

ewid

th

1

4IN1−PWM1

5IN1+

IN2+

IN2−

Vi(2)

Vi(1)

mute

mute

SGND

SGND

SGND1

SGND2

3

20

REL123

SW124

EN1

STAB

DIAGCUR

DIAGTMP

SW2

REL2

PWM2

21

22

19

15

13

EN2

REL1

SW1

EN1

SW2

REL2

EN216

14

17

6

11

8

9

7

2

Rfb

Rfb

INPUTSTAGE

INPUTSTAGE

TDA8929T

PWMMODULATOR

PWMMODULATOR

MODE

STABI

OSCILLATOR MANAGER

VSSA VDDA

VSS1 VDD1

12 10

VSSA VDDA

VSS2(sub) VSSDVDD2

VMODE

VSSA

MODE

OSCROSC

18

MGU387

CONTROLAND

HANDSHAKE

DRIVERHIGH

TDA8926J

DRIVERLOW

2

7

+25 V

−25 V

VSS1

VSS1

VSSA

VSS2

VSSD

VDDD

VDD2

VDDA

6

1

4

8 10

VDD2 VDD1

13 5

CONTROLAND

HANDSHAKE

DRIVERHIGH

DRIVERLOW

14

11

12

17

16

BOOT1

OUT1

OUT2

BOOT2

SGND(0 V)

STAB

POWERUP

DIAG

TEMPERATURE SENSORAND

CURRENT PROTECTION

9

3

15

Fig.4 Typical application schematic of the class-D system using TDA8929T and the TDA8926J.

2001 Dec 11 9



8.2 Pulse width modulation frequency

The output signal of the power stage is a PWM signal witha carrier frequency of approximately 300 kHz. Using asecond-order LC demodulation filter in the applicationresults in an analog audio signal across the loudspeaker.This switching frequency is fixed by an external resistorROSC connected between pin OSC and VSS. With theresistor value given in the application diagram, the carrierfrequency is typical 317 kHz. The carrier frequency can be

calculated using: [Hz]

If two or more class-D systems are used in the same audioapplication, it is advised to have all devices working at thesame switching frequency. This can be realized byconnecting all OSC pins together and feed them from anexternal oscillator. Using an external oscillator it isnecessary to force pin OSC to a DC-level above SGND forswitching from the internal to an external oscillator. In thiscase the internal oscillator is disabled and the PWM willswitch on the external frequency. The frequency range ofthe external oscillator must be in the range as specified inthe switching characteristics.

Application in a practical circuit:

• Internal oscillator: ROSC connected between pin OSCand VSS

• External oscillator: connect oscillator signal betweenpin OSC and pin SGND; delete ROSC.

8.3 Protections

The controller is provided with two diagnostic inputs. Oneor both pins can be connected to the diagnostic output ofone or more power stages.

8.3.1 DIAGNOSTIC TEMPERATURE

A LOW level on pin DIAGTMP will immediately force bothpins EN1 and EN2 to a LOW level. The power stage shutsdown and the temperature is expected to drop. Ifpin DIAGTMP goes HIGH, pins EN1 and EN2 willimmediately go HIGH and normal operation will bemaintained.

Temperature hysteresis, a delay before enabling thesystem again, is arranged in the power stage. Internallythere is a pull-up resistance to 5 V at the diagnostic inputof the controller. Because the diagnostic output of thepower stage is an open-drain output, diagnostic lines canbe connected together (wired-OR). It should be noted thatthe TDA8929T itself has no temperature protection.

8.3.2 DIAGNOSTIC CURRENT

This input is intended to protect against short-circuitsacross the loudspeaker load. In the event that the currentlimit in the power stage is exceeded, pin DIAGCUR mustbe pulled to a LOW level. A LOW level on the diagnosticcurrent input will immediately force the output pins EN1and EN2 to a LOW level. The power stage will shut downwithin less than 1 µs and the high current is switched off.In this state the dissipation is very low. Every 220 ms thecontroller will attempt to restart the system. If there is stilla short-circuit across the loudspeaker load, the system isswitched off again as soon as the maximum current isexceeded. The average dissipation will be low because ofthis low duty factor. The actual current limiting value is setby the power stage.

Depending on the type of power stage which is used,several values are possible:

• TDA8926TH: limit value can be externally adjusted witha resistor; maximum is 5 A

• TDA8927TH: limit value can be externally adjusted witha resistor; maximum is 7.5 A

• TDA8926J and TDA8926ST: limit value is fixed at 5 A

• TDA8927J and TDA8927ST: limit value is fixed at 7.5 A.

fosc9 109×ROSC

-------------------=

2001 Dec 11 10



8.3.3 START-UP SAFETY TEST

During the start-up sequence, when pin MODE is switchedfrom standby to mute, the condition at the output terminalsof the power stage are checked. These are the same linesas the feedback inputs of the controller. In the event of ashort-circuit of one of the output terminals to VDD or VSSthe start-up procedure is interrupted and the system waitsfor non-shorted outputs. Because the test is done beforeenabling the power stages, no large currents will flow in theevent of a short-circuit. This system protects againstshort-circuits at both sides of the output filter to both supplylines. When there is a short-circuit from the outputs of thepower stage to one of the supply lines, before thedemodulation filter, it will also be detected by the start-upsafety test. Practical use from this test feature can befound in detection of short-circuits on the printed-circuitboard.

Remark: this test is only operational prior to or during thestart-up sequence, and not during normal operating.

8.4 Differential audio inputs

For a high common mode rejection and a maximumflexibility of application, the audio inputs are fullydifferential. By connecting the inputs anti-parallel thephase of one of the channels is inverted, so that a load canbe connected between the two output filters. In this casethe system operates as a mono BTL amplifier (see Fig.5).

Also in the stereo single-ended configuration it isrecommended to connect the two differential inputs inanti-phase. This has advantages for the current handlingof the power supply at low signal frequencies.


MGW185

TDA8929TREL1

SW1

EN1

EN2

SW2

OUT1

SGND

OUT2REL2

IN1+

Vi

IN1−

IN2+

IN2−

CONTROLLER

POWERSTAGE

Fig.5 Mono BTL application.

2001 Dec 11 11



9 LIMITING VALUESIn accordance with the Absolute Maximum Rate System (IEC 60134).

Notes

1. Human Body Model (HBM); Rs = 1500 Ω and C = 100 pF.

2. Machine Model (MM); Rs = 10 Ω; C = 200 pF and L = 0.75 µH.

10 THERMAL CHARACTERISTICS

11 QUALITY SPECIFICATION

In accordance with “SNW-FQ611-part D” if this device is used as an audio amplifier.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VP supply voltage − ±30 V

VMODE(sw) mode select switch voltage referenced to SGND 0 5.5 V

Tstg storage temperature −55 +150 °CTamb ambient temperature −40 +85 °CTvj virtual junction temperature − 150 °CVes(HBM) electrostatic discharge

voltage (HBM)note 1

all pins with respect to VDD (class A) −500 +500 V

all pins with respect to VSS (class A1) −1000 +1000 V

all pins with respect to GND (class B) −2500 +2500 V

all pins with respect to each other(class B)

−2000 +2000 V

Ves(MM) electrostatic dischargevoltage (MM)

note 2

all pins with respect to VDD (class A) −100 +100 V

all pins with respect to VSS (class B) −100 +100 V

all pins with respect to GND (class B) −300 +300 V

all pins with respect to each other(class B)

−200 +200 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 65 K/W

2001 Dec 11 12



12 DC CHARACTERISTICSVP = ±25 V; Tamb = 25 °C; measured in Fig.10; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

VP supply voltage note 1 ±15 ±25 ±30 V

Iq(tot) total quiescent current − 20 30 mA

Istb standby current VMODE = 0 V − 30 100 µA

Offset

VOO output offset voltage in system on and mute − − 150 mV

∆VOO delta output offset voltage insystem

on ↔ mute − − 80 mV

Mode select input (pin MODE); see Figs 6, 7 and 8

VMODE input voltage note 2 0 − 5.5 V

IMODE input current VMODE = 5.5 V − − 1000 µA

Vth1+ positive threshold voltage 1 standby → mute;note 2

− 1.6 2.0 V

Vth1− negative threshold voltage 1 mute → standby;note 2

0.8 1.0 − V

VMODE(hys1) hysteresis voltage 1 (Vth1+) − (Vth1−) − 600 − mV

Vth2+ positive threshold voltage 2 mute → on;note 2

− 3.8 4.0 V

Vth2− negative threshold voltage 2 on → mute;note 2

3.0 3.2 − V

VMODE(hys2) hysteresis voltage 2 (Vth2+) − (Vth2−) − 600 − mV

Audio inputs (pins IN1+, IN1 −, IN2+ and IN2−)

VI DC input voltage note 2 − 0 − V

Internal stabilizer (pin STAB)

VO(STAB) stabilizer output voltage mute and on;note 3

11 13 15 V

ISTAB(max) maximum current on pin STAB mute and on 10 − − mA

Enable outputs (pins EN1 and EN2)

VOH HIGH-level output voltage referenced to VSS VSTAB − 1.6 VSTAB − 0.7 − V

VOL LOW-level output voltage referenced to VSS 0 − 0.8 V

Current diagnose input (pin DIAGCUR with internal pull-up resistance)

VIH HIGH-level input voltage no errors; note 3 − VSTAB − V

VIL LOW-level input voltage note 3 0 − 1.5 V

Rpu(int) internal pull-up resistance tointernal digital supply

− 12 − kΩ

Temperature diagnose input (pin DIAGTMP with internal pull-up resistance)

VIH HIGH-level input voltage no errors; note 3 4 5.5 V

VIL LOW-level input voltage note 3 0 − 1.5 V

2001 Dec 11 13



Notes

1. The circuit is DC adjusted at VP = ±15 to ±30 V.

2. Referenced to SGND (0 V).

3. Referenced to VSS.

13 AC CHARACTERISTICS

Rpu(int) internal pull-up resistance tointernal digital supply

− 12 − kΩ

Switch outputs (pins SW1 and SW2)

VOH HIGH-level output voltage note 3 VSTAB − 1.6 VSTAB − 0.7 − V

VOL LOW-level output voltage note 3 0 − 0.8 V

Control inputs (pins REL1 and REL2)

VIH HIGH-level input voltage note 3 10 − VSTAB V

VIL LOW-level input voltage note 3 0 − 2 V


Stereo single-ended application; note 1

THD total harmonic distortion Po = 1 W; note 2

fi = 1 kHz − 0.01 0.05 %

fi = 10 kHz − 0.1 − %


SVRR supply voltage ripple rejection on; fi = 100 Hz; note 3 − 55 − dB

on; fi = 1 kHz; note 3 40 50 − dB

mute; fi = 100 Hz; note 3 − 55 − dB

standby; fi = 100 Hz; note 3 − 80 − dB

Zi input impedance 45 68 − kΩVn(o) noise output voltage on; Rs = 0 Ω; B = 22 Hz to 22 kHz − 220 400 µV

on; Rs = 10 kΩ; B = 22 Hz to 22 kHz − 230 − µV

mute; note 4 − 220 − µV

αcs channel separation Po = 10 W; Rs = 0 Ω − 70 − dB

∆Gv channel unbalance − − 1 dB

Vo output signal mute; Vi = Vi(max) = 1 V (RMS) − − 400 µV

CMRR common mode rejection ratio Vi = 1 V (RMS) − 75 − dB

Mono BTL application; note 5

THD total harmonic distortion Po = 1 W; note 2

fi = 1 kHz − 0.01 0.05 %

fi = 10 kHz − 0.1 − %



2001 Dec 11 14



Notes

1. VP = ±25 V; fi = 1 kHz; Tamb = 25 °C; measured in Fig.10; unless otherwise specified.

2. THD is measured in a bandwidth of 22 Hz to 22 kHz. When distortion is measured using a low-order low-pass filtera significantly higher value will be found, due to the switching frequency outside the audio band.

3. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω.

4. B = 22 Hz to 22 kHz and independent of Rs.

5. VP = ±25 V; fi = 1 kHz; Tamb = 25 °C; measured in reference design in Fig.12; unless otherwise specified.

SVRR supply voltage ripple rejection on; fi = 100 Hz; note 3 − 49 − dB

on; fi = 1 kHz; note 3 36 44 − dB

mute; fi = 100 Hz; note 3 − 49 − dB

standby; fi = 100 Hz; note 3 − 80 − dB

Zi input impedance 23 34 − kΩVn(o) noise output voltage on; Rs = 0 Ω; B = 22 Hz to 22 kHz − 280 500 µV

on; Rs = 10 kΩ; B = 22 Hz to 22 kHz − 300 − µV

mute; note 4 − 280 − µV

Vo output signal mute; Vi = Vi(max) = 1 V (RMS) − − 500 µV

CMRR common mode rejection ratio Vi = 1 V (RMS) − 75 − dB



VMODE(hys1) VMODE(hys2)

VMODEVth1− Vth1+ Vth2− Vth2+

MGW334

standby

mute

on

Fig.6 Mode pin selection.

2001 Dec 11 15




MGW152

on

mute

switching

audio

standby

>110 ms110 ms

0 V (SGND)

2 V

4 V

VMODE

VEN

VSTAB

VSS

Fig.7 Mode pin timing from standby to on via mute.

When switching from standby to mute there is a delay of 110 ms before the output starts switching. The audio signal isavailable after the mode pin has been set to on, but not earlier than 220 ms after switching to mute.


MGW151

on

switching

audio

standby

110 ms 110 ms

0 V (SGND)

4 V

VMODE

VEN

VSTAB

VSS

Fig.8 Mode pin timing from standby to on.

When switching from standby to on there is a delay of 110 ms before the output starts switching.After a second delay of 110 ms the audio signal is available.

2001 Dec 11 16



14 SWITCHING CHARACTERISTICSVP = ±25 V; Tamb = 25 °C; measured in Fig.10; unless otherwise specified.

Notes

1. Frequency set with ROSC, according to the formula in the functional description.

2. For tracking the external oscillator has to switch around SGND + 2.5 V with a minimum voltage of VOSC(ext).

14.1 Minimum pulse width

The minimum obtainable pulse width of the PWM output signal of a class-D system, sets the maximum output voltageswing after the demodulation filter and also the maximum output power. Delays in the power stages are the main causefor the minimum pulse width being not equal to zero. The TDA8926 and TDA8927 power stages have a minimum pulsewidth of tW(min) = 220 ns (typical). Using the TDA8929T controller, the effective minimum pulse is reduced by a factor oftwo during clipping. For the calculation of the maximum output power at clipping the effective minimum pulse width duringclipping is 0.5tW(min).

For the practical useable minimum and maximum duty factor (δ) which determines the maximum output power:

× 100% < δ < × 100%

Using the typical values of the TDA8926 and TDA8927 power stages:

3.5% < δ < 96.5%.


Switching frequency

fosc oscillator frequency ROSC = 30.0 kΩ 309 317 329 kHz

ROSC = 27 kΩ;see Fig.12

− 360 − kHz

fosc(r) oscillator frequency range note 1 210 − 600 kHz

VOSC maximum voltage at pin OSC frequency tracking − − SGND + 12 V

VOSC(trip) trip level at pin OSC for tracking frequency tracking − SGND + 2.5 − V

ftrack frequency range for tracking frequency tracking 200 − 600 kHz

VOSC(ext) voltage at pin OSC for tracking note 2 − 5 − V

tW(min) fosc×2

------------------------------- 1tW(min) fosc×

2-------------------------------–

2001 Dec 11 17



15 TEST AND APPLICATION INFORMATION

15.1 Test circuit

The test diagram in Fig.10 can be used for stand alonetesting of the controller. Audio and mode input pins areconfigured as in the application. For the simulation of aswitching output power stage a simple level shifter can beused. It converts the digital PWM signal from the controller(switching between VSS and VSS + 12 V level) to aPWM signal switching between VDD and VSS.

A proposal for a simple level shifting circuit is givenin Fig.9.

The low-pass filter performs the demodulation, so that theaudio signal can be measured with an audio analyzer. Formeasuring low distortion values, the speed of the levelshifter is important. Special care has to be taken at asufficient supply decoupling and output waveforms withoutringing.

The handshake with the power stage is simulated by adirect connection of the release inputs (REL1 and REL2)with the switch outputs (SW1 and SW2) of the controller.The enable outputs (EN1 and EN2) for waking-up thepower stage are not used here, only the output level andtiming are measured.


MGW154

10 kΩ

1.33 kΩ

2 kΩ

74LV14

20 kΩ

10 Ω

33 Ω

42 Ω10 nF

PWM

VDD

VSS

switch0/12 V

VSS

+5 V

BST82

PHC2300

10 Ω

Fig.9 Level shifter.

2001D

ec11

18

Philips S

emiconductors

Prelim

inary specification

Controller class-D

audio amplifier

TD

A8929T


dbook, full pagewidth

MGW153

30 kΩ

47 µF

100 nF

STABILIZER

SGND

SGND

SGND

SGND

100 nF

audioanalyzer

audio left

audio right

220 nF

220 nF

100 nF

SGND

SGND

4

1 3

5

2

7

6

11

8

9

12 10

17

14

13

16

22

15

19

23

24

21

0/12 V −30 V/+30 V

20Rfb

Rfb

mute

mute

mute

V/I

V/I

SGND

TDA8929TSGND

OSCILLATOR

WINDOWCOMPARATOR

WINDOWCOMPARATOR

MODE

MANAGER

220 nF

220 nF

18

VSS1

SGND1

VDD1

IN1−

IN1+

MODE

VMODE

VSS

Vi(L)

Vi(R)

OSC

IN2+

IN2−

VDD2

VDD

SGND2

VSS2(sub)

VSS

47 µF

100 nFVDD

VDD

VSS

VSS

SW1

REL1

LEVEL SHIFTER 30 kHzLOW-PASS

DIAGCUR

EN1

STAB

VSSD

VSS

PWM1

PWM2

PWM

EN2

DIAGTMP

REL2

SW2

SGND

Vp

VSS

VDD

Vp

V

V

V

V

SGND

audioanalyzer0/12 V −30 V/+30 V

VDD

VSS

VSS

LEVEL SHIFTER 30 kHzLOW-PASS

PWM

V

Fig.10 Test diagram.

2001 Dec 11 19



15.2 BTL application

When using the system in a mono BTL application (formore output power), the inputs of both channels must beconnected in parallel. The phase of one the inputs must beinverted (see Fig.5). In principle the loudspeaker can beconnected between the outputs of the two single-endeddemodulation filters. For improving the common modebehavior of the filter, the configuration in Fig.12 is advised.

15.3 Mode pin

For correct operation the switching voltage on pin MODEshould be de-bounced. If this pin is driven by a mechanicalswitch an appropriate de-bouncing low-pass filter shouldbe used. If pin MODE is driven by an electronic circuit ormicrocontroller then it should remain, for at least 100 ms,at the mute voltage level (Vth1+) before switching back tothe standby voltage level.

15.4 External clock

Figure 11 shows an external clock oscillator circuit.

15.5 Reference designs

The reference design for a two-chip class-D audioamplifier for TDA8926J or TDA8927J and TDA8929T isshown in Fig.12. The Printed-Circuit Board (PCB) layout isshown in Fig.13. The bill of materials is given in Table 1.

The reference design for a two-chip class-D audioamplifier for TDA8926TH or TDA8927TH and TDA8929Tis shown in Fig.14. The PCB layout is shown in Fig.15.


MGW155

R195 kΩ

9.1 kΩ

R1

39 kΩ

R20

mode select

external clock

S1on MODE

OSC

muteoff

C44220 nF

D15V6

C3120 pF1

HEF4047B

J1

14

2

GND

13

3 12

4 11

5 10

6 9

7 8

VDDA

6

TDA8929T

7

Fig.11 External oscillator circuit.

2001D

ec11

20

Philips S

emiconductors

Prelim

inary specification

Controller class-D

audio amplifier

TD

A8929T


hand

book

, ful

l pag

ewid

thMLD633

39 kΩ

R1939 kΩ

R710 kΩ

220 nFC2R20

1 kΩ

R10

Sumida 33 µHCDRH127-330

L4


L2

GND

220 nF

C44220 nF

C1

3

6 17PWM2

5

4

8

9

10 12

15

n.c.

1

1 nF

C29

input 2input 1

J5

J6

D1(5.6 V)

D2(7.5 V)

IN1+

IN1−

GND

2

11

SGND1

SGND2

S1

VSSA

VSS1VSS2

VDDA

VDD2VDD1

GND

1

2

1

2

1

2

QGND

QGND

QGND

QGND

OUT1−

OUT1+

OUT1+

OUT2−

OUT2−

OUT2+BOOT2

BOOT1

OUT1

OUT2

VDDDVDD1

VDD2

VSS2

VSS1

VDDD

VSSD

VSSA VSSD

27 kΩ

R17

220 nF

C3

OSC

POWERUP

VSSA

220 nF

C5

MODE

VDDA

R24200 kΩ

VDDD

onmute

off

U2

TDA8929T

CONTROLLERC22

330 pF

C27470 nF

C4220 nF C7

220 nF

C14470 nF

C181 nF

C191 nF

C201 nF

C211 nF

C16470 nF

C6220 nF

C915 nF

C815 nF

C43180 pF

IN2+

IN2−

R6 10 kΩ

C26470 nF

R410 kΩ

1 nF

C28

C24470 nF

R5 10 kΩ

J3J1

QGND QGND

inputs

outputs

power supply

mode select

J4

J2

VSS

C25470 nF

C23330 pF

R115.6 Ω

C10560 pF

VSSD

VDDD VSSD

R125.6 Ω

R135.6 Ω

R145.6 Ω

C11560 pF

C12560 pF

C13560 pF

R229.1 kΩ

VSSD

VSSA

VDDA

VDDD

C311 nF

C301 nF

C33220 nF

C351500 µF(35 V)

R2110 kΩ

C32220 nF

C341500 µF(35 V)

C38220 nF

C39220 nF

C4147 µF(35 V)

C36220 nF

C37220 nF

C4047 µF(35 V)

GND

QGND

QGND

beadL6

L5bead

L7bead

GND

VDD

VSS

+25 V

−25 V

1

2

3

13SW2

14REL2

16EN2

SW2

REL2

EN2

21

PWM1

23SW1

24

15

9

3

U1

TDA8926Jor

TDA8927J

POWER STAGE

17

16

14

4

2

1

8

10

13

5

6

7

11

12

REL1

20

EN1

SW1

REL1

EN1

19STAB

STAB18

VSSD

22DIAGCUR

DIAG

R1624 Ω

R1524 Ω

4 or 8 ΩSE

4 or 8 ΩSE

8 ΩBTL

C17220 nF

C15220 nF

Fig.12 Two-chip class-D audio amplifier application diagram for TDA8926J or TDA8927J and TDA8929T.

R21 and R22 are only necessary in BTL applications with asymmetrical supply.

BTL: remove R6, R7, C23, C26 and C27 and close J5 and J6.

C22 and C23 influence the low-pass frequency response and should be tuned with the real load (loudspeaker).

Inputs floating or inputs referenced to QGND (close J1 and J4) or referenced to VSS (close J2 and J3) for an input signal ground reference.

2001D

ec11

21

Philips S

emiconductors

Prelim

inary specification

Controller class-D

audio amplifier

TD

A8929T



MLD634

C24

D1

TDA8926J/27J & TDA8929T

Copper top, top view

Copper bottom, top view

Silk screen top, top view

Silk screen bottom, top view

D2

L7

L5

In1

GN

D

In2

Out1 Out2

state of D artVersion 21 03-2001

U1

C25C34

C35

C40

C26

C27

L6

ONMUTEOFF

C41

C16

C14

S1

R20

R1

R21L2

L4

R22

C38

U2

C39

C36

R24

R5

R4 R6

R7

C2

C31C30C18

C19

C20

C21

C1

C9

C8

J4

J5

J6

J1J3J2

R19

C13

C33

C32

C11

C29C28

R14

R12

C3

C43R10

C12

C17

R16

C15

R15

R13

R11C10

C5

C37

C22C23

C44

VD

D

VS

S

In1

Out1 Out2

GND

In2

QGND

VDD VSS

C7

C4

C6

Fig.13 Printed-circuit board layout for TDA8926J or TDA8927J and TDA8929T.

2001D

ec11

22

Philips S

emiconductors

Prelim

inary specification

Controller class-D

audio amplifier

TD

A8929T


hand

book

, ful

l pag

ewid

th

MGW232

39 kΩ

R130 kΩ

R710 kΩ

100 nFC12R2

1 kΩ

R8

5.6 Ω

R11


L4


L2L1

bead

L3bead

GND

100 nF

C1220 nF

C11

3

6 17PWM2

5

4

8

9

10 12

15

n.c.

1

1 nF

C10

input 2input 1

J5

J6

D1(5.6 V)

IN1+

IN1−

GND

2

11

SGND1

SGND2

S1

VSSA

VSSD

VSS1VSS2

VDDA

VDD2VDD1

GND

1

2

1

2

1

2

QGND

QGND

QGND

QGND

OUT1−

OUT1+

OUT1+

OUT2−

OUT2−

OUT2+BOOT2

BOOT1

OUT1

OUT2

VDDDVDD1

VDD2

VSS2

VSS1

VDDD

VSSD

VSSAVSSD

27 kΩ

R37

220 nF

C2

OSC

POWERUP

VSSA

100 nF

C14

MODE

VDDA

R18200 kΩ

D2(7.5 V)

VDDD

onmute

off

U2

TDA8929T

CONTROLLERC3

330 pF

C81 µF

C13100 nF C27

100 nF

C36470 nF

C401 nF

C411 nF

C421 nF

C431 nF

C37470 nF

C28100nF

C3315 nF

C2615 nF

C15180 pF

IN2+

IN2−

R6 10 kΩ

C71 µF

R510 kΩ

1 nF

C9

C61 µF

R4 10 kΩ

J3J1

QGND QGND

inputs

outputs

power supply

mode select

J4

J2

VSS

C51 µF

C4330 pF

R125.6 Ω

C24560 pF

VSSD

VDDD VSSD

R135.6 Ω

R145.6 Ω

R155.6 Ω

C25560 pF

C34560 pF

C35560 pF

R109.1 kΩ

VSSD

VSSA

VDDA

VDDD

C171 nF

C161 nF

R910 kΩ

C20100 nF

C21100 nF

C2347 µF(35 V)

C18100 nF

C19100 nF

C2247 µF(35 V)

GND

QGND

QGND

QGND

beadL6

L5bead

L7bead

GND

C30100 nF

C321500 µF(35 V)

C29100 nF

C311500 µF(35 V)

VDD

VSS

+25 V

−25 V

1

2

3

13SW2

14REL2

16EN2

SW2

REL2

EN2

21

PWM1

23SW1

24

14

6

23

U1

TDA8926THor

TDA8927TH

POWER STAGE

16

15

13

24

22

21

5

8

11

2

3

4

9

10

REL1

20

EN1

SW1

REL1

EN1

19STAB

STAB

19VSS(sub)VSSD

17LIMVSSD

7STAB18

22DIAGCUR DIAG

R175.6 Ω

R165.6 Ω

4 or 8 ΩSE

4 or 8 ΩSE

8 ΩBTL

C39220 nF

C38220 nF

1, 12, 18, 20

n.c.

Fig.14 Two-chip class-D audio amplifier application diagram for TDA8926TH or TDA8927TH and TDA8929T.

R9 and R10 are only necessary in BTL applications with asymmetrical supply.

BTL: remove R6, R7, C4, C7 and C8 and close J5 and J6.

Demodulation coils L2 and L4 should be matched in BTL.

Inputs floating or inputs referenced to QGND (close J1 and J4) or referenced to VSS (close J2 and J3).

2001D

ec11

23

Philips S

emiconductors

Prelim

inary specification

Controller class-D

audio amplifier

TD

A8929T


dbook, full pagewidth

MGW147

TDA8926TH/27THTDA8929T

Copper top, top view

Copper bottom, top view

Silk screen top, top view

Silk screen bottom, top view

In1In2

State of D art

ONMUOFF

S1

L4

L3C31

C32

C22

D1

C23

C37

C36L6 Version 2CTH1

L5

L1

C29

C2

C9C10

C8C7

R4R5

R7R6

R3

C30

C35

C1 C15

C12

C21J6J5

C19

C13

L7

C3C4

C5C6

C18

C11

R11

C20R8

R1 R2

C14

R12

R14

R13

R17 R16 R10R9C39

C43 J4

J2J3 J1

QGNDC42 C41 C40 C16 C17

C38

R15

C25

C24

C34

C26

C33

Jan 2001

U1 U2

C27

C28

L5

GND

Out1 Out2

VDD VSS

Fig.15 Printed-circuit board layout for TDA8926TH or TDA8927TH and TDA8929T.

2001 Dec 11 24



15.6 Reference design bill of material

Table 1 Two-chip class-D audio amplifier PCB (Version 2.1; 03-2001) for TDA8926J or TDA8927J and TDA8929T(see Figs 12 and 13)

COMPONENT DESCRIPTION VALUE COMMENTS

In1 and In2 Cinch input connectors 2 × Farnell: 152-396

Out1, Out2, VDD,GND and VSS

supply/output connectors 2 × Augat 5KEV-02;1 × Augat 5KEV-03

S1 on/mute/off switch PCB switch Knitter ATE 1 E M-O-M

U1 power stage IC TDA8926J/27J DBS17P package

U2 controller IC TDA8929T SO24 package

L2 and L4 demodulation filter coils 33 µH 2 × Sumida CDRH127-330

L5, L6 and L7 power supply ferrite beads 3 × Murata BL01RN1-A62

C1 and C2 supply decoupling capacitors forVDD to VSS of the controller

220 nF/63 V 2 × SMD1206

C3 clock decoupling capacitor 220 nF/63 V SMD1206

C4 12 V decoupling capacitor of thecontroller

220 nF/63 V SMD1206

C5 12 V decoupling capacitor of the powerstage

220 nF/63 V SMD1206

C6 and C7 supply decoupling capacitors forVDD to VSS of the power stage

220 nF/63 V SMD1206

C8 and C9 bootstrap capacitors 15 nF/50 V 2 × SMD0805

C10, C11,C12 and C13

snubber capacitors 560 pF/100 V 4 × SMD0805

C14 and C16 demodulation filter capacitors 470 nF/63 V 2 × MKT

C15 and C17 resonance suppress capacitors 220 nF/63 V 2 × SMD1206

C18, C19,C20 and C21

common mode HF coupling capacitors 1 nF/50 V 4 × SMD0805

C22 and C23 input filter capacitors 330 pF/50 V 2 × SMD1206

C24, C25,C26 and C27

input capacitors 470 nF/63 V 4 × MKT

C28, C29,C30 and C31

common mode HF coupling capacitors 1 nF/50 V 2 × SMD0805

C32 and C33 power supply decoupling capacitors 220 nF/63 V 2 × SMD1206

C34 and C35 power supply electrolytic capacitors 1500 µF/35 V 2 × Rubycon ZL very low ESR (largeswitching currents)

C36, C37,C38 and C39

analog supply decoupling capacitors 220 nF/63 V 4 × SMD1206

C40 and C41 analog supply electrolytic capacitors 47 µF/35 V 2 × Rubycon ZA low ESR

C43 diagnostic capacitor 180 pF/50 V SMD1206

C44 mode capacitor 220 nF/63 V SMD1206

D1 5.6 V zener diode BZX79C5V6 DO-35

D2 7.5 V zener diode BZX79C7V5 DO-35

R1 clock adjustment resistor 27 kΩ SMD1206

2001 Dec 11 25



R4, R5,R6 and R7

input resistors 10 kΩ 4 × SMD1206

R10 diagnostic resistor 1 kΩ SMD1206

R11, R12,R13 and R14

snubber resistors 5.6 Ω; >0.25 W 4 × SMD1206

R15 and R16 resonance suppression resistors 24 Ω 2 × SMD1206

R19 mode select resistor 39 kΩ SMD1206

R20 mute select resistor 39 kΩ SMD1206

R21 resistor needed when using anasymmetrical supply

10 kΩ SMD1206

R22 resistor needed when using anasymmetrical supply

9.1 kΩ SMD1206

R24 bias resistor for powering-up the powerstage

200 kΩ SMD1206

COMPONENT DESCRIPTION VALUE COMMENTS

15.7 Curves measured in reference design

handbook, halfpage102

10

1

10−1

10−3

10−2

MLD627

10−2 10−1 1Po (W)

THD+N(%)

10 102 103

(1)

(2)

(3)

Fig.16 THD + N as a function of output power.

2 × 8 Ω SE; VP = ±25 V:

(1) 10 kHz.

(2) 1 kHz.

(3) 100 Hz.

handbook, halfpage

MLD628

10 102 103 104 105

102

10

1

10−1

10−3

10−2

fi (Hz)

THD+N(%)

(1)

(2)

Fig.17 THD + N as a function of input frequency.

2 × 8 Ω SE; VP = ±25 V:

(1) Po = 10 W.

(2) Po = 1 W.

2001 Dec 11 26




10

1

10−1

10−3

10−2

MLD629

10−2 10−1 1Po (W)

THD+N(%)

10 102 103

(1)

(2)

(3)


2 × 4 Ω SE; VP = ±25 V:

(1) 10 kHz.

(2) 1 kHz.

(3) 100 Hz.

handbook, halfpage

MLD630

10 102 103 104 105

102

10

1

10−1

10−3

10−2

fi (Hz)

THD+N(%)

(1)

(2)


2 × 4 Ω SE; VP = ±25 V:

(1) Po = 10 W.

(2) Po = 1 W.


10

1

10−1

10−3

10−2

MLD631

10−2 10−1 1Po (W)

THD+N(%)

10 102 103

(1)

(2)

(3)


1 × 8 Ω BTL; VP = ±25 V:

(1) 10 kHz.

(2) 1 kHz.

(3) 100 Hz.

handbook, halfpage

MLD632

10 102 103 104 105

102

10

1

10−1

10−3

10−2

fi (Hz)

THD+N(%)

(1)

(2)


1 × 8 Ω BTL; VP = ±25 V:

(1) Po = 10 W.

(2) Po = 1 W.

2001 Dec 11 27



handbook, halfpage

0

25

5

10

15

20

MLD609

10−2 10−1 1

(2)

Po (W)

P(W)

10 102 103

(1)

(3)

Fig.22 Power dissipation as a function of outputpower.

VP = ±25 V; fi = 1 kHz:

(1) 2 × 4 Ω SE.

(2) 1 × 8 Ω BTL.

(3) 2 × 8 Ω SE.

handbook, halfpage

0

(3) (1)

(2)

150

100

0

20

40

60

80

30

η(%)

Po (W)60 90 120

MLD610

Fig.23 Efficiency as a function of output power.

VP = ±25 V; fi = 1 kHz:

(1) 2 × 4 Ω SE.

(2) 1 × 8 Ω BTL.

(3) 2 × 8 Ω SE.

handbook, halfpage

10

(3)

(4)

(1)

(2)

35

200

0

40

80

120

160

15

Po(W)

VP (V)20 25 30

MLD611

Fig.24 Output power as a function of supplyvoltage.

THD + N = 0.5%; fi = 1 kHz:

(1) 1 × 4 Ω BTL.

(2) 1 × 8 Ω BTL.

(3) 2 × 4 Ω SE.

(4) 2 × 8 Ω SE.

handbook, halfpage

10

(3)

(4)

(1)

(2)

35

200

0

40

80

120

160

15

Po(W)

VP (V)20 25 30

MLD612

Fig.25 Output power as a function of supplyvoltage.

THD + N = 10%; fi = 1 kHz:

(1) 1 × 4 Ω BTL.

(2) 1 × 8 Ω BTL.

(3) 2 × 4 Ω SE.

(4) 2 × 8 Ω SE.

2001 Dec 11 28



handbook, halfpage

−100

0

−80

−60

−40

−20

MLD613

10210fi (Hz)

αcs(dB)

103 104 105

(1)

(2)

Fig.26 Channel separation as a function of inputfrequency.

2 × 8 Ω SE; VP = ±25 V:

(1) Po = 10 W.

(2) Po = 1 W.

handbook, halfpage

−100

0

−80

−60

−40

−20

MLD614

10210fi (Hz)

αcs(dB)

103 104 105

(1)

(2)

Fig.27 Channel separation as a function of inputfrequency.

2 × 4 Ω SE; VP = ±25 V:

(1) Po = 10 W.

(2) Po = 1 W.

handbook, halfpage

20

45

25

30

35

40

MLD615

10210fi (Hz)

G(dB)

103 104 105

(1)

(2)

(3)

Fig.28 Gain as a function of input frequency.

VP = ±25 V; Vi = 100 mV;Rs = 10 kΩ/Ci = 330 pF:

(1) 1 × 8 Ω BTL.

(2) 2 × 8 Ω SE.

(3) 2 × 4 Ω SE.

handbook, halfpage

20

45

25

30

35

40

MLD616

10210fi (Hz)

G(dB)

103 104 105

(1)

(2)

(3)

Fig.29 Gain as a function of input frequency.

VP = ±25 V; Vi = 100 mV;Rs = 0 Ω:

(1) 1 × 8 Ω BTL.

(2) 2 × 8 Ω SE.

(3) 2 × 4 Ω SE.

2001 Dec 11 29



handbook, halfpage

−100

0

−80

−60

−40

−20

MLD617

10210fi (Hz)

SVRR(dB)

103 104 105

(1)

(2)

(3)

Fig.30 SVRR as a function of input frequency.

VP = ±25 V; Vripple = 2 V (p-p) with respect to GND:

(1) Both supply lines in anti-phase.

(2) Both supply lines in phase.

(3) One supply line rippled.

handbook, halfpage

0 5

0

−100

−80

−60

−40

−20

1

(1)

(3)

SVRR(dB)

Vripple (V)2 3 4

MLD618

(2)

Fig.31 SVRR as a function of Vripple (p-p).

VP = ±25 V; Vripple with respect to GND:

(1) fripple = 1 kHz.

(2) fripple = 100 Hz.

(3) fripple = 10 Hz.

handbook, halfpage

0 10 20 30VP (V)

Iq(mA)

37.5

100

0

20

40

60

80

MLD619

Fig.32 Quiescent current as a function of supplyvoltage.

RL = open.

handbook, halfpage

0 10 20 30VP (V)

fclk(kHz)

40

380

340

348

356

364

372

MLD620

Fig.33 Clock frequency as a function of supplyvoltage.

RL = open.

2001 Dec 11 30



handbook, halfpage

0

5

1

2

3

4

MLD621

10−110−2Po (W)

Vripple(V)

1 10 102

(1)

(2)

Fig.34 Supply voltage ripple as a function of outputpower.

VP = ±25 V; 1500 µF per supply line; fi = 10 Hz:

(1) 1 × 4 Ω SE.

(2) 1 × 8 Ω SE.

handbook, halfpage5

010 104

MLD622

102 103fi (Hz)

SVRR(%)

1

2

3

4

(1)

(2)

Fig.35 SVRR as a function of input frequency.

VP = ±25 V; 1500 µF per supply line:

(1) Po = 30 W into 1 × 4 Ω SE.

(2) Po = 15 W into 1 × 8 Ω SE.

handbook, halfpage

600100

(3)

fclk (kHz)

THD+N(%)

200 300 400 500

10

1

10−1

10−2

10−3

MLD623

(1)

(2)

Fig.36 THD + N as a function of clock frequency.

VP = ±25 V; Po = 1 W in 2 × 8 Ω:

(1) 10 kHz.

(2) 1 kHz.

(3) 100 Hz.

handbook, halfpage

100 600

50

0

10

20

30

40

200

Po(W)

fclk (kHz)300 400 500

MLD624

Fig.37 Output power as a function of clockfrequency.

VP = ±25 V; RL = 2 × 8 Ω; fi = 1 kHz; THD + N = 10%.

2001 Dec 11 31



handbook, halfpage

100 600

150

0

30

60

90

120

200

Iq(mA)

fclk (kHz)300 400 500

MLD625

Fig.38 Quiescent current as a function of clockfrequency.

VP = ±25 V; RL = open.

handbook, halfpage

100 600

1000

0

200

400

600

800

200

Vr(PWM)(mV)

fclk (kHz)300 400 500

MLD626

Fig.39 PWM residual voltage as a function of clockfrequency.

VP = ±25 V; RL = 2 × 8 Ω.

2001 Dec 11 32



16 PACKAGE OUTLINE

UNITA

max. A1 A2 A3 bp c D (1) E (1) (1)e HE L Lp Q Zywv θ

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm

inches

2.65 0.300.10

2.452.25

0.490.36

0.320.23

15.615.2

7.67.4 1.27

10.6510.00

1.11.0

0.90.4 8

0

o

o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.10.4

SOT137-1

X

12

24

w M

θ

AA1

A2

bp

D

HE

Lp

Q

detail X

E

Z

c

L

v M A

13

(A )3

A

y

0.25

075E05 MS-013

pin 1 index

0.10 0.0120.004

0.0960.089

0.0190.014

0.0130.009

0.610.60

0.300.29 0.050

1.4

0.0550.4190.394

0.0430.039

0.0350.0160.01

0.25

0.01 0.0040.0430.0160.01

e

1

0 5 10 mm

scale

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

97-05-2299-12-27

2001 Dec 11 33



17 SOLDERING

17.1 Introduction to soldering surface mountpackages

This text gives a very brief insight to a complex technology.A more in-depth account of soldering ICs can be found inour “Data Handbook IC26; Integrated Circuit Packages”(document order number 9398 652 90011).

There is no soldering method that is ideal for all surfacemount IC packages. Wave soldering can still be used forcertain surface mount ICs, but it is not suitable for fine pitchSMDs. In these situations reflow soldering isrecommended.

17.2 Reflow soldering

Reflow soldering requires solder paste (a suspension offine solder particles, flux and binding agent) to be appliedto the printed-circuit board by screen printing, stencilling orpressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,convection or convection/infrared heating in a conveyortype oven. Throughput times (preheating, soldering andcooling) vary between 100 and 200 seconds dependingon heating method.

Typical reflow peak temperatures range from215 to 250 °C. The top-surface temperature of thepackages should preferable be kept below 220 °C forthick/large packages, and below 235 °C for small/thinpackages.

17.3 Wave soldering

Conventional single wave soldering is not recommendedfor surface mount devices (SMDs) or printed-circuit boardswith a high component density, as solder bridging andnon-wetting can present major problems.

To overcome these problems the double-wave solderingmethod was specifically developed.

If wave soldering is used the following conditions must beobserved for optimal results:

• Use a double-wave soldering method comprising aturbulent wave with high upward pressure followed by asmooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprintlongitudinal axis is preferred to be parallel to thetransport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axismust be parallel to the transport direction of theprinted-circuit board.

The footprint must incorporate solder thieves at thedownstream end.

• For packages with leads on four sides, the footprint mustbe placed at a 45° angle to the transport direction of theprinted-circuit board. The footprint must incorporatesolder thieves downstream and at the side corners.

During placement and before soldering, the package mustbe fixed with a droplet of adhesive. The adhesive can beapplied by screen printing, pin transfer or syringedispensing. The package can be soldered after theadhesive is cured.

Typical dwell time is 4 seconds at 250 °C.A mildly-activated flux will eliminate the need for removalof corrosive residues in most applications.

17.4 Manual soldering

Fix the component by first soldering twodiagonally-opposite end leads. Use a low voltage (24 V orless) soldering iron applied to the flat part of the lead.Contact time must be limited to 10 seconds at up to300 °C.

When using a dedicated tool, all other leads can besoldered in one operation within 2 to 5 seconds between270 and 320 °C.

2001 Dec 11 34



17.5 Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximumtemperature (with respect to time) and body size of the package, there is a risk that internal or external packagecracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to theDrypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it isdefinitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGESOLDERING METHOD

WAVE REFLOW (1)

BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable(2) suitable

PLCC(3), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SSOP, TSSOP, VSO not recommended(5) suitable

2001 Dec 11 35



18 DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet waspublished. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DATA SHEET STATUS (1) PRODUCTSTATUS(2) DEFINITIONS

Objective data Development This data sheet contains data from the objective specification for productdevelopment. Philips Semiconductors reserves the right to change thespecification in any manner without notice.

Preliminary data Qualification This data sheet contains data from the preliminary specification.Supplementary data will be published at a later date. PhilipsSemiconductors reserves the right to change the specification withoutnotice, in order to improve the design and supply the best possibleproduct.

Product data Production This data sheet contains data from the product specification. PhilipsSemiconductors reserves the right to make changes at any time in orderto improve the design, manufacturing and supply. Changes will becommunicated according to the Customer Product/Process ChangeNotification (CPCN) procedure SNW-SQ-650A.

19 DEFINITIONS

Short-form specification The data in a short-formspecification is extracted from a full data sheet with thesame type number and title. For detailed information seethe relevant data sheet or data handbook.

Limiting values definition Limiting values given are inaccordance with the Absolute Maximum Rating System(IEC 60134). Stress above one or more of the limitingvalues may cause permanent damage to the device.These are stress ratings only and operation of the deviceat these or at any other conditions above those given in theCharacteristics sections of the specification is not implied.Exposure to limiting values for extended periods mayaffect device reliability.

Application information Applications that aredescribed herein for any of these products are forillustrative purposes only. Philips Semiconductors makeno representation or warranty that such applications will besuitable for the specified use without further testing ormodification.

20 DISCLAIMERS

Life support applications These products are notdesigned for use in life support appliances, devices, orsystems where malfunction of these products canreasonably be expected to result in personal injury. PhilipsSemiconductors customers using or selling these productsfor use in such applications do so at their own risk andagree to fully indemnify Philips Semiconductors for anydamages resulting from such application.

Right to make changes Philips Semiconductorsreserves the right to make changes, without notice, in theproducts, including circuits, standard cells, and/orsoftware, described or contained herein in order toimprove design and/or performance. PhilipsSemiconductors assumes no responsibility or liability forthe use of any of these products, conveys no licence or titleunder any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties thatthese products are free from patent, copyright, or maskwork right infringement, unless otherwise specified.

© Koninklijke Philips Electronics N.V. 2001 SCA73All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any licenseunder patent- or other industrial or intellectual property rights.

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com . Fax: +31 40 27 24825For sales offices addresses send e-mail to: [email protected] .

Printed in The Netherlands 753503/01/pp36 Date of release: 2001 Dec 11 Document order number: 9397 750 08189

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