TC - Timer Counter

Timer Counter

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Timer Counter

Timer Counter

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Timer Counter Features Three 16-bit Timer Counter Channels with chaining capability A Wide Range of Functions:

- Capture Mode:– Frequency Measurement

– Event Counting

– Interval Measurement

- Waveform Mode:– Pulse Generation

– Delay Timing

– Pulse Width Modulation

Each Channel is User-configurable and Contains:– Three External Clock Inputs

– Five Internal Clock Inputs

– Two Multi-purpose Input/Output Signals Internal Interrupt Signal Up/down Capabilities Two Global Registers that Act on All Three TC Channels

Timer Counter

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Block Diagram

Timer Counter

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I/O Pins Definition

Timer Counter

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Dependencies

PMC has to be programmed 1st for Timer Counter to work Multiplexed PIO Pins have to be disabled to allow the TC to use it in waveform

or capture mode Multiplexed PIO Pins have not to be disabled if the TC is used to generate

internal tick

Timer Counter

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Clock Sources

TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5

5 Internal

Clock Sources

3 External

Clock Sources

Timer Counter

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Clock Selection and Control

S

RQ

S

RQ

CLKDISCLKENCLKSTA

Trigger ( Reset Counter )

Clock Control Output

LDBSTOP

CPCSTOP

Load RB ( Capture )

Compare RC ( Waveform )

Counter

Clock

Clock Selection- MCK/2, MCK/8, MCK/32, MCK/128,

MCK/1024

- External clock signals XC0, XC1, XC2

- Selected clock can be inverted

- Burst Function

Clock Control- 2 control levels

• enable/disable • start/stop

- Software Enabling Commands by Control Register : CLKEN and CLKDIS

- Loading RB in Capture Mode or RC Compare in Waveform Mode can stop or disable the counter clock

MCK/8

MCK/32

MCK/128

MCK/1024

XC0

XC1

XC2

CLKI

CLKS

BURST

1

MCK/2

Timer Counter

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Counter Duration and Resolution The maximal counter duration when internal clock is used, is determined by the

internal clock (MCK) and the prescale number Maximal Counter Duration (seconds) = 216/CLK where CLK is in Hz. Counter Resolution = 1/CLK

Real-time counter overflow rates for various MCK

Timer Counter

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External Clock 16 bit counter can be programmed as a 16 bit event counter An external transition on XCx (rising or falling following the state

of CLKI, bit [3] of the Mode registers) increments the counter.

WARNING

If an external clock is used, make sure that each of its pulses has a duration strictly higher than

the system clock (MCK) period

Timer Counter

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Trigger

Clock Counter

0002h0001h0000hxxxxClock Value

Counter Reset- performed by a trigger- Synchronous : effective only at following active clock edge- All triggers are synchronous (even CPCTRG)

Counter Reset

Timer Counter

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Triggers Waveform Mode

- SWTRG : software

- SYNC : synchronous

- CPCTRG : RC Compare

- ENETRG : External Event

- EEVT • TIOB is set as an input and

can not generate waveform• XC0• XC1• XC2

- EEVTEDG• none• positive edge• negative edge• both edges

Capture Mode- SWTRG : software

- SYNC : 3-channels shot

- CPCTRG : RC Compare

- ABETRG• TIOA• TIOB

- ETRGEDG • none• positive edge• negative edge• both edges

Internal Internal

External

External

Counter Trigger configuration is in the TC Channel Mode register TC_CMR TC_CMR fields have not the same settings according to Wave or Capture Mode

Timer Counter

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Clock Value

Clock Counter

Clock Selected

Burst

Burst Mode

- BURST input can be XC0, XC1,XC2 External signal conditional count Clock is enabled only if selected input is high

Burst Mode

Timer Counter

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Capture Mode WAVE bit field is set to ZERO in the TC_CMR Capture mode allows the TC channel to perform measurements such as:

- pulse timing, - frequency, period,- duty cycle, phase

TIOA and TIOB signals are used as input RA and RB 16-bit registers are in Read-Only access

Timer Counter

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Capture Mode

16-bit Counter

Capture Register A

TIOAinput

TIOBinput

Capture Register B

RA Loading

Logic

SYNC

SWTRG

RC Compare

Register C

CPCTRG

LDRA LDRB

EdgeDetector

ETRGEDG

ABETRG

SelectedClock

RB Loading

Logic

RA Loading Logic : can be loaded only after a trigger or if RB has been loaded RB Loading Logic : can be loaded only after a trigger and if RA has been loaded

Timer Counter

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TC Channel Mode Register: Capture Mode Timer Counter Channel Mode Register TC_CMR (Read / Write) WAVE 1-bit field =0 sets the Counter Channel in Capture Mode

TCCLKS Clock Selected

MCK/2

MCK/8

MCK/32

MCK/128

0 00

1 10

010

100

0 01

1 11

011

101

MCK/1024

XC0

XC1

XC2

BURST

0 0

0 1

1 0

1 1

The clock is not gated by an external signal

XC0 is ANDed with the selected clock



TC_CMR in CAPTURE Mode

LDRA ABETRG10

CPCTRG14

WAVE=016 1517

LDRB1819

TCCLKS02

CLKI3

BURST5 4

LDBSTOP6

LDBDIS7

ETRGEDG9 8

Timer Counter

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TC Channel Mode Register: Capture Mode

LDRA

0 0

0 1

1 0

1 1

RA Loading edge

none

rising

falling

rising and falling

LDRB

0 0

0 1

1 0

1 1

RB Loading edge

none

rising

falling

rising and falling

ETRGEDG

0 0

0 1

1 0

1 1

External Trigger Edge

none

rising

falling

rising and falling

LDRBLDRA19 18 17 16

TC_CMR

TC_CMR

ETRGEDG9 8

TC_CMR in CAPTURE Mode

LDRA ABETRG10

CPCTRG14

WAVE=016 1517

LDRB1819

TCCLKS02

CLKI3

BURST5 4

LDBSTOP6

LDBDIS7

ETRGEDG9 8

CLKI when set the counter is incremented at the falling edge

CPCTRG when set RC compare resets and start the counter clock

ABETRG when set TIOA is used as an external trigger, equal zero TIOB is used as an external trigger

Timer Counter

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TC Status Register TC_SR: Capture Mode Counter Overflow occurs when the counter reaches 0xFFFF Load Overrun occurs when RA or RB are reloaded before being read RC Compare is set when the counter reaches the RC value RA Loading is set when RA is loaded RB Loading is set when RB is loaded External Trigger is set when an external event is detected Counter Clock Status TIOA Mirror reflects TIOA pin value TIOB Mirror reflects TIOB pin value The bit field – is set to a to zero value on read in Waveform mode

LOVRS COVFS1 0

--2

--3

LDRAS CPCS5 4

LDRBS6

ETRGS7

CLKSTAMTIOAMTIOB161718

Timer Counter

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TC Interrupts : Capture Mode Timer Counter Interrupt Enable Register TC_IER (Write Only)

0 = No effect

1 = Enable Timer Counter Interrupt Disable Register TC_IDR (Write Only)

0 = No effect

1 = Disable Timer Counter Interrupt Mask Register TC_IMR (Read Only)

0 = Not enabled

1 = Enabled The bit fields – are unused and have no effect in capture Mode

TC_IER, TC_IDR,TC_IMR

LOVRS COVFS1 0

--2

--3

LDRAS CPCS5 4

LDRBS6

ETRGS7

Timer Counter

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Capture Mode Example A TIOB rising edge resets and starts the counter A rising TIOA edge loads RA and a falling TIOA edge loads RB RA contains the phase between TIOB and TIOA (RB-RA) is the duration of the TIOA pulse

Timer Counter

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Waveform Mode Can generates 1 or 2 PWM signals with

- same frequency - different duty cycles

Can generates different types of one-shot or repetitive pulses TIOA is configured as an output TIOB is defined as an output if it is not used as an external event (EEVT

parameter in TC_CMR) Output controller can set, clear or toggle TIOA and/or TIOB outputs RA, RB and RC registers can all be used as compare registers

Timer Counter

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Block Diagram in Waveform Mode

16-bit Counter

Register A

TIOBinput

Register B

SYNC

SWTRG

RC Compare

Register C

CPCTRG

EdgeDetector

EEVTEDG

EEVT

SelectedClock

RB CompareRA Compare

XC2XC1XC0

ENETRG

ASWTRG

AEEVT

ACPC

ACPA

BSWTRG

BEEVT

BCPC

BCPB

TIOBoutput

TIOAoutput

EEVT = TIOB

TIOB defines as input

Timer Counter

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Channel Mode Register: Waveform Mode

Manages the behavior of TIOA

Manages the

behavior of TIOB

External Event Source and Edge Selection

Clock Source Selection

RC Compare effect on TC’s

clock

Timer Counter

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TC Channel Mode Register: Waveform Mode Timer Counter Channel Mode Register TC_CMR (Read / Write) WAVE 1-bit field =1 sets the Counter Channel in Waveform Mode

TCCLKS Clock Selected

MCK/2

MCK/8

MCK/32

MCK/128

0 00

1 10

010

100

0 01

1 11

011

101

MCK/1024

XC0

XC1

XC2

WAVSEL

0 0

0 1

1 0

1 1

UP mode without automatic trigger on RC compare

Effect

UP mode with automatic trigger on RC compare

UP DOWN mode without automatic trigger on RCcompare

UP DOWN mode with automatic trigger on RCcompare

TC_CMR in WAVEFORM Mode

EEVTEDG9 8 CPCDIS7

TCCLKS2 0

CLKI3

CPCSTOP6

BURST5 4

EEVT11 10WAVE=1

15WAVSEL14 13

ACPC19 18ACPA

17 16ENETRG

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BSWTRG31 30

BEEVT29 28 25 24BCPA

27 26BCPC AEEVTASWTRG23 22 21 20

Timer Counter

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TC Channel Mode Register: Waveform Mode

ACPC

0 0

0 1

1 0

1 1

none

set

clear

toggle

RC Compare Effect on TIOA

ACPA

0 0

0 1

1 0

1 1

RA Compare effect on TIOA

none

set

clear

toggle

ACPAACPC19 18 17 16

Effect on TIOBBCPC BCPA

27 26 25 24

ASWTRG

0 0

0 1

1 0

1 1

none

set

clear

toggle

Software Trigger Effect onTIOA

AEEVT

0 0

0 1

1 0

1 1

none

set

clear

toggle

External Event on TIOA

AEEVTASWTRG23 22 21 20

Effect on TIOBBSWTRG BEEVT

31 30 29 28

Timer Counter

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TC Channel Mode Register: Waveform ModeBURST

0 0

0 1

1 0

1 1

The clock is not gated by an external signal



XC2 is ANDed with the selected clock ETRGEDG

0 0

0 1

1 0

1 1

External Trigger Edge

none

rising

falling

rising and falling

EEVTEDG9 8

EEVT

0 0

0 1

1 0

1 1

External Event Signal Selection

TIOB WARNING TIOB IS AN INPUT & CAN NOT

GENERATE WAVEFORM

XC0

XC1

XC2

EEVT11 10

Timer Counter

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TC Status Register TC_SR: Waveform Mode Counter Overflow occurs when the counter reaches 0xFFFF RA compare is set when the counter reaches the RA value RB compare is set when the counter reaches the RB value RC Compare is set when the counter reaches the RC value External Trigger is set when an external event is detected Counter Clock Status TIOA Mirror reflects TIOA pin value TIOB Mirror reflects TIOB pin value The bit field – is set to a to zero value on read in Waveform mode

-- COVFS1 0

CPAS2

CPBS3

-- CPCS5 4

--6

ETRGS7

CLKSTAMTIOAMTIOB161718

Timer Counter

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TC Interrupts : Waveform Mode Timer Counter Interrupt Enable Register TC_IER (Write Only)

0 = No effect

1 = Enable Timer Counter Interrupt Disable Register TC_IDR (Write Only)

0 = No effect

1 = Disable Timer Counter Interrupt Mask Register TC_IMR (Read Only)

0 = Not enabled

1 = Enabled The bit fields – are unused and have no effect in waveform Mode

TC_IER, TC_IDR,TC_IMR

-- COVFS1 0

CPAS2

CPBS3

-- CPCS5 4

--6

ETRGS7

Timer Counter

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Waveform Generation: WAVSEL=00

Without Automatic Trigger on RC compare means that the Counter is cleared- when reaches its maximal value (0xFFFF)- When an external event or software trigger occurs

Square wave generation on TIOA and TIOB Toggle after an equality with RA or RC for TIOA and RB or RC for TIOB

Timer Counter

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With Automatic on RC compare means that the Counter is cleared- when reaches its RC value- When an external event or software trigger occurs


Timer Counter

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With Automatic Trigger on RC compare means that the Counter is decremented

- when reaches its programmable RC value - When an external event or software trigger occurs


Timer Counter

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Without Automatic Trigger on RC compare means that the Counter is decremented

- when reaches its maximal value (0xFFF) - When an external event or software trigger occurs


Timer Counter

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Timer Counter Block Timer Counter Block Control Register TC_BCR (Write

Only) - SYNC:1-bit field- SYNC=1 allows a Commune Software triggers on the 3 Timer

Counter Channels. Timer Counter Block Mode Register TC_BMR (Read/Write)

- Allows chaining capability while using an external clock- Three 2-bit fields: TC0XC0S, TC1XC1S, TC2XC2S- TC0XC0 means External Clock XC0 of Timer counter 0- Possible external clock sources are on Timer Counter 1 and 2

• TIOA1, TIOA2

• TCLK0 (XC0), the true Timer counter 0 « external clock » TC_BMR

TC0XC0S1 0

TC1XC1S23

TC2XC2S5 4

TC0XC0S

0 0

0 1

1 0

1 1

XC0 signal

TCLK0

none

TIOA0

TIOA2

TC1XC1S

0 0

0 1

1 0

1 1

XC1 signal

TCLK1

none

TIOA1

TIOA2

TC2XC2S

0 0

0 1

1 0

1 1

XC2 signal

TCLK2

none

TIOA0

TIOA1

Timer Counter

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Timer Counter Summary Three 16-bit Timer Counter Channels

- Three output compare or two input capture Wide range of functions including:

- Frequency measurement- Event counting- Interval measurement- Pulse generation- Delay timing- Pulse Width Modulation- Up/down capabilities

Each channel is user-configurable and contains:- Three external clock inputs- Five internal clock inputs- Two multi-purpose input/output signals- Two global registers that act on all three TC channels

Capture

Waveform

Documents

TC - Timer Counter