TB-FMCH-8AD250 Hardware User Manual · TB-FMCH-8AD250 Hardware User Manual Rev.1.0 5 1. Introduction Thank you for purchasing the TB-FMCH-8AD250 board.Before using the product, be

TB-FMCH-8AD250 Hardware User Manual

1 Rev.1.0


Rev. 1.0


2 Rev.1.0

Revision History Version Date Description Publisher

Rev. 0.1 06/21/2016 Initial release. Test data still required. LM / DM Rev. 0.2 08/17/2016 Updated signature on last page. ST Rev. 0.3 10/27/2016 More performance data added LM Rev. 1.0 11/08/2016 Reviewed and updated. Released. ST


3 Rev.1.0

Table of Contents 1. Introduction ................................................................................................................................ 5 2. Related Documents and Accessories ........................................................................................ 8 3. Overview .................................................................................................................................... 9 4. Features ................................................................................................................................... 10 5. Block Diagram ......................................................................................................................... 11 6. External View of the Board ...................................................................................................... 12 7. Board Specifications ................................................................................................................ 14

7.1. Mechanical ............................................................................................................................ 14 7.2. Electrical................................................................................................................................ 15 7.3. Measured Performance ......................................................................................................... 17

7.3.1. Frequency Response .................................................................................................... 17 7.3.2. Adjacent Channel Coupling ........................................................................................... 17 7.3.3. Spectrum Plots .............................................................................................................. 18 7.3.4. Input Return Loss .......................................................................................................... 24 7.3.5. Clock Output .................................................................................................................. 26 7.3.6. Trigger Output ............................................................................................................... 27

8. Board Hardware ....................................................................................................................... 28 8.1. ADC Inputs ............................................................................................................................ 28 8.2. ADC Outputs ......................................................................................................................... 28 8.3. External Clock and Trigger .................................................................................................... 28 8.4. On-Board Clock and SYSREF Generation ............................................................................ 29 8.5. AD9250 and AD9528 Register Programming ........................................................................ 29 8.6. Power System ....................................................................................................................... 30 8.7. LED Indicators ....................................................................................................................... 31 8.8. HPC FMC Connector to Carrier Board .................................................................................. 32 8.9. FMC I2C EEPROM ................................................................................................................ 36 8.10. Thermal Performance ........................................................................................................ 36

9. Appendix A: FMC I2C EEPROM ............................................................................................... 40 10. Appendix B: TB-FMCH-8AD250 Quick Start ............................................................................ 43

10.1. VC707 (FMC2) Pin Assignment ......................................................................................... 43 10.2. Demonstration Set-up ....................................................................................................... 44

11. Appendix C: Configuration Details for the AD9528 .................................................................. 46


4 Rev.1.0

List of Figures Figure 1: TB-FMCH-8AD250 Block Diagram .................................................................................. 11 Figure 2: Photo of TB-FMCH-8AD250 (Component side, heatsink removed) ................................ 12 Figure 3: Photo of TB-FMCH-8AD250 (Side 2) .............................................................................. 13 Figure 4: Board Dimensions .......................................................................................................... 14 Figure 5: Frequency Response ...................................................................................................... 17 Figure 6: Adjacent Channel Crosstalk (input = channel 3) ............................................................. 17 Figure 7: Spectrum for Channels 1:8, 30 MHz Input ...................................................................... 18 Figure 8: Spectrum for Channels 1:8, 90 MHz Input ...................................................................... 19 Figure 9: Spectrum for Channels 1:8, 140 MHz Input .................................................................... 20 Figure 10: Spectrum for Channels 1:8, 185 MHz Input .................................................................. 21 Figure 11: Spectrum for Channels 1:8, 220 MHz Input ................................................................... 22 Figure 12: Spectrum for Channels 1:8, 305 MHz Input .................................................................. 23 Figure 13: Broadband Return Loss (2 boards, 8 ADC channels each) ........................................... 24 Figure 14: Zoomed Return Loss (Nyquist zones 1 and 2) .............................................................. 25 Figure 15: Bi-directional Clock MMCX set as Output ..................................................................... 26 Figure 16: Bi-directional Trigger MMCX set as Output ................................................................... 27 Figure 17: Analog input circuitry ..................................................................................................... 28 Figure 18: External Clock Reference ............................................................................................. 29 Figure 19: SPI Conversion and Level Translation .......................................................................... 30 Figure 20: Power system block diagram ........................................................................................ 31 Figure 21: FMC HPC Connector Pin Layout as per VITA 57.1 ....................................................... 32 Figure 22: Heat Sink mechanical drawing (for reference only) ....................................................... 37 Figure 23: Thermal Image – back side, heatsink installed on component side ............................... 38 Figure 24: Thermal Image - component side with heatsink ............................................................ 39 Figure 25: FMC HPC Connector Pinout (FMC2 on VC707) ........................................................... 44

List of Tables

Table 2-1 Accessories ...................................................................................................................... 8 Table 7-1: TB-FMCH-8AD250 Electrical Characteristics ................................................................ 15 Table 7-2: TB-FMCH-8AD250 Absolute Maximum Electrical Characteristics ................................. 16 Table 8-1 HPC FMC Host Board Connector Pin Assignment ......................................................... 33 Table 8-2 Channel naming and numbering explanation ................................................................. 36 Table 9-1 FMC I2C EEPROM Contents ......................................................................................... 40


5 Rev.1.0

1. Introduction Thank you for purchasing the TB-FMCH-8AD250 board. Before using the product, be sure to carefully read this user manual and fully understand how to correctly use the product.

SAFETY PRECAUTIONS Be sure to observe these precautions! Observe the precautions listed below to prevent injuries to you or other personnel or damage to property. • Before using the product, read these safety precautions carefully to assure correct use. • These precautions contain serious safety instructions that must be observed. • After reading through this manual, be sure to always keep it handy. The following conventions are used to indicate the possibility of injury/damage and classify precautions if the product is handled incorrectly.

Indicates the high possibility of serious injury or death if the product is handled incorrectly.

Indicates the possibility of serious injury or death if the product is handled incorrectly.

Indicates the possibility of injury or physical damage in connection with houses or household goods if the product is handled incorrectly.

The following graphical symbols are used to indicate and classify precautions in this manual. (Examples)

Turn off the power switch.

Do not disassemble the product.

Do not attempt this.

Danger

Warning

Caution


6 Rev.1.0

In the event of a failure, disconnect the power supply. If the product is used as is, a fire or electric shock may occur. Disconnect the power supply immediately and contact our sales personnel for repair.

If an unpleasant smell or smoking occurs, disconnect the power supply. If the product is used as is, a fire or electric shock may occur. Disconnect the power supply immediately. After verifying that there is no smoking, contact our sales personnel for repair.

Do not disassemble, repair or modify the product. Otherwise, a fire or electric shock may occur due to a short circuit or heat generation. For inspection, modification or repair, contact our sales personnel.

Do not touch a cooling fan. As a cooling fan rotates at high speed, do not put your hand close to it. Otherwise, it may cause injury to persons. Never touch a rotating cooling fan.

Do not place the product on unstable locations. Otherwise, it may drop or fall, resulting in injury to persons or failure.

If the product is dropped or damaged, do not use it as is. Otherwise, a fire or electric shock may occur.

Do not touch the product with a metallic object. Otherwise, a fire or electric shock may occur.

Do not place the product in dusty or humid locations or where water may splash. Otherwise, a fire or electric shock may occur.

Do not get the product wet or touch it with a wet hand. Otherwise, the product may break down or it may cause a fire, smoking or electric shock.

Do not touch a connector on the product (gold-plated portion). Otherwise, the surface of a connector may be contaminated with sweat or skin oil, resulting in contact failure of a connector or it may cause a malfunction, fire or electric shock due to static electricity.

Warning


7 Rev.1.0

Do not use or place the product in the following locations. • Humid and dusty locations • Airless locations such as closet or bookshelf • Locations which receive oily smoke or steam • Locations exposed to direct sunlight • Locations close to heating equipment • Closed inside of a car where the temperature becomes high • Static-prone locations • Locations close to water or chemicals Otherwise, a fire, electric shock, accident or deformation may occur due to a short circuit or heat generation.

Do not place heavy things on the product.

Otherwise, the product may be damaged.

■ Disclaimer This product is a multi-channel analog to digital converter interface for Xilinx FPGA evaluation boards. Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated. Even if the product is used properly, Tokyo Electron Device Limited assumes no responsibility for any damages caused by: (1) Earthquake, thunder, natural disaster or fire resulting from the use beyond our responsibility, acts by

a third party or other accidents, the customer’s willful or accidental misuse, or use under other abnormal conditions.

(2) Secondary impact arising from use of this product or its unusable state (business interruption or others)

(3) Use of this product against the instructions given in this manual. (4) Malfunctions due to connection to other devices. Tokyo Electron Device Limited assumes no responsibility or liability for: (1) Erasure or corruption of data arising from use of this product. (2) Any consequences or other abnormalities arising from use of this product, or (3) Damage of this product not due to our responsibility or failure due to modification. This product has been developed by assuming its use for research, testing or evaluation. It is not authorized for use in any system or application that requires high reliability. Repair of this product is carried out by replacing it on a chargeable basis, not repairing the faulty devices. However, non-chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product. The specification of this product is subject to change without prior notice. The product is subject to discontinuation without prior notice.

Caution


8 Rev.1.0

2. Related Documents and Accessories All documents relating to this board can be downloaded from the TED Support Web at address https://www.teldevice.co.jp/spweb/c0201s

Table 2-1 Accessories

Description Manufacturer Quantity Spacer, 10mm, M2.6 Hirosugi 2 Spacer, 25mm, M2.6 Hirosugi 2 Screw, 6mm, M2.6 w/ washers Hirosugi 6


9 Rev.1.0

3. Overview The TB-FMCH-8AD250 is an 8-channel, 250MSPS, 14-bit, ANSI/VITA 57.1 compatible, analog-to-digital converter FPGA Mezzanine Card (FMC). It is carefully designed to be compatible with a large variety of Xilinx®-based carrier boards. The user can connect up to eight (8) analog inputs for digitization, and when necessary, leverage the Trigger and Reference Clocking features. The TB-FMCH-8AD250 provides a convenient method for prototyping, proving, and de-risking your mixed-signal development. The TB-FMCH-8AD250 features four (4), Analog Devices® AD9250, dual, JESD204B ADCs. Following conversion, each output channel results in a 5 Gbit/s, JESD204B serial output lane. The FMC supports JESD204B subclass 1, enabling the user to synchronize all eight (8) channels due to the JESD204B deterministic latency features. Low-jitter ADC clocking is provided by a multiple output, Analog Devices AD9528 clock generation chip. In addition to this free-running system, provision is made to both accept and generate external clock and trigger sources. The front edge of the FMC features ten (10) MMCX jacks: Eight (8) analog inputs, one (1) bi-directional trigger, and one (1) bidirectional clock reference.


10 Rev.1.0

4. Features Eight (8) analog inputs Four (4) Analog Devices AD9250 ADCs (250MSPS, 14-bit) Low-jitter ADC clocking Analog Devices AD9528 clock generator JESD204B subclass 1 Deterministic latency via SYSREF support External clock connection 10 MHz reference input or variable frequency output External trigger connection Input or output capability FPGA VADJ signal level 1.2V through 3.3V support 12V0 and 3V3 power entry Overcurrent protection via PTCs FMC Configuration EEPROM Micron M24C02 2Kb I2C EEPROM with GA0/1 address selection LED indicators Power good, PLL lock indicators (green), Trouble (red)


11 Rev.1.0

5. Block Diagram Figure 1 shows the TB-FMCH-8AD250 block diagram.

VCXO

LOW

JIT

TER

CLO

CK

GE

NER

ATO

R

ADI

AD95

28

BALU

NBA

LUN

TER

MIN

ATIO

N

RF

INPU

T 1

ADI

AD92

50

AD

C1

BALU

N

TER

MIN

ATIO

N

MM

CX

RF

INPU

T 2M

MC

X

BALU

N

TER

MIN

ATIO

N

RF

INPU

T 3

BALU

N

TER

MIN

ATIO

N

MM

CX

RF

INPU

T 4M

MC

X

BALU

N

TER

MIN

ATIO

N

RF

INPU

T 5

BALU

N

TER

MIN

ATIO

N

MM

CX

RF

INPU

T 6M

MC

X

BALU

N

TER

MIN

ATIO

N

RF

INPU

T 7

BALU

N

TER

MIN

ATIO

N

MM

CX

RF

INPU

T 8M

MC

X

CLO

CKM

MC

XTE

RM

INAT

ION

TRIG

GE

R[L

VTT

L, 5

V TO

L]MM

CX

LOW

LAT

ENC

Y BU

FFE

RS

VCXO

_IN

REF

ASY

SREF

[LV

DS]

SAM

PLI

NG

CLO

CK

S[L

VD

S]

SPI B

US

(1.8

V)

FMC

CO

NN

EC

TOR

CLK

SPI

BU

S (3

.3V)

LEVE

LTR

ANSL

ATE

M2C

_FPG

A_LV

DS[

2:1]

_CLK

[PN

]

M2C

_FPG

A_LV

DS_

SYSR

EF[P

N]

M2C

_FPG

A_LV

DS3

_CLK

[PN

]

GB

TCLK

[1:0

]C

LK0

CLK

1

OU

T[11

:9]

[LV

DS]

OU

T8[L

VD

S]

ADC

_RST

_N

ADC

1A_C

ML[

PN]

ADC

1B_C

ML[

PN]

ADC

2A_C

ML[

PN]

ADC

2B_C

ML[

PN]

ADC

3A_C

ML[

PN]

ADC

3B_C

ML[

PN]

ADC

4A_C

ML[

PN]

ADC

4B_C

ML[

PN]

+12V

_FM

C+3

V3_F

MC

VAD

J

EEPR

OM

(2K

)I2

C

SAM

TEC

ASP-

1344

88-0

1

STM

M24

C02

-WDW

6TP

CLK

GEN

_RES

ETn

(3.3

V)C

LKG

EN_M

AN_S

YNC

(3.3

V)

SWIT

CHER

_SYN

Q[2

:1] (

3.3V

)

CLK

SPI

(VAD

J)

SWIT

CHER

_SYN

Q[2

:1] (

VAD

J)AD

C S

PI (V

ADJ)

CLK

GEN

_RES

ETn

(VAD

J)C

LKG

EN_M

AN_S

YNC

(VAD

J)

BALU

N

BALU

N

BALU

N

BALU

N

BALU

N

BALU

N

BALU

N50

Ω

50Ω

50Ω

50Ω

50Ω

50Ω

50Ω

50Ω

ADC

_PD

WN

ADC

_RST

_N (1

.8V)

ADC

_PD

WN

(1.8

V)

ADC

4_LV

DS_

SYN

CB[

PN]

ADC

3_LV

DS_

SYN

CB[

PN]

ADC

2_LV

DS_

SYN

CB[

PN]

ADC

1_LV

DS_

SYN

CB[

PN]

ADI

AD92

50

ADI

AD92

50

ADI

AD92

50

C2M

_TRI

GG

ER[P

N]

M2C

_TRI

GG

ER[P

N]

ADC

4B_B

LEED

_TR

IGG

ER

ADC

4B_B

LEED

_TR

IGG

ER

VCXO

_VT

OU

T12P

STA

TUS

0

STA

TUS

1

TRO

UBLE

AD

C4

AD

C3

AD

C2

D12

D13

D16

Cry

stek

CVH

D-0

37X

-125

CLK

_C2M

_REF

CLK

[PN

]R

EFB

SYSR

EF_R

EQ

Figure 1: TB-FMCH-8AD250 Block Diagram


12 Rev.1.0

6. External View of the Board

TRIGGERI/O

CLOCK REF.I/O

CHANNEL 8

8x SHIELDS OVER BALUNS FOR GREATER

CH-CH ISOLATION4x AD9250

ADCs4x ADM7171

LDOs

AD9528 CLOCK

GENERATOR VCXOFMC HPC

CONNECTOR

CHANNEL 7

CHANNEL 6

CHANNEL 5

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

ANAL

OG

INP

UTS

Figure 2: Photo of TB-FMCH-8AD250 (Component side, heatsink removed)


13 Rev.1.0

TROUBLELED (RED)

POWER GOODLED (GREEN)

TRIGGERI/O

CLOCK REF.I/O

CHANNEL 8

CHANNEL 7

CHANNEL 6

CHANNEL 5

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

AN

ALO

G IN

PU

TS

STATUS0LED (GREEN)

STATUS1LED (GREEN)

Figure 3: Photo of TB-FMCH-8AD250 (Side 2)


14 Rev.1.0

7. Board Specifications 7.1. Mechanical

The following shows the TB-FMCH-8AD250 board physical specifications. External Dimensions 84 mm L x 69 mm W – Dimensions / features per VITA57.1 Number of Layers 12 layers Board Thickness 1.6 mm Material Isola370HR FR4 FMC HPC Connector Samtec ASP-134488-01 MMCX Connectors Molex 73415-1001 Note: SSMC Connectors (e.g. Radiall / AEP 7110-1511-000) rather than MMCX may be available in some jurisdictions as a special order item. Contact inrevium sales for more information

Notes:

• Board outline features conform to VITA57.1 conduction-cooled, commercial grade, single-width modules, Regions 1, 2, and 3, present.

• Board component side is defined in VITA 57.1 as Side 1 and faces the host carrier card when installed • Board solder side is defined as Side 2 and is probe and visually accessible when the card is installed

Ø2.2 13plcs

63.0

0

66.0

0

61.3

0

3.00

59.0

558

.30

3.30

63.5

0

18.40

20.0020.003.30

2.50

0.50

18.00

15.90

1.50

15.0

015

.00

15.0

015

.00

35.90

8.2813

.28

18.2

823.2

828.2

833.2

838.2

843.2

848.2

853.2

8

0.29

63.4

0

Ø2.7 4plcs

Figure 4: Board Dimensions

Note: The board dimensions photo above is for reference only - do not use for design purposes. inrevium can provide a mechanical file if dimensional accuracy is important.


15 Rev.1.0

7.2. Electrical

The following table presents electrical performance characteristics for the TB-FMCH-8AD250.

Table 7-1: TB-FMCH-8AD250 Electrical Characteristics

Min Typ Max Units Notes Upper ‐3 dB input frequency 400 MHz Upper ‐6 dB input frequency 600 MHz Lower ‐3 dB input frequency 1 MHz Input level (at 100 MHz) for ‐1 dBFS 6.8 dBm 50 ohm sinewave source Input return loss (Ch1‐8), 4.5 MHz ‐ 400 MHz ‐10 dB SNR

Input = 30 MHz 70.9 dBFS Input = 90 MHz 70.2 dBFS Input = 140 MHz 68.8 dBFS Input = 185 MHz 65.7 dBFS Input = 220 MHz 66.5 dBFS Input = 305 MHz 64.5 dBFS

SFDR Input = 30 MHz 78.5 dBc Input = 90 MHz 77.4 dBc Input = 140 MHz 79.8 dBc Input = 185 MHz 75.5 dBc Input = 220 MHz 79 dBc Input = 305 MHz 76.8 dBc

ENOB Input = 30 MHz 11.4 bits Input = 90 MHz 11.2 bits Input = 140 MHz 11 bits Input = 185 MHz 10.6 bits Input = 220 MHz 10.8 bits Input = 305 MHz 10.4 bits

Two‐tone SFDR TBD dBc

Fin1 = 184.12 MHz, Fin2 = 187.12 MHz, both tones at ‐7 dBFS

Crosstalk @ 100 MHz: first adjacent ‐90 ‐85 dB

Ch3 input, Ch2 and Ch4 levels

Crosstalk @ 100 MHz: second adjacent ‐100 dB

Ch3 input, Ch2 and Ch4 levels

External clock input frequency 9999750 10000000 10000250 Hz +/‐ 25 ppm Current from 12V0 800 mA Current from 3V3 100 mA Current from VADJ 100 mA


16 Rev.1.0

Table 7-2: TB-FMCH-8AD250 Absolute Maximum Electrical Characteristics

Absolute max rating Ch1‐8 input level 16 dBm 50 ohm source Clock input level 3.6 Volts pk‐pk Trigger input level 3.6 Volts pk‐pk Ambient temperature (convection airflow) 0 45 deg C


17 Rev.1.0

7.3. Measured Performance 7.3.1. Frequency Response

Figure 5: Frequency Response

7.3.2. Adjacent Channel Coupling

Figure 6: Adjacent Channel Crosstalk (input = channel 3)


18 Rev.1.0

7.3.3. Spectrum Plots

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch3 30 MHz

Freq = 30.1 MHzSFDR = 76.91 dBcSNR = 69.84 dBcSINAD = 68.57 dBcTHD = -74.47 dBcENOB = 11.31 Bits

X: 30.1Y: -1.273

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch5 30 MHz


X: 30.1Y: -1.259

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch7 30 MHz


X: 30.1Y: -1.427

Leve

l (dB

FS)

Figure 7: Spectrum for Channels 1:8, 30 MHz Input


19 Rev.1.0

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch1 90 MHz


X: 90.1Y: -1.142

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch3 90 MHz


X: 90.1Y: -0.9962

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch5 90 MHz


X: 90.1Y: -0.9667

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch7 90 MHz


X: 90.1Y: -1.18

Leve

l (dB

FS)



20 Rev.1.0

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch1 140 MHz


X: 109.9Y: -1.045

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch3 140 MHz


X: 109.9Y: -0.8846

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch5 140 MHz


X: 109.9Y: -0.8165

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch7 140 MHz


X: 109.9Y: -1.03

Leve

l (dB

FS)



21 Rev.1.0

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch1 185 MHz


X: 64.9Y: -1.233

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch3 185 MHz


X: 64.9Y: -1.054

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch5 185 MHz

Freq = 64.9 MHzSFDR = 73 dBcSNR = 62.98 dBcSINAD = 62.76 dBcTHD = -75.85 dBcENOB = 10.29 Bits

X: 64.9Y: -0.962

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch7 185 MHz


X: 64.9Y: -1.207

Leve

l (dB

FS)



22 Rev.1.0

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch1 220 MHz


X: 29.9Y: -1.392

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch3 220 MHz


X: 29.9Y: -1.271

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch5 220 MHz

Freq = 29.9 MHzSFDR = 82.23 dBcSNR = 65.97 dBcSINAD = 65.71 dBcTHD = -78 dBcENOB = 10.82 Bits

X: 29.9Y: -1.173

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch7 220 MHz

Freq = 29.9 MHzSFDR = 80.19 dBcSNR = 65.62 dBcSINAD = 65.38 dBcTHD = -78 dBcENOB = 10.8 Bits

X: 29.9Y: -1.386

Leve

l (dB

FS)



23 Rev.1.0

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch1 305 MHz


X: 55.1Y: -1.401

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch3 305 MHz


X: 55.1Y: -1.243

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch5 305 MHz


X: 55.1Y: -1.171

Leve

l (dB

FS)

0 20 40 60 80 100 120Frequency (MHz)

-120

-100

-80

-60

-40

-20

0

Leve

l (dB

FS)

LD6751 Ch7 305 MHz


X: 55.1Y: -1.317

Leve

l (dB

FS)



24 Rev.1.0

7.3.4. Input Return Loss Overlayed return loss plots are shown below for the 8 ADC inputs from two TB-FMCH-8AD250 boards (16 traces in total). The first plot shows the broadband return loss results while the second plot has zoomed in on the first two Nyquist zones (DC – 125 MHz, 125 MHz – 250 MHz). The two traces that are slightly different from the others are both from ADC channel 7 – the channel that has the tiny coupling into the trigger channel. In all cases, it can be seen that return loss is better than -10 dB below 400 MHz.

Figure 13: Broadband Return Loss (2 boards, 8 ADC channels each)


25 Rev.1.0

Figure 14: Zoomed Return Loss (Nyquist zones 1 and 2)


26 Rev.1.0

7.3.5. Clock Output

Figure 15: Bi-directional Clock MMCX set as Output


27 Rev.1.0

7.3.6. Trigger Output

Figure 16: Bi-directional Trigger MMCX set as Output


28 Rev.1.0

8. Board Hardware 8.1. ADC Inputs The 8 ADC inputs (CH1 – CH8) are AC coupled and converted to differential format using a series – shunt double balun configuration. All channels are ESD-protected with PESD5V0F1BL “Femtofarad” bidirectional protection diodes. Each input is designed to be driven by a 50 ohm source. The discrete components are selected to optimize performance in the first Nyquist zone.

Figure 17: Analog input circuitry

Note: Although it is possible for the user to “tune” the front-end values to optimize the performance for their application, any soldering will void the warranty. Please contact inrevium with questions or concerns regarding this. 8.2. ADC Outputs The main outputs from each of the four (4) AD9250 ADC chips are two JESD204B output lanes and two corresponding Fast Detect outputs. The JESD204B lanes each run at 5 Gbits/s when supporting 14-bit, 250MSPS conversions for a total link rate of 5 Gbits/s x 8 lanes = 40 Gbits/s. The lanes are high speed, AC-coupled, differential pair serial links using CML levels and require careful routing, impedance control and gigabit receivers on the carrier card. The single-ended Fast Detect signals provide a low latency indication of an input that has exceeded a user-programmable threshold. As an example, a user might use this as an extremely fast method of detecting an overflow situation. Refer to the AD9625 datasheet for additional details. 8.3. External Clock and Trigger The external clock MMCX connection is AC coupled and ESD-protected with a PESD5V0F1BL “Femtofarad” bidirectional protection diode. This connection can also be configured as a clock output with appropriate register settings to the AD9528 clock generation chip.


29 Rev.1.0

Figure 18: External Clock Reference

The external trigger MMCX connection is DC coupled and ESD-protected with a PESD5V0F1BL “Femtofarad” bidirectional protection diode. This connection can also be configured as a trigger output with appropriate register settings to the FPGA on the carrier card. Note that a small portion of the trigger signal is weakly coupled to the channel seven (7) analog front-end input. This allows a trigger event to also be captured by an ADC channel which can facilitate closer analysis of the trigger wave-shape or trigger timing. JESD204B latency can also be determined and monitored with this capability. Note: Although it is theoretically possible for the user to disconnect the weak coupling of trigger into channel seven (7) by removing C277 (0.1 uF) or R207 (49.9 ohms), any soldering will void the warranty. 8.4. On-Board Clock and SYSREF Generation The AD9528 clock generation chip and the Crystek CVHD-37X-125 VCXO form the stand-alone basis for generating the 250 MHz sampling clocks used by the four (4) AD9250 ADC chips. If a 10 MHz (+/- 25 ppm) external clock is provided at the MMCX connector, all clocks will lock to this external source and green LED D12 will light (assuming the AD9528 is configured to use its STATUS0 pin to indicate PLL1 lock). The same thing will happen if a 10 MHz clock is sent from the carrier card to the REFB clock input of the AD9528. Note that if a 10 MHz clock is provided by the carrier to the AD9528 REFB input, this 10 MHz clock must NOT be derived from any clocks supplied by the AD9528 to the carrier card. This configuration will not damage anything, but proper PLL operation will not be possible. Note: The Quick Start FPGA load for the VC707 configures priority to the external MMCX clock source. If a 10 MHz clock is provided to both the external clock MMCX connector and the AD9528 REFB input from the carrier, the system will lock to the external clock on the MMCX input. A user might opt to implement a similar priority method. The AD9528 is also used to generate the SYSREF synchronization signal that is passed to the four (4) AD9250 ADC chips and to the carrier card. Subclass 1 operation from the JESD204B standard is used, resulting in deterministic and equal latency of the path from each ADC input to the corresponding data stream output from the JESD204B receive block on the carrier card. The reference FPGA load for the VC707 initially configures the AD9528 to generate a periodic SYSREF at 125 / 32 ~= 3.9 MHz, then turns SYSREF off to minimize the potential of adding to the system noise floor. 8.5. AD9250 and AD9528 Register Programming The four (4) AD9250 dual ADCs and the AD9528 clock generator require register configuration prior to operation. Note: Common configuration parameters are listed in the Quick Start reference design. Both the AD9250


30 Rev.1.0

and the AD9528 are highly programmable; users should review and understand Analog Devices datasheets and application notes prior to using the TB-FMCH-8AD250. The AD9250 and the AD9528 make use of a 3-wire SPI interface. The interface consists of Chip Select, Clock, and a bi-directional Data line. This un-conventional 3-wire SPI interface raises two design complications: One, most controllers or FPGAs are designed to interface to a 4-wire SPI interface, and two, the AD9250 and the AD9528 have different I/O voltages. The TB-FMCH-8AD250 uses the following circuit, injunction with the specialized FPGA logic, to complete the level translation and 3-to-4-wire conversion.

BUFFER

FMC

CO

NN

EC

TOR

CLKGEN

BUFFERC2M_CLKGEN_VADJ_CS_NC2M_VADJ_SCLK

ADC_1V8_SDIO

BUFFER C2M_VADJ_SDIO_DIR

BUFFER

CLKGEN_3V3_SDIOC2M_CLKGEN_VADJ_SDIO

C2M_ADC_VADJ_SDIO

ADC[4:1]

C2M_ADC[4:1]_VADJ_CS_NADC[4:1]_1V8_CS_NADC_1V8_SCLK

CLKGEN_3V3_CS_NCLKGEN_3V3_SCLK

3.3V

1.8V

3.3V

1.8V

VADJ

VADJ

VADJ

VADJ

3.3V

1.8V

VADJ

Figure 19: SPI Conversion and Level Translation

Note: The Quick Start reference design provides a method for interfacing to this circuit. Note: To avoid the potential for irreparably damaging the FMC and/or the carrier, due to bus contention, the user must be extremely careful to understand and follow the timing required by C2M_VADJ_SDIO_DIR control signal. Review the schematic carefully! 8.6. Power System The TB-FMCH-8AD250 uses the 12 Volt, the 3.3 Volt, the 3.3V AUX, and the VADJ rails supplied on the FMC connector from the carrier card. Most of the TB-FMCH-8AD250 power is drawn from the 12 volt rail which is protected from over-current conditions by a PTC resettable fuse1. Intermediate supplies of 4 volts and 2.5 volts are generated by switching power supplies connected to 12V0. The 4 volt intermediate rail is converted to two separate 3.3 volt supplies (using low-noise LDO linear regulators) for use with the AD9528 clock chip and the CVHD-037X-125 VCXO. The 2.5 volt intermediate rail is converted to four separate 1.8 volt supplies (using low-noise LDO linear regulators) for use with the four AD9250 ADC chips. VADJ can range from 1.2V to 3.3V and is used mainly to power the voltage translators.

1 Although PTC’s do offer over-current protection, depending on the over-current condition, they may not be immediately effective, as they can take an extremely long time to “trip”. If a PTC “trips” remove all power, and wait a few minutes for the PTC to cool down and “reset” itself.


31 Rev.1.0

The 4 volt and 2.5 volt switching supplies each provide an open-drain Power-Good output; these are tied together and used as the control for the “EN_PWR” green LED indicator D1.

SWITCHER

TITPS84250RKGR

LDO

ADIADM7171ACPZ

LDO

ADIADM7171ACPZ

LDOLDO

LDOLDO

ADIADM7171ACPZ

1V8_ADC11V8_ADC21V8_ADC31V8_ADC4

+3V3_VCXO

+3V3_CLOCKING

+4V+12V_FMC

SWITCHER

+2.5V

SWITCHER_SYNQ1

SWITCHER_SYNQ2

TITPS84250RKGR

PG_C2M

EN_P

WR

EN

EN

EN

PWR_GOODEN_PWRD1

PG

PG

EN

EN

Figure 20: Power system block diagram

The 4 volt and 2.5 volt switching supplies can be synchronized to a source provided by the carrier card. This source should provide a 50% duty cycle square wave at a frequency between 400 KHz and 500 KHz. Switching frequency ripple induced on the 12 volt supply can be minimized by sending the 4 volt switcher a square wave that is 180 degrees out of phase with the square wave provided to the 2.5 volt switcher. Note: The reference design drives the two switchers out of phase with a 450.5 KHz, 50% duty cycle square wave using the “_SYNQ1” and “_SYNQ2” lines. The actual switching frequency can be set in the range 400 KHz to 500 KHz by a register setting in the FPGA. 8.7. LED Indicators Three green LEDs and one red LED are located on Side 2 (solder side) of the TB-FMCH-8AD250 so they are visible when the card is installed on an FMC carrier. Green LED D1 indicates that all power supplies are enabled. Red LED D16 is controlled by the carrier card and can be used as a general “Trouble” light appropriate to the user’s application. Green LEDs D12 and D13 are controlled by the STATUS0 and STATUS1 pins (respectively) of the AD9528 clock generator chip. These can be configured to indicate the lock status of the two PLLs inside the AD9528. Other status options can also be selected – consult the AD9528 datasheet for more details. Note that if STATUS0 is configured to indicate the lock state of PLL1 in the AD9528, the associated green LED (D12) will not light until a 10 MHz reference is provided at either the external clock MMCX connector or from the carrier card through the FMC connector. If the STATUS1 pin on the AD9528 is configured to indicate the lock state of PLL2, the associated green LED (D13) should light once the AD9528 has been properly configured.


32 Rev.1.0

Refer to Figure 3 for the physical location of these LEDs. 8.8. HPC FMC Connector to Carrier Board The TB-FMCH-8AD250 interfaces to the Carrier board via an HPC FMC connector. An excerpt from ANSI/VITA 57.1 of the FMC HPC connector physical pin layout is provided below. The TB-FMCH-8AD250 makes use of a subset of the signals below.

Figure 21: FMC HPC Connector Pin Layout as per VITA 57.1

The actual FMC pin assignment for the TB-FMCH-8AD250 is provided in Table 8-1. In this table the C2M direction means Carrier-to-Mezzanine, representing an input to the FMC. The M2C direction means Mezzanine-to-Carrier, representing an output from the FMC. BIDIR identifies those signals whose direction can be application selected. Unused LAxx, DPx, and GBTCLKx signals are not included in the table and are left unconnected. Power and GND pins are also not included; refer to Figure 25: FMC HPC Connector Pinout (FMC2 on VC707) for power and ground pin connections. FPGA IO allocations to FMC IO pins are platform specific and not included in the following table. Please refer to the user manual of the particular FMC carrier host FPGA platform being used for the mapping of FMC IOs to FPGA banks and pins.


33 Rev.1.0

Table 8-1 HPC FMC Host Board Connector Pin Assignment

J6 Pin

Schematic Signal Name VITA 57.1 Pin

Name Direction Type Description

H4 CLK_M2C_FPGA_LVDS3_P CLK0_M2C_P M2C LVDS Reference clock to the FPGA

global clock pins H5 CLK_M2C_FPGA_LVDS3_N CLK0_M2C_N M2C LVDS

G2 CLK_M2C_FPGA_LVDS_SYSREF_P CLK1_M2C_P M2C LVDS Reference SYSREF to FPGA

global clock pins G3 CLK_M2C_FPGA_LVDS_SYSREF_N CLK1_M2C_N M2C LVDS

G6 ADC2_LVDS_SYNC_P LA00_CC_P C2M LVDS JESD204B Synchronization

signal to ADC2 (Channels 3

and 4) G7 ADC2_LVDS_SYNC_N

LA00_CC_N C2M LVDS

D8 ADC3_LVDS_SYNC_P LA01_CC_P C2M LVDS JESD204B Synchronization

signal to ADC3 (Channels 5

and 6) D9 ADC3_LVDS_SYNC_N

LA01_CC_N C2M LVDS

H7

C2M_ADC_PDWN

LA02_P

C2M LVCMOS

ADC Power-Down or Standby

control (active high). Common

to all four (4) ADCs.

H8 C2M_ADC_RST_N

LA02_N C2M LVCMOS

ADC reset (active low).

Common to all four (4) ADCs.

G9 CLK_C2M_REFCLKP LA03_P C2M LVDS Reference clock to the

AD9528. Can be used to

synchronize the AD9528 to an

FPGA master clock. G10 CLK_C2M_REFCLKN

LA03_N C2M LVDS

H10 SYSREF_P LA04_P C2M LVDS SYSREF to the AD9528. Can

be used by the AD9528 as an

external SYSREF reference. H11 SYSREF_N

LA04_N C2M

LVDS

D11 M2C_TRIGGERP LA05_P M2C LVDS Externally applied Trigger

signal from the Trigger input

connector D12 M2C_TRIGGERN

LA05_N M2C LVDS

C10 C2M_TRIGGERP LA06_P C2M LVDS FPGA generated trigger. Used

when the Trigger connector is

being driven as an output. C11 C2M_TRIGGERN

LA06_N C2M LVDS

H13 C2M_VADJ_SCLK

LA07_P

C2M LVCMOS

SPI Bus SCLK, to the ADCs

and Clock Generator

H14

C2M_VADJ_SDIO_DIR

LA07_N

C2M LVCMOS

SPI Bus buffer/level translator

direction control (an integral

part of the 3-to-4 wire SPI

conversion). Care must be

exercised at manipulate this

signal with the correct timing.

G12 C2M_CLKGEN_VADJ_CS_N

LA08_P C2M LVCMOS

SPI Bus, Clock Generator

Chip Select (active low)

G13 C2M_ADC1_VADJ_CS_N LA08_N C2M LVCMOS SPI Bus, ADC1 Chip Select

(active low)

D14 C2M_ADC2_VADJ_CS_N LA09_P C2M LVCMOS SPI Bus, ADC2 Chip Select


34 Rev.1.0

J6 Pin



(active low)

D15 C2M_ADC3_VADJ_CS_N LA09_N C2M LVCMOS SPI Bus, ADC3 Chip Select

(active low)

C14 C2M_ADC4_VADJ_CS_N LA10_P C2M

LVCMOS SPI Bus, ADC4 Chip Select

(active low)

C15 C2M_ADC_VADJ_SDIO LA10_N C2M

LVCMOS SPI Bus, ADC bi-directional

data

H16 C2M_CLKGEN_VADJ_SDIO LA11_P C2M

LVCMOS SPI Bus, Clock Generator

bi-directional data

H17 CLKGEN_VADJ_RESET_N LA11_N C2M LVCMOS Clock Generator Reset (active

low)

G15 CLKGEN_VADJ_MAN_SYNC_N LA12_P C2M LVCMOS

Start or stop the internal

SYSREF generator within the

Clock Generator

G16 BUFFER_OE_N LA12_N C2M LVCMOS

Enable the interface

buffers/level translators (active

low)

D17 M2C_ADC1_FDA LA13_P M2C LVCMOS Fast Detect Indicator, Ch. 2

D18 M2C_ADC1_FDB LA13_N M2C LVCMOS Fast Detect Indicator, Ch. 1

C18 M2C_ADC2_FDA LA14_P M2C LVCMOS Fast Detect Indicator, Ch. 4

C19 M2C_ADC2_FDB LA14_N M2C LVCMOS Fast Detect Indicator, Ch. 3

H19 M2C_ADC3_FDA LA15_P M2C LVCMOS Fast Detect Indicator, Ch. 6

H20 M2C_ADC3_FDB LA15_N M2C LVCMOS Fast Detect Indicator, Ch. 5

G18 M2C_ADC4_FDA LA16_P M2C LVCMOS Fast Detect Indicator, Ch. 8

G19 M2C_ADC4_FDB LA16_N M2C LVCMOS Fast Detect Indicator, Ch. 7

D20 ADC4_LVDS_SYNC_P LA17_CC_P C2M LVDS JESD204B, Sync, Ch. 7/8

D21 ADC4_LVDS_SYNC_N LA17_CC_N C2M LVDS

C22 ADC1_LVDS_SYNC_P LA18_CC_P C2M LVDS JESD204B, Sync, Ch. ½

C23 ADC1_LVDS_SYNC_N LA18_CC_N C2M LVDS

H22 C2M_VADJ_SWITCHER_SYNQ1 LA19_P C2M LVCMOS Synchronization clock to the

4V switcher (0º)

H23 C2M_VADJ_SWITCHER_SYNQ2 LA19_N C2M LVCMOS Synchronization clock to the

2.5V switcher (180º)

G21 TROUBLE LA20_P C2M LVCMOS RED LED (active high)

D4 CLK_M2C_FPGA_LVDS1_P GBTCLK0_M2C_P M2C LVDS MGT Reference Clock

D5 CLK_M2C_FPGA_LVDS1_N GBTCLK0_M2C_N M2C LVDS

B20 CLK_M2C_FPGA_LVDS2_P GBTCLK1_M2C_P M2C LVDS MGT Reference Clock

B21 CLK_M2C_FPGA_LVDS2_N GBTCLK1_M2C_N M2C LVDS

C6 ADC3A_CML_P DP0_M2C_P M2C CML JESD204B, High-Speed Serial

Lane, Channel 6 C7 ADC3A_CML_N DP0_M2C_N M2C CML

A2 ADC3B_CML_P DP1_M2C_P M2C CML JESD204B, High-Speed Serial

Lane, Channel 5 A3 ADC3B_CML_N DP1_M2C_N M2C CML

A6 ADC4A_CML_P DP2_M2C_P M2C CML JESD204B, High-Speed Serial

Lane, Channel 8 A7 ADC4A_CML_N DP2_M2C_N M2C CML


35 Rev.1.0

J6 Pin







A18 ADC2A_CML_P DP5_M2C_P M2C CML JESD204B, High-Speed Serial

Lane, Channel 4 A19 ADC2A_CML_N DP5_M2C_N M2C CML

B16 ADC1B_CML_P DP6_M2C_P M2C CML JESD204B, High-Speed Serial

Lane, Channel 1 B17 ADC1B_CML_N DP6_M2C_N M2C CML

B12 ADC1A_CML_P DP7_M2C_P M2C CML JESD204B, High-Speed Serial

Lane, Channel 2 B13 ADC1A_CML_N DP7_M2C_N M2C CML

C30 CLK_FMC_SCL_OD SCL C2M LVTTL OD FMC IPMI EEPROM Clk

C31 FMC_SDA_OD SDA BIDIR LVTTL OD FMC IPMI EEPROM Data

C34 GA0 GA0 C2M LVTTL FMC IPMI EEPROM slave

address select MSB

D35 GA1 GA1 C2M LVTTL FMC IPMI EEPROM slave

address select LSB

D1

PG_C2M

PG_C2M

C2M LVTTL

Power Good. Acts as a power

switch to enable and disable

power to the FMC.

F1

PG_M2C

PG_M2C

M2C LVTTL

Power Good. Indicates that the

two switchers are operating

within tolerance.

H2 GND PRSNT_M2C_N M2C LVTTL Card presence (asserted)

D30 FMC_TDI/FMC_TDO

TDI C2M LVTTL Looped JTAG data to maintain

carrier JTAG loop D31 TDO M2C LVTTL

D29 Open TCK C2M LVTTL Not used

D33 Open TMS C2M LVTTL Not used

D34 Open TRST_N C2M LVTTL Not used

H1 Open VREF_A_M2C M2C N/A Not used

K1 Open VREF_B_M2C M2C N/A Not used

J39 VIO_B_M2C_1/Open VIO_B_M2C M2C N/A Not used

K40 VIO_B_M2C_2/Open VIO_B_M2C M2C N/A Not used


36 Rev.1.0

Note: The AD9250 is a dual channel device. Within the device, the channels are identified as “A” and “B”. Due to the device’s pin assignment and the PCB layout requirement, “A” is actually the higher channel ordinal within the pair. The following table should help clarify the nomenclature.

Table 8-2 Channel naming and numbering explanation

ADC Physical Channel

Intra-ADC identifier

Example

1 1 B

ADC1B… ADC1_FDB…

2 A ADC1A…

ADC1_FDA…

2 3 B


4 A ADC2A…

ADC2_FDA…

3 5 B


6 A ADC3A…

ADC3_FDA…

4 7 B


8 A ADC4A…

ADC4_FDA…

8.9. FMC I2C EEPROM A 2 Kbit I2C EEPROM (M24C02) is provided for FMC identification, as described in section 5.5 of ANSI / VITA 57.1. It is at I2C address 0b1010000x and is connected to the FMC dedicated I2C pins at J6-C30 (SCL) and J6-C31 (SDA). The pull-up resistors to 3V3_AUX are not populated (R3 and R4) since the pull-ups should be provided on the carrier. The EEPROM is permanently enabled for writing. The FMC identification EEPROM is programmed at the factory to enable automated identification, verification, and configuration of Main Board parameters (typically VADJ voltage level). The contents of the EEPROM are described in Appendix A. Note: The user must be cognizant that the FMC I2C EEPROM is always write-enabled. As it contains critical information required for correct operation, one must never overwrite the factory settings. 8.10. Thermal Performance The TB-FMCH-8AD250 dissipates approximately 7W of power. This amount of power, in a small form factor means that significant component temperature rise is unavoidable. To ensure robust performance, the common features of the FMC design in association with the heatsink work to conductively cool the FMC such that all components are maintained well below their maximum junction temperatures within the stated operating temperature range, in natural convection environments. Alternative cooling methods (e.g. forced convection) may be introduced to expand the operational temperature range of the unit, but


37 Rev.1.0

care must be taken, and may void the warranty. For reference, the heatsink mechanical design and thermal images are shown below.

Figure 22: Heat Sink mechanical drawing (for reference only)


38 Rev.1.0

Figure 23: Thermal Image – back side, heatsink installed on component side

(Typical operation: 8-channel, 250MSPS, VADJ=1.8V)


39 Rev.1.0

Figure 24: Thermal Image - component side with heatsink

Note: As depicted in the above thermal images, during and after operation, the TB-FMCH-8AD250 unit experiences significant temperature rise. Unit may be hot to the touch. Handle with care.


40 Rev.1.0

9. Appendix A: FMC I2C EEPROM The following table describes the contents of the FMC I2C EEPROM as programmed at the factory.

Table 9-1 FMC I2C EEPROM Contents

Board Information Field Size Data

Language Code 1 0 Date / Time of Manufacture 3 <Variable> Board Manufacturer 16 FidusSystemsInc Board Product Name 16 TB-FMCH-8AD250 Board Serial Number 16 <Variable> Board Part Number 16 PA-10193-01 FRU File ID 1 0 Hardware Revision 6 <Variable> MAC Address 6 00:00:00:00:00:00

Multi-Record Information VITA Subtype 0 Record

Field Size Data Description Vendor OUI 3 0x0012A2 Fixed value of 0x0012A2 Subtype/Version 1 0x00 7:4 (type): main definition type

3:0 (version): current version Size/Connectors/Clock Dir 1 0x1C 7:6 (size): single width

5:4 (P1 size): HPC 3:2 (P2 size): not fitted 0 (clock dir): Mezzanine to Carrier 0: reserved 0

P1 Bank A Number Signals 1 0x29 41 signals P1 Bank B Number Signals 1 0x00 P2 Bank A Number Signals 1 0x00 P2 Bank B Number Signals 1 0x00 P1/P2 Number Transceivers 1 0x00 Max Clock for TCK 1 0x95 In units of MHz: 149MHz


41 Rev.1.0

DC Load Record – VADJ Field Size Data Description

Output Information 1 0x00 Bit map containing output number, etc. (VADJ) Nominal Voltage 2 0x00B4 In units of 10mV (1.8V) Minimum Voltage 2 0x0078 In units of 10mV (1.2V) Maximum Voltage 2 0x014A In units of 10mV (3.3V) Ripple and Noise (PK-PK) 2 0x0032 In units of 1mV (10Hz to 30MHz) (50mV) Minimum Current Draw 2 0x0005 In units of 1mA (5mA) Maximum Current Draw 2 0x0064 In units of 1mA (100mA) DC Load Record – 3P3V

Field Size Data Description Output Information 1 0x01 Bit map containing output number, etc. (3.3V) Nominal Voltage 2 0x014A In units of 10mV (3.3V) Minimum Voltage 2 0x0139 In units of 10mV (3.13V) Maximum Voltage 2 0x0154 In units of 10mV (3.4V) Ripple and Noise (PK-PK) 2 0x0032 In units of 1mV (10Hz to 30MHz) (50mV) Minimum Current Draw 2 0x000F In units of 1mA (15mA) Maximum Current Draw 2 0x0064 In units of 1mA (100mA) DC Load Record – 12P0V

Field Size Data Description Output Information 1 0x02 Bit map containing output number, etc. (12V) Nominal Voltage 2 0x04B0 In units of 10mV (12V) Minimum Voltage 2 0x0474 In units of 10mV (11.4V) Maximum Voltage 2 0x04EC In units of 10mV (12.6V) Ripple and Noise (PK-PK) 2 0x0064 In units of 1mV (10Hz to 30MHz) (100mV) Minimum Current Draw 2 0x01F4 In units of 1mA (500mA) Maximum Current Draw 2 0x02EE In units of 1mA (750mA) DC Output Record – VIO_B_M2C (NOT CONNECTED ON TB-FMCH-8AD250)

Field Size Data Description Output Information 1 0x03 Bit map containing output number, etc. Nominal Voltage 2 0x0000 In units of 10mV Minimum Voltage 2 0x0000 In units of 10mV Maximum Voltage 2 0x0000 In units of 10mV Ripple and Noise (PK-PK) 2 0x0000 In units of 1mV (10Hz to 30MHz) Minimum Current Load 2 0x0000 In units of 1mA Maximum Current Load 2 0x0000 In units of 1mA


42 Rev.1.0

DC Output Record – VREF_A_M2C (NOT CONNECTED ON TB-FMCH-8AD250) Field Size Data Description

Output Information 1 0x04 Bit map containing output number, etc. Nominal Voltage 2 0x0000 In units of 10mV Minimum Voltage 2 0x0000 In units of 10mV Maximum Voltage 2 0x0000 In units of 10mV Ripple and Noise (PK-PK) 2 0x0000 In units of 1mV (10Hz to 30MHz) Minimum Current Load 2 0x0000 In units of 1mA Maximum Current Load 2 0x0000 In units of 1mA DC Output Record – VREF_B_M2C (NOT CONNECTED ON TB-FMCH-8AD250)

Field Size Data Description Output Information 1 0x05 Bit map containing output number, etc. Nominal Voltage 2 0x0000 In units of 10mV Minimum Voltage 2 0x0000 In units of 10mV Maximum Voltage 2 0x0000 In units of 10mV Ripple and Noise (PK-PK) 2 0x0000 In units of 1mV (10Hz to 30MHz) Minimum Current Load 2 0x0000 In units of 1mA Maximum Current Load 2 0x0000 In units of 1mA


43 Rev.1.0

10. Appendix B: TB-FMCH-8AD250 Quick Start A reference “.bit” FPGA configuration file is available for the Xilinx VC707 board. This provides default configuration settings for the AD9528 clock generator chip, the four AD9250 ADC chips, and the JESD204B IP core. A command line / UART connection is also provided for register access. All FPGA development for this reference design was done in release 2016.1 of the Xilinx Vivado tool. Please ask your sales contact for additional information. 10.1. VC707 (FMC2) Pin Assignment The figure below shows the FMC connections between the VC707 (FMC2) and the TB-FMCH-8AD250. Unshaded cells are "No Connect" (NC) and list the VITA name. Shaded cells list the VITA name followed by TB-FMCH-8AD250 connection details and VC707 FPGA pin number (in brackets). Note that the FPGA pin numbers correspond ONLY to the FMC2 (J37) HPC connector.


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VREF_B_M2C GND VREF_A_M2C GNDPG_M2C (AF29) GND PG_C2M (AL32) GND

CLK_DIR: 3P3V_FMC_10K_PU (NC) GND

GND CLK3_BIDIR_PPRSNT_M2C_L: PRSNT_M2C_L

(GND) (AG32)

CLK1_M2C_P: CLK_M2C_FPGA_LVDS_SYSREF_P

(U39) GND HA01_P_CC GND DP0_C2M_P GND

DP1_M2C_P: ADC3B_CML_P

(N6)

GND CLK3_BIDIR_N GND

CLK1_M2C_N: CLK_M2C_FPGA_LVDS_SYSREF_N

(T39) GND HA01_N_CC GND DP0_C2M_N GND

DP1_M2C_N: ADC3B_CML_N

(N5)

CLK2_BIDIR_P GND

CLK0_M2C_P: CLK_M2C_FPGA_LVDS3_P

(AF39) GND HA00_P_CC GNDGBTCLK0_M2C_P:

CLK_M2C_FPGA_LVDS1_P (K8) GND DP9_M2C_P GND

CLK2_BIDIR_N GND

CLK0_M2C_N: CLK_M2C_FPGA_LVDS3_N

(AF40) GND HA00_N_CC GND

GBTCLK0_M2C_N: CLK_M2C_FPGA_LVDS1_N

(K7) GND DP9_M2C_N GND

GND HA03_P GNDLA00_P_CC: ADC2_LVDS_SYNC_P

(AD40) GND HA05_P GNDDP0_M2C_P: ADC3A_CML_P

(P8) GND

DP2_M2C_P: ADC4A_CML_P

(L6)

HA02_P HA03_NLA02_P: C2M_ADC_PWDN

(AK39)LA00_N_CC: ADC2_LVDS_SYNC_N

(AD41) HA04_P HA05_N GNDDP0_M2C_N: ADC3A_CML_N

(P7) GND

DP2_M2C_N: ADC4A_CML_N

(L5)

HA02_N GNDLA02_N: C2M_ADC_RST_N

(AL39) GND HA04_N GNDLA01_P_CC:

ADC3_LVDS_SYNC_P (AF41) GND DP8_M2C_P GND

GND HA07_P GNDLA03_P: CLK_C2M_REFCLKP

(AJ42) GND HA09_PLA01_N_CC:

ADC3_LVDS_SYNC_N (AG41) GND DP8_M2C_N GND

HA06_P HA07_N LA04_P: SYSREF_P (AL41)LA03_N: CLK_C2M_REFCLKN

(AK42) HA08_P HA09_N GNDLA06_P: C2M_TRIGGERP

(AD38) GND


(J6)

HA06_N GND LA04_N: SYSREF_N (AL42) GND HA08_N GNDLA05_P: M2C_TRIGGERP

(AF42)LA06_N: C2M_TRIGGERN

(AE38) GND


(J5)

GND HA11_P GND

LA08_P: C2M_CLKGEN_VADJ_CS_N

(AD42) GND HA13_PLA05_N: M2C_TRIGGERN

(AG42) GNDDP7_M2C_P: ADC1A_CML_P

(R6) GND

HA10_P HA11_NLA07_P: C2M_VADJ_SCLK

(AC40)LA08_N: C2M_ADC1_VADJ_CS_N

(AE42) HA12_P HA13_N GND GNDDP7_M2C_N:

ADC1A_CML_N (R5) GND

HA10_N GNDLA07_N: C2M_VADJ_SDIO_DIR

(AC41) GND HA12_N GND

LA09_P: C2M_ADC2_VADJ_CS_N

(AJ38)

LA10_P: C2M_ADC4_VADJ_CS_N

(AB41) GND


(W6)

GND HA14_P GND

LA12_P: CLKGEN_VADJ_MAN_SYNC_N

(Y39) GND HA16_P

LA09_N: C2M_ADC3_VADJ_CS_N

(AK38)LA10_N:

C2M_ADC_VADJ_SDIO (AB42) GND


(W5)

HA17_P_CC HA14_N

LA11_P: C2M_CLKGEN_VADJ_SDIO

(Y42) LA12_N: BUFFER_OE_N (AA39) HA15_P HA16_N GND GNDDP6_M2C_P: ADC1B_CML_P

(U6) GND

HA17_N_CC GND

LA11_N: CLKGEN_VADJ_RESET_N

(AA42) GND HA15_N GNDLA13_P: M2C_ADC1_FDA

(W40) GNDDP6_M2C_N:

ADC1B_CML_N (U5) GND

GND HA18_P GND LA16_P: M2C_ADC4_FDA (AJ40) GND HA20_P LA13_N: M2C_ADC1_FDB (Y40)LA14_P: M2C_ADC2_FDA

(AB38) GND

DP5_M2C_P: ADC2A_CML_P

(V4)

HA21_P HA18_NLA15_P: M2C_ADC3_FDA

(AC38) LA16_N: M2C_ADC4_FDB (AJ41) HA19_P HA20_N GNDLA14_N: M2C_ADC2_FDB

(AB39) GND

DP5_M2C_N: ADC2A_CML_N

(V3)

HA21_N GNDLA15_N: M2C_ADC3_FDB

(AC39) GND HA19_N GNDLA17_P_CC:

ADC4_LVDS_SYNC_P (U37) GND

GBTCLK1_M2C_P: CLK_M2C_FPGA_LVDS2_P

(T8) GND

GND HA22_P GND LA20_P: TROUBLE (V33) GND HB03_PLA17_N_CC:

ADC4_LVDS_SYNC_N (U38) GND

GBTCLK1_M2C_N: CLK_M2C_FPGA_LVDS2_N

(T7) GND

HA23_P HA22_N

LA19_P: C2M_VADJ_SWITCHER_SYNQ1

(U32) LA20_N HB02_P HB03_N GNDLA18_P_CC:

ADC1_LVDS_SYNC_P (U36) GND DP1_C2M_P

HA23_N GND

LA19_N: C2M_VADJ_SWITCHER_SYNQ2

(U33) GND HB02_N GND LA23_PLA18_N_CC:

ADC1_LVDS_SYNC_N (T37) GND DP1_C2M_NGND HB01_P GND LA22_P GND HB05_P LA23_N GND DP9_C2M_P GND

HB00_P_CC HB01_N LA21_P LA22_N HB04_P HB05_N GND GND DP9_C2M_N GNDHB00_N_CC GND LA21_N GND HB04_N GND LA26_P LA27_P GND DP2_C2M_P

GND HB07_P GND LA25_P GND HB09_P LA26_N LA27_N GND DP2_C2M_NHB06_P_CC HB07_N LA24_P LA25_N HB08_P HB09_N GND GND DP8_C2M_P GNDHB06_N_CC GND LA24_N GND HB08_N GND TCK GND DP8_C2M_N GND

GND HB11_P GND LA29_P GND HB13_P TDI: FMC_TDI SCL: CLK_FMC_SCL_OD GND DP3_C2M_PHB10_P HB11_N LA28_P LA29_N HB12_P HB13_N TDO: FMC_TDO SDA: FMC_SDA_OD GND DP3_C2M_NHB10_N GND LA28_N GND HB12_N GND 3P3VAUX: 3V3_AUX GND DP7_C2M_P GNDGND HB15_P GND LA31_P GND HB19_P TMS GND DP7_C2M_N GND

HB14_P HB15_N LA30_P LA31_N HB16_P HB19_N TRST_L GA0: GA0_1K3 GND DP4_C2M_PHB14_N GND LA30_N GND HB16_N GND GA1: GA1_1K3 12P0V: 12V0_P GND DP4_C2M_NGND HB18_P GND LA33_P GND HB21_P 3P3V: 3V3_P GND DP6_C2M_P GND

HB17_P_CC HB18_N LA32_P LA33_N HB20_P HB21_N GND 12P0V: 12V0_P DP6_C2M_N GNDHB17_N_CC GND LA32_N GND HB20_N GND 3P3V: 3V3_P GND GND DP5_C2M_P

GNDVIO_B_M2C:

3V3_VIO_B_M2C GND VADJ: FMC_VADJ GNDVADJ:

FMC_VADJ GND 3P3V: 3V3_P GND DP5_C2M_NVIO_B_M2C:

3V3_VIO_B_M2C GND VADJ: FMC_VADJ GNDVADJ:

FMC_VADJ GND 3P3V: 3V3_P GND RES0 GND

Figure 25: FMC HPC Connector Pinout (FMC2 on VC707)

10.2. Demonstration Set-up The following steps can be followed as a quick start to demonstrate default operation of the TB-FMCH-8AD250 using the reference design:

(1) Install the TB-FMCH-8AD250 on the FMC2 connector on a Xilinx VC707 board. Make sure power is OFF on the VC707 before making this connection

(2) Set the DIP switches on the VC707 so that JTAG FPGA programming is supported (3) Attach JTAG / USB and UART / USB connectors to the VC707 and to a host computer (4) Power up the VC707


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(5) Start a terminal session using Tera Term (or similar terminal emulator). Select the “COM” port displaying the Silicon Labs USB UART. Configure the connection for a speed of 115,200 baud, 8 data bits, 1 stop bit, no parity bit, and no flow control. Set a character delay of 1 ms and a line delay of 100 ms.

(6) Open a Vivado Hardware Manager session (7) Select a new connection (and all the associated defaults) if this is the first time connecting the

host PC to the particular VC707, otherwise select a previous connection. If you have difficulties with using a previous connection, then establish a new connection.

(8) Right-click on the FPGA part number in the hierarchy pane and select “Program”. A dialog box will open asking for the “.bit” and “.ltx” files. Navigate to the “download.bit” file and select it, then navigate to the “debug_probes.ltx” file and select it, then “OK” to program the FPGA. Note that the Tcl console screen will indicate clock issues for the ILA at this point since there is no appropriate clock coming from the TB-FMCH-8AD250 yet.

(9) When programming completes, you should see a live command line on the terminal screen. Type “init” to load a default configuration into all system registers2. You can also make changes to the default values at the command line or enter the entire configuration script using cut-paste on the command line.

(10) In the Vivado IDE, select “Refresh” to update the status of the FPGA. The ILA clock issues on the Tcl command line should be resolved.

(11) Trigger the ILA by clicking the double arrow icon (>>). This will bring 8 lanes of ADC data into the display. You can then change the format of the data display to “analog” and the number format to “signed”. If you have signals feeding any of the ADC inputs, you should now see their waveforms.

2 The “init” command is not currently supported. The user must configure the reference design by playing back the provided scripts.


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11. Appendix C: Configuration Details for the AD9528 The following figures capture the configuration details for the AD9528 clock generator chip. The screen shots below are from the Analog Devices software used to generate the configuration parameters.


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