TB OK D21 Hardware User Manual...Turn off main power and allow to cool before handling. Warning! ! ! ! ! ! ! TB-OK-D21 Hardware User Manual Rev. 1.03 8 Do not use or place the product

TB-OK-D21 Hardware User Manual

1 Rev. 1.03


Rev. 1.03


2 Rev. 1.03

Revision History

Version Date Description Publisher

Rev. 1.00 2019/6/28 Initial Release Kazu, ST

Rev. 1.01 2019/6/28 Update 10.4 EMCCLK Kazu

Rev. 1.02 2019/7/01 Update DDR4 part number on section 4 and 10.6 Kazu

Rev. 1.03 2019/11/01 Change the EEPROM to “not populated” in “10.9.

General Purpose EEPROM”

Revise the pin name of the PLL output in “Figure 9-5

Onboard PLLs”

Added note 10,11 and 12 to “9.5. FMC+ connectors”

Kazu


3 Rev. 1.03

Table of Contents

1. Related Documents ..................................................................................................................... 9

2. Accessories ................................................................................................................................. 9

3. Overview .................................................................................................................................... 10

4. Features ...................................................................................................................................... 11

5. Block Diagram of TB-OC-D21 ................................................................................................... 12

6. Block Diagram of IM-B20 Origami Module ................................................................................ 14

7. External View of TB-OK-D21 ..................................................................................................... 15

8. Board Specifications of TB-OC-D21 ......................................................................................... 16

9. Description of Components on TB-OC-D21 .............................................................................. 17

9.1. Power supply structure ............................................................................................................. 17

9.2. Power Sequencing ................................................................................................................... 17

9.3. Power input connector .............................................................................................................. 18

9.4. Reset ........................................................................................................................................ 18

9.5. FMC+ connectors ..................................................................................................................... 19

9.6. Onboard PLL ............................................................................................................................ 30

9.7. Crystal Oscillator ...................................................................................................................... 32

9.8. JTAG-over-USB ........................................................................................................................ 32

9.9. UART-over-USB ....................................................................................................................... 33

9.10. General Purpose LEDs......................................................................................................... 33

9.11. Pin Header ............................................................................................................................ 34

9.12. Push-button Switch ............................................................................................................... 34

9.13. DIP Switch ............................................................................................................................ 35

9.14. Test Pads .............................................................................................................................. 35

10. Description of Components on IM-B20 Origami Module ...................................................... 36

10.1. General Purpose LEDs on IM-B20 ....................................................................................... 36

10.2. 200MHz System Clock ......................................................................................................... 37

10.3. 300MHz System Clock ......................................................................................................... 37

10.4. EMCCLK ............................................................................................................................... 38

10.5. Configuration Memory .......................................................................................................... 40

10.6. DDR4 .................................................................................................................................... 41

10.7. Voltage source (onboard ADC) for V_P and V_N pin .......................................................... 41

10.8. Real Time Clock ................................................................................................................... 42

10.9. General Purpose EEPROM .................................................................................................. 43

10.10. Temperature Sensor ............................................................................................................. 44

10.11. Resistor network ................................................................................................................... 45


4 Rev. 1.03

List of Figures

Figure 5-1 System Block Diagram ................................................................................................... 12

Figure 5-2 Clock Sub-System Diagram............................................................................................ 13

Figure 6-1 IM-B20 Origami Module block diagram .......................................................................... 14

Figure 7-1 D21 Board Top View ....................................................................................................... 15

Figure 8-1 D21 Dimensions (unit: mm) ............................................................................................ 16

Figure 9-1 Power supply structure ................................................................................................... 17

Figure 9-2 Power Input ..................................................................................................................... 18

Figure 9-3 Reset ............................................................................................................................... 18

Figure 9-4 FMC+ pinout ................................................................................................................... 19

Figure 9-5 Onboard PLLs ................................................................................................................. 30

Figure 9-6 Crystal Oscillator ............................................................................................................. 32

Figure 9-6 General Purpose LED ..................................................................................................... 33

Figure 9-7 Pin Header ...................................................................................................................... 34

Figure 9-8 Push-button Switch ......................................................................................................... 34

Figure 9-9 DIP Switch ...................................................................................................................... 35

Figure 10-1 General Purpose LEDs ................................................................................................. 36

Figure 10-2 200MHz System Clock ................................................................................................. 37

Figure 10-3 300MHz System Clock ................................................................................................. 37

Figure 10-4 133MHz EMCCLK (TB-OK-D21(JP) 2.0.00) ................................................................ 38

Figure 10-4 80MHz EMCCLK(TB-OK-D21(JP) 2.1.00) ................................................................... 38

Figure 10-5 NOR Flash (TB-OK-D21(JP) 2.0.00) ............................................................................ 40

Figure 10-5 QSPI Flash (TB-OK-D21(JP) 2.1.00) ........................................................................... 40

Figure 10-6 Voltage source for V_P and V_N .................................................................................. 41

Figure 10-7 Real Time Clock ............................................................................................................ 42

Figure 10-8 General Purpose EEPROM (TB-OK-D21(JP) Rev 2.0.00 ) ......................................... 43

Figure 10-8 General Purpose EEPROM (TB-OK-D21(JP) Rev 2.1.00 ) ......................................... 43

Figure 10-9 Temperature Sensor ..................................................................................................... 44

Figure 10-10 Resistor networks ....................................................................................................... 45


5 Rev. 1.03

List of Tables

Table 2-1 Accessories ........................................................................................................................ 9

Table 9-1 FMC+ J17 Pinout .............................................................................................................. 20

Table 9-2 FMC+ J18 Pinout .............................................................................................................. 25

Table 9-3 U17 pinout ........................................................................................................................ 31

Table 9-4 U317 pinout ...................................................................................................................... 31

Table 9-5 Y303 pinout ...................................................................................................................... 32

Table 9-6 Y304 pinout ...................................................................................................................... 32

Table 9-7 UART-over-USB pinout .................................................................................................... 33

Table 9-8 General purpose LEDs pinout .......................................................................................... 33

Table 9-9 Pin header pinout ............................................................................................................. 34

Table 9-10 Push-button Switch pinout .............................................................................................. 34

Table 9-11 DIP Switch pinout ........................................................................................................... 35

Table 10-1 General Purpose LEDs pinout ....................................................................................... 36

Table 10-2 200MHz System Clock ................................................................................................... 37

Table 10-3 300MHz System Clock ................................................................................................... 37

Table 10-4 EMCCLK pinout .............................................................................................................. 38

Table 10-5 Real Time Clock pinout .................................................................................................. 42

Table 10-6 General Purpose EEPROM pinout ................................................................................. 43

Table 10-7 Temperature sensor ....................................................................................................... 44

Table 10-8 Resistor networks ........................................................................................................... 46


6 Rev. 1.03

Introduction Thank you for purchasing the TB-OK-D21 board. Before using the product, be sure to carefully read

this user manual and fully understand how to use the product correctly. First read through this manual,

and always keep it handy.

SAFETY PRECAUTIONS Be sure to follow these precautions

Observe the precautions listed below to prevent injuries to you or other personnel or damage to property.

• Before using the product, read these safety precautions carefully to ensure proper use.

• These precautions contain serious safety instructions that must be followed.

• After reading through this manual, be sure to always keep it handy.

The following conventions are used to indicate the possibility of injury/damage and classify precautions if

the product is handled incorrectly.

Indicates the high possibility of serious injury or death if the product is handled

incorrectly.

Indicates the possibility of serious injury or death if the product is handled

incorrectly.

Indicates the possibility of injury or physical damage in connection with houses or

household goods if the product is handled incorrectly.

The following graphical symbols are used to indicate and classify precautions in this manual.

(Examples)

Turn off the power switch.

Do not disassemble the product.

Do not attempt this.

Danger

Warning

Caution

!


7 Rev. 1.03

In the event of a failure, disconnect the power supply.

If the product is used as is, a fire or electric shock may occur. Disconnect the power supply

immediately and contact our sales personnel for repair.

If an unpleasant smell or smoking occurs, disconnect the power supply.

If the product is used as is, a fire or electric shock may occur. Disconnect the power supply

immediately. After verifying that no smoking is observed, contact our sales personnel for

repair.

Do not disassemble, repair or modify the product.

Otherwise, a fire or electric shock may occur due to a short circuit or heat generation. For

inspection, modification or repair, contact our sales personnel.

Do not place the product and AC desktop adapter on unstable locations.

Otherwise, it may drop or fall, resulting in injury to persons or failure.

If the product is dropped or damaged, do not use it as is.

Otherwise, a fire or electric shock may occur.

Do not touch the product with a metallic object.


Do not place the product in dusty or humid locations or where water may

splash.


Do not get the product wet or touch it with a wet hand.

Otherwise, the product may break down or it may cause a fire, smoking or electric shock.

Do not touch a connector on the product (gold-plated portion).

Otherwise, the surface of a connector may be contaminated with sweat or skin oil, resulting

in contact failure of a connector or it may cause a malfunction, fire or electric shock due to

static electricity.

Do not touch the product with hands

Hot surface can cause burns. Turn off main power and allow to cool before

handling.

Warning

!

!

!

!

!

!

!


8 Rev. 1.03

Do not use or place the product in the following locations.

• Humid, high temperature higher than 85 degrees Fahrenheit (30 degrees Celsius) and dusty

locations

• Airless locations such as closet or bookshelf

• Locations which receive oily smoke or steam

• Locations exposed to direct sunlight

• Locations close to heating equipment

• Closed inside of a car where the temperature becomes high

• Staticky locations

• Locations close to water or chemicals

Otherwise, a fire, electric shock, accident or deformation may occur due to a short circuit or heat

generation.

Do not place heavy things on the product.

Otherwise, the product may be damaged.

■ Disclaimer

This product is an evaluation board intended for development of video interface. Tokyo Electron Device

Limited assumes no responsibility for any damages resulting from the use of this product for purposes

other than those stated.

Even if the product is used properly, Tokyo Electron Device Limited assumes no responsibility for any

damages caused by:

(1) Earthquake, thunder, natural disaster or fire resulting from the use beyond our responsibility, acts by

a third party or other accidents, the customer’s willful or accidental misuse or use under other

abnormal conditions.

(2) Secondary impact arising from use of this product or its unusable state (business interruption or

others)

(3) Use of this product against the instructions given in this manual.

(4) Malfunctions due to connection to other devices.

Tokyo Electron Device Limited assumes no responsibility or liability for:

(1) Erasure or corruption of data arising from use of this product.

(2) Any consequences or other abnormalities arising from use of this product, or

(3) Damage of this product not due to our responsibility or failure due to modification

This product has been developed by assuming its use for research, testing or evaluation. It is not

authorized for use in any system or application that requires high reliability.

Repair of this product is carried out by replacing it on a chargeable basis, not repairing the faulty devices.

However, non-chargeable replacement is offered for initial failure if such notification is received within

two weeks after delivery of the product.

The specification of this product is subject to change without prior notice.

The product is subject to discontinuation without prior notice.

Caution

!

!


9 Rev. 1.03

1. Related Documents

The latest version of the hardware user manual can be downloaded from Inrevium website at

http://solutions.inrevium.com/

Technical documents related to the IM-B20 Origami Module are provided under NDA. Please contact

your distributor for more information.

Xilinx FPGA documents can be downloaded from:

http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/kintex-ultras

cale.html

2. Accessories

The following table lists the accessories that are included:

Table 2-1 Accessories

Description Manufacturer Quantity

Desktop power adapter (252W,12V,PN:GST280A12-C6P) or equivalent Mean Well 1

TB-OK-D21 :

AC cord (18AWG NEMA5-15P - IEC320 3, PN: P006-003) or equivalent

TB-OK-D21JP:

AC cord(NEMA5-15P - IEC 320-C13 6', PN: AC-C13 JP) or equivalent

Tripp Lite

CUI Inc. 1

USB2.0 Type A TO MICRO-USB TypeB 6' (PN : U050-006) or equivalent Tripp Lite 2


http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/kintex-ultrascale.html

http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/kintex-ultrascale.html


10 Rev. 1.03

3. Overview

The TB-OK-D21(JP), IM-B20 Origami Module Evaluation Platform, enables users to evaluate,

experiment, build, and target designs destined for Xilinx Kintex UltraScale FPGAs. The Kintex UltraScale

FPGA is populated on the pre-installed IM-B20 Origami Module. The D21 Carrier is provisioned with

several peripherals and two FMC+ expansion ports. The combination of a large scale Kintex UltraScale

FPGA and carefully selected peripherals make the board a flexible solution for jump-starting your FPGA

design, and de-risking your program.

Two, nearly identical, part numbers are available for ordering:

1. TB-OK-D21: Includes the D21 Carrier board (PN: TB-OC-D21) and the IM-B20 Origami Module

(OM-B20-Z2-KU-060). This package is sold with a North American power cord.

or

2. TB-OK-D21JP: Includes the D21 Carrier board (PN: TB-OC-D21) and the IM-B20 Origami

Module (OM-B20-Z2-KU-060). This package is sold with a Japanese power code.

For out of the box operation, regardless of the part number ordered, the Origami Module is

factory-installed on to the D21 Carrier via the Z-ray high-speed, high-density connector.

The D21 Carrier (PN: TB-OC-D21) is typically not sold individually. If you have questions, please contact

Tokyo Electron Device sales.

Note 1: D21 has been tested with inrevium HDMI2.0 FMC, 12G-SDI FMC and DisplayPort 1.4 FMC.

Compatibility with the other boards is not guaranteed. To confirm other FMC(+) compatibility, contact

Tokyo Electron Device sales prior to purchase.

Note 2: The TB-OK-D21(JP) is fully assembled at the factory. Disassembling any portion, including

removing the Origami Module, will void the Manufacturer’s Warranty.

Note 3: FMC(+) cards are not hot swappable. Hotswapping FMC(+) cards may result in permanagent

damage to the TB-OK-D21 and/or the FMC(+) card. Hotswapping the FMC(+) voids the Manufacturer’s

Warranty. Prior to installing or removing FMC(+) card(s), ensure that the power is turned-off and wait at

least 10 seconds.

Note 4: The board specification and Information in the technical documents are subject to change

without notice.

Note 5: RoHS/REACH Certificate of Compliance (CoC) cannot be issued for this product.

Note 6: Regardless of the type of AC cable and AC Adapter included with the purchase, the customer is

responsible for selecting and utilizing an AC cable and AC Adapter that are appropriate and Certified for

use in his/her respective location.

Note 7: To avoid unexpected behavior and the potential of permanent damage, please do not touch the

board during operation.

Note 8: For ease of use, a JTAG-over-USB module is populated on the board. The traditional 14pin

JTAG header is not supported.

Note 9: FMC(+) cards can consume significant power. As the TB-OK-D21 is a development platform, the

user is responsible for, and must be aware of, the power consumption of the provisioned D21 Carrier

board, and ensuring that the entire Platform is adequately cooled.

Note 10: Please refer to the notes described in each section to find technical limitations.


11 Rev. 1.03

4. Features

TB-OC-D21 carrier:

- Z-RAY x 1 supports IM-B20 Origami Module (Custom part)

- FMC+/HSPC x 2（with functional limitations) (PN: ASP-184329-01)

- Clock generator AD9578 x 2 for Gigabit Transceivers (PN: AD9578BCPZ)

- 156.25 Mhz Oscillator for Gigabit Transceivers (PN: 531BC156M250DG)

- JTAG-over-USB

- UART-over-USB

- 12V power input

- DIP Switch (2 position, general purpose), Push Button Switch , LEDs, Pin Headers

IM-B20 Origami Module:

- Z-RAY x 1 (Custom part)

- Xilinx Kintex UltraScale FPGA : XCKU060 -2 speed grade in FFVA1156 package (PN:

XCKU060-2FFVA1156E)

- Gigabit Transceiver x 28

- 200 MHz Oscillator for FPGA fabric (PN: SG3225VAN 200.000000M-KEGA3)

- 300 MHz Oscillator for FPGA fabric (PN: DSC1103CI5-300.0000)

- 4GByte DDR4 SDRAM: 16Gbits per bank x 2 banks (4 chips x 256Mbits depth x 16 width) (PN:

H5AN4G6NAFR-UHC or equivalent )

- 1 Gbit Parallel NOR Flash x1(PN: PC28F00AP30BFA ) or 512 Gbit x 2 Serial NOR Flash for

configuration (PN: MT25QU512ABB8E12-0SIT)


12 Rev. 1.03

5. Block Diagram of TB-OC-D21

The System Block diagram and clock sub-system are shown in Figure 5-1 and Figure 5-2.

MGTREFCLK0_P/N for GTH bank 228 and MGTREFCLK1_P/N for GTH bank 224 are not connected to

the FMC(+) connectors, and cannot be used.

DP[15:0]

16ch GTH +

4 pair of reference CLKs

J17

(FMC+)

J18

(FMC+)

Power

CLK generator

AD9578

12V

USB-UART

CP2102NMicroUSB

12V

3.3V

Power for

FMC+s

DP[11:0]

12ch GTH +

3 pair of reference CLKs

LA[33:0]

6 differential pairs + 56 IOs

+

2pairs of CLK

DP[3:0] GTH224

DP[7:4] GTH225

DP[11:8] GTH226

DP[15:12] GTH227

DP[3:0] GTH127

DP[7:4] GTH128

DP[11:8] GTH228

DP[15:12] no assign

LA[33:0]

9 differential pairs + 50 IOs +

2pairs of CLKs

Bank 67,68

Bank 66,67

CLK generator

AD9578

Xtal

(156.25MHz)

Xtal

(156.25MHz)

JTAGDigilent

JTAG module

Dip SW (2bit)

LED (3bit)

Pin Header (2bit)

Bank 64

CLKx_BIDIR_P/N

REFCLK_x2x_P/N

SYNC_x2x_P/N

12 IOs

Bank 64

SCL/SDA

2 IOs

Bank 64

CLKx_BIDIR_P/N

REFCLK_x2x_P/N

SYNC_x2x_P/N

12 IOs

Bank 64

SCL/SDA

2 IOs

Push SW (1bit)

3.0V

IM-B20 Origami Module

on Z-ray connector

Figure 5-1 System Block Diagram


13 Rev. 1.03

GTH 224

MGTREFCLK0_P/N

GTH 225

MGTREFCLK0_P/N

MGTREFCLK1_P/N

GTH 127

MGTREFCLK0_P/N

MGTREFCLK1_P/N

GTH 128

MGTREFCLK0_P/N

MGTREFCLK1_P/N

GBTCLK0_M2C_P/N

GBTCLK1_M2C_P/N

GBTCLK0_M2C_P/N

GBTCLK1_M2C_P/N

J17

(FMC+)

J18

(FMC+)U17 (On

Board PLL

(AD9578))

Y303 (Xtal)

(156.25MHz)

GTH 226

GTH 227

MGTREFCLK0_P/N

MGTREFCLK1_P/N

GTH 228

MGTREFCLK1_P/N

MGTREFCLK0_P/N

MGTREFCLK1_P/N

GBTCLK2_M2C_P/N

GBTCLK3_M2C_P/N

GBTCLK2_M2C_P/N

J17

(FMC+)

J18

(FMC+)

U317 (On

Board PLL

(AD9578))

Y304 (Xtal)

(156.25MHz)　

Clock to fabric

Clock from fabric

Clock from fabric

Z

-

R

A

Y

Figure 5-2 Clock Sub-System Diagram


14 Rev. 1.03

6. Block Diagram of IM-B20 Origami Module

The IM-B20 block diagram is shown in Figure 6-1. Note that batteries for Vbat and RTC and EEPROM

are not populated. Program Flash type and bus width depend on D21 board revision.

Figure 6-1 IM-B20 Origami Module block diagram


15 Rev. 1.03

7. External View of TB-OK-D21

Onboard components are shown on the top side view in Figure 7-1

Figure 7-1 D21 Board Top View

Power input

USB UART

Power

Switch

USB

JTAG

IM-B20

Origami

Module

DIP SW

Push SW

Pin

headers

FMC+

J18

FMC+

J17

General

Purpose

LEDs

General Purpose LEDs

on IM-B20 module


16 Rev. 1.03

8. Board Specifications of TB-OC-D21

Figure 8-1 shows D21 Dimensions.

Dimensions : 150mm x 169mm

Number of layers : 18-layer

Thickness : 2.07mm

Material : Panasonic R-5670K Megtron 6 prepreg, R-5775K Megtron 6

Figure 8-1 D21 Dimensions (unit: mm)


17 Rev. 1.03

9. Description of Components on TB-OC-D21

9.1. Power supply structure

D21 Power supply structure is shown in Figure 9-1.

12V input39-30-1060 or

equivalent

LTM8055 (7A)

12V to 3.3V

LTM4649 (10A)

12V to 1.8V

LDO

TPS7A4901

12V to 3.0V3.0V for Origami VBAT (0.01A)

7A

8.1A

0.01A

7A

1.5A

0.01A

2.4A

10.91A

USB-UART

Bus power 5V

USB-UART

Bridge

CP2102N

0.01A

LTC4210Power control/

Overcurrent protection/

Soft start

Power SW

VCC_12P0V

ORIGAMI module 12V (4.5A)

FMC 12V (2A)

FAN 12V (0.5A)

ORIGAMI module 3.3V (0.5A)

FMC 3.3V (6A)

D21 onboard peripheral 3.3V (0.5A)

D21 onboard peripheral 1.8V (0.1A)

FMC VADJ fixed 1.8V (8A)

VCC_3P3V

1V8_VCCAUX

3V0_VBAT

Figure 9-1 Power supply structure

9.2. Power Sequencing

3.3V and 3.0V power supply are always enabled. 1.8V power supply is enabled when the ‘ORI_PWRGD’

signal coming from Z-ray pin V17 is high. ‘ORI_PWRGD’ indicates that the power sequencing on the

IM-B20 Module is complete.


18 Rev. 1.03

9.3. Power input connector

The power input circuitry is shown in the figure below. Please do not connect any power source to the

connector other than the desktop adapter bundled with D21.

Figure 9-2 Power Input

9.4. Reset

The following sequence defines the Reset operation: Once all of the D21 power supplies are active, and

the ORI_PWRGD signal (Z-ray, pin V17) is high, the reset signal that drives the IM-B20 Module,

A-INIT_ODN (Z-ray, pin U1) becomes enabled (active high). A-INIT_ODN is connected to INIT_B of the

FPGA. The Reset circuitry is shown below.

Figure 9-3 Reset


19 Rev. 1.03

9.5. FMC+ connectors

D21 is provisioned with two FMC+ connectors. These connectors were designed to be compatible with

the VITA 57.4 standard. Figure 9-4 shows the VITA 57.4 standard pin assignment. Please refer to Table

9-1and Table 9-2 for additional details on the actual D21 FMC+ implementation.

Note 1: NOT all FMC port connections shown in Figure 9-4 are provisioned on D21.

Note 2: Pullup/Down and termination registers are populated on some signals.

Note 3: LAxx_P/N are traced as Single-ended unless otherwise noted.

Note 4: Some of LAxx_P/N_CC are connected to non CC pins.

Note 5: FPGA VCCO and FMC VADJ voltage are fixed to 1.8V. A bi-directional voltage converter

translates 1.8V to 3.3V on SDA and SCL to comply with the required 3.3V signaling level.

Note 6: The FMC+ power rails do not have overcurrent protection. DO NOT short the power rails.

Note 7: The CLK and SYNC pins are shown below cannot be used with an LVDS IO standard as they are

connected to an HR bank with a fixed 1.8V VCCO.

CLK2_BIDIR_P, CLK2_BIDIR_N, CLK3_BIDIR_P, CLK3_BIDIR_N,

REFCLK_M2C_P, REFCLK_M2C_N, REFCLK_C2M_P, REFCLK_C2M_N,

SYNC_M2C_P, SYNC_M2C_N, SYNC_C2M_P, SYNC_C2M_N

Note 8: GA0 and GA1 pin of both FMC+ connectors are tied to GND via a 10kohm register.

Note 9: The FMC+ ports are NOT spaced to support a double width FMC card.

Note10: The trace length of the signals traced as single-ended is not identical.

Note11: The trace length of the differential signals between pair to pair is not identical. The trace length

of the differential signals within each deferential pair is almost identical.

Note12: CLKx_BIDIR_P/N, REFCLK_C2M_P/N, and SYNC_x2x_P/N are connected to non CC pins.

Due to the above stipulations, prior to purchase, review your needs carefully, and contact Tokyo Electron

Device to discuss your application and FMC compatibility.

Figure 9-4 FMC+ pinout


20 Rev. 1.03

Table 9-1 FMC+ J17 Pinout

FMC+

Pin Name

FMC

Pin

Z-ray

Pin FPGA Pin Name Bank

FPGA

Pin Note

LA00_P_CC G6 M44 IO_L11P_T1U_N8_GC_66 66 G9 Diff signal

LA00_N_CC G7 M43 IO_L11N_T1U_N9_GC_66 66 F9 Diff signal

LA01_P_CC D8 M47 IO_L1P_T0L_N0_DBC_66 66 F8 Diff signal

LA01_N_CC D9 M46 IO_L1N_T0L_N1_DBC_66 66 E8 Diff signal

LA02_P H7 O31 IO_L6P_T0U_N10_AD6P_66 66 E10

LA02_N H8 O32 IO_L6N_T0U_N11_AD6N_66 66 D10

LA03_P G9 P30 IO_L24P_T3U_N10_66 66 D13

LA03_N G10 P32 IO_L24N_T3U_N11_66 66 C13

LA04_P H10 R30 IO_L22P_T3U_N6_DBC_AD0P_66 66 F13

LA04_N H11 R32 IO_L22N_T3U_N7_DBC_AD0N_66 66 E13

LA05_P D11 R27 IO_L20P_T3L_N2_AD1P_66 66 C12

LA05_N D12 R29 IO_L20N_T3L_N3_AD1N_66 66 B12

LA06_P C10 O28 IO_L5P_T0U_N8_AD14P_66 66 D9

LA06_N C11 O29 IO_L5N_T0U_N9_AD14N_66 66 C9

LA07_P H13 P27 IO_L23P_T3U_N8_66 66 A13

LA07_N H14 P29 IO_L23N_T3U_N9_66 66 A12

LA08_P G12 M50 IO_L3P_T0L_N4_AD15P_66 66 D8 Diff signal

LA08_N G13 M49 IO_L3N_T0L_N5_AD15N_66 66 C8 Diff signal

LA09_P D14 Q28 IO_L4P_T0U_N6_DBC_AD7P_66 66 B10

LA09_N D15 Q29 IO_L4N_T0U_N7_DBC_AD7N_66 66 A10

LA10_P C14 R26 IO_L21P_T3L_N4_AD8P_66 66 C11

LA10_N C15 P26 IO_L21N_T3L_N5_AD8N_66 66 B11

LA11_P H16 O25 IO_L2P_T0L_N2_66 66 B9

LA11_N H17 O26 IO_L2N_T0L_N3_66 66 A9

LA12_P G15 M38 IO_L9P_T1L_N4_AD12P_66 66 J8 Diff signal

LA12_N G16 M37 IO_L9N_T1L_N5_AD12N_66 66 H8 Diff signal

LA13_P D17 P23 IO_L7P_T1L_N0_QBC_AD13P_66 66 L8

LA13_N D18 P24 IO_L7N_T1L_N1_QBC_AD13N_66 66 K8

LA14_P C18 M35 IO_L10P_T1U_N6_QBC_AD4P_66 66 K10 Diff signal

LA14_N C19 M34 IO_L10N_T1U_N7_QBC_AD4N_66 66 J10 Diff signal

LA15_P H19 O22 IO_L8P_T1L_N2_AD5P_66 66 J9

LA15_N H20 O23 IO_L8N_T1L_N3_AD5N_66 66 H9

LA16_P G18 M32 IO_L15P_T2L_N4_AD11P_66 66 K11 Diff signal

LA16_N G19 M31 IO_L15N_T2L_N5_AD11N_66 66 J11 Diff signal

LA17_P_CC D20 K32 IO_L14P_T2L_N2_GC_67 67 E22 Diff signal, 100ohm term、1.8V pullup by 10k,


21 Rev. 1.03

pulldown by 10k

LA17_N_CC D21 K31 IO_L14N_T2L_N3_GC_67 67 E23 Diff signal, 100ohm term、1.8V pullup by 10k,

pulldown by 10k

LA18_P_CC C22 M23 IO_L16P_T2U_N6_QBC_AD3P_66 66 L13 Diff signal

LA18_N_CC C23 M22 IO_L16N_T2U_N7_QBC_AD3N_66 66 K13 Diff signal

LA19_P H22 P20 IO_L12P_T1U_N10_GC_66 66 G10

LA19_N H23 P21 IO_L12N_T1U_N11_GC_66 66 F10

LA20_P G21 O19 IO_L18P_T2U_N10_AD2P_66 66 J13

LA20_N G22 O20 IO_L18N_T2U_N11_AD2N_66 66 H13

LA21_P H25 T19 IO_L19P_T3L_N0_DBC_AD9P_66 66 E11

LA21_N H26 T18 IO_L19N_T3L_N1_DBC_AD9N_66 66 D11

LA22_P G24 P15 IO_L14P_T2L_N2_GC_66 66 H12

LA22_N G25 P14 IO_L14N_T2L_N3_GC_66 66 G12

LA23_P D23 O17 IO_L22P_T3U_N6_DBC_AD0P_67 67 G20

LA23_N D24 O16 IO_L22N_T3U_N7_DBC_AD0N_67 67 F20

LA24_P H28 O14 IO_L24P_T3U_N10_67 67 H21

LA24_N H29 O13 IO_L24N_T3U_N11_67 67 G21

LA25_P G27 P11 IO_L23P_T3U_N8_67 67 G22

LA25_N G28 O11 IO_L23N_T3U_N9_67 67 F22

LA26_P D26 Q17 IO_L21P_T3L_N4_AD8P_67 67 F23

LA26_N D27 P9 IO_L21N_T3L_N5_AD8N_67 67 F24

LA27_P C26 M29 IO_L17P_T2U_N8_AD10P_66 66 L12 Diff signal

LA27_N C27 M28 IO_L17N_T2U_N9_AD10N_66 66 K12 Diff signal

LA28_P H31 O10 IO_L19P_T3L_N0_DBC_AD9P_67 67 G24

LA28_N H32 P8 IO_L19N_T3L_N1_DBC_AD9N_67 67 F25

LA29_P G30 O8 IO_L11P_T1U_N8_GC_67 67 E25

LA29_N G31 O7 IO_L11N_T1U_N9_GC_67 67 D25

LA30_P H34 P6 IO_L7P_T1L_N0_QBC_AD13P_67 67 E26

LA30_N H35 P5 IO_L7N_T1L_N1_QBC_AD13N_67 67 D26

LA31_P G33 O5 IO_L1P_T0L_N0_DBC_67 67 F27

LA31_N G34 O4 IO_L1N_T0L_N1_DBC_67 67 E27

LA32_P H37 P2 IO_L5P_T0U_N8_AD14P_67 67 D28

LA32_N H38 O2 IO_L5N_T0U_N9_AD14N_67 67 C28

LA33_P G36 P3 IO_L3P_T0L_N4_AD15P_67 67 E28

LA33_N G37 O1 IO_L3N_T0L_N5_AD15N_67 67 D29

CLK0_M2C_P H4 M41 IO_L13P_T2L_N0_GC_QBC_67 67 D23 Diff signal, 100ohm term、1.8V pullup by 10k,

pulldown by 10k, AC coupled

CLK0_M2C_N H5 M40 IO_L13N_T2L_N1_GC_QBC_67 67 C23 Diff signal, 100ohm term、1.8V pullup by 10k,



22 Rev. 1.03

CLK1_M2C_P G2 M8 IO_L13P_T2L_N0_GC_QBC_66 66 H11 Diff signal, 100ohm term、1.8V pullup by 10k,


CLK1_M2C_N G3 M7 IO_L13N_T2L_N1_GC_QBC_66 66 G11 Diff signal, 100ohm term、1.8V pullup by 10k,


CLK2_BIDIR_P K4 R9 IO_L24P_T3U_N10_64 64 AK8 Single-ended, LVDS and LVDS_25 cannot be

used on HR bank with 1.8V VCCO

CLK2_BIDIR_N K5 R6 IO_L24N_T3U_N11_64 64 AL8 Single-ended, LVDS and LVDS_25 cannot be


CLK3_BIDIR_P J2 Q10 IO_L21P_T3L_N4_AD8P_64 64 AK10 Single-ended, LVDS and LVDS_25 cannot be


CLK3_BIDIR_N J3 Q7 IO_L21N_T3L_N5_AD8N_64 64 AL9 Single-ended, LVDS and LVDS_25 cannot be


REFCLK_M2C_P L24 S15 IO_L14P_T2L_N2_GC_64 64 AF9 Single-ended, LVDS and LVDS_25 cannot be


REFCLK_M2C_N L25 T14 IO_L14N_T2L_N3_GC_64 64 AG9 Single-ended, LVDS and LVDS_25 cannot be


REFCLK_C2M_P L20 R2 IO_L22P_T3U_N6_DBC_AD0P_64 64 AN8 Single-ended, LVDS and LVDS_25 cannot be


REFCLK_C2M_N L21 U2 IO_L22N_T3U_N7_DBC_AD0N_64 64 AP8 Single-ended, LVDS and LVDS_25 cannot be


SYNC_M2C_P L28 R3 IO_L20P_T3L_N2_AD1P_64 64 AN9 Single-ended, LVDS and LVDS_25 cannot be


SYNC_M2C_N L29 Q1 IO_L20N_T3L_N3_AD1N_64 64 AP9 Single-ended, LVDS and LVDS_25 cannot be


SYNC_C2M_P L16 Q4 IO_L2P_T0L_N2_64 64 AN13 Single-ended, LVDS and LVDS_25 cannot be


SYNC_C2M_N L17 Q2 IO_L2N_T0L_N3_64 64 AP13 Single-ended, LVDS and LVDS_25 cannot be


SCL C30 R12 IO_L6P_T0U_N10_AD6P_64 64 AK13

Single-ended, LVDS and LVDS_25 cannot be

used on HR bank with 1.8V VCCO, converted

to 3.3V IO voltage

SDA C31 R8 IO_L6N_T0U_N11_AD6N_64 64 AL13



to 3.3V IO voltage

DP0_M2C_P C6 A5 MGTHRXP0_224 224 AP2

DP0_M2C_N C7 A4 MGTHRXN0_224 224 AP1

DP1_M2C_P A2 C5 MGTHRXP1_224 224 AM2

DP1_M2C_N A3 C4 MGTHRXN1_224 224 AM1

DP2_M2C_P A6 A8 MGTHRXP2_224 224 AK2

DP2_M2C_N A7 A7 MGTHRXN2_224 224 AK1

DP3_M2C_P A10 C8 MGTHRXP3_224 224 AJ4

DP3_M2C_N A11 C7 MGTHRXN3_224 224 AJ3

DP4_M2C_P A14 A11 MGTHRXP0_225 225 AH2

DP4_M2C_N A15 A10 MGTHRXN0_225 225 AH1


23 Rev. 1.03

DP5_M2C_P A18 C11 MGTHRXP1_225 225 AF2

DP5_M2C_N A19 C10 MGTHRXN1_225 225 AF1

DP6_M2C_P B16 A14 MGTHRXP2_225 225 AD2

DP6_M2C_N B17 A13 MGTHRXN2_225 225 AD1

DP7_M2C_P B12 C14 MGTHRXP3_225 225 AB2

DP7_M2C_N B13 C13 MGTHRXN3_225 225 AB1

DP8_M2C_P B8 A38 MGTHRXP0_226 226 Y2

DP8_M2C_N B9 A37 MGTHRXN0_226 226 Y1

DP9_M2C_P B4 C38 MGTHRXP1_226 226 V2

DP9_M2C_N B5 C37 MGTHRXN1_226 226 V1

DP10_M2C_P Y10 A41 MGTHRXP2_226 226 T2

DP10_M2C_N Y11 A40 MGTHRXN2_226 226 T1

DP11_M2C_P Z12 C41 MGTHRXP3_226 226 P2

DP11_M2C_N Z13 C40 MGTHRXN3_226 226 P1

DP12_M2C_P Y14 A44 MGTHRXP0_227 227 M2

DP12_M2C_N Y15 A43 MGTHRXN0_227 227 M1

DP13_M2C_P Z16 C44 MGTHRXP1_227 227 K2

DP13_M2C_N Z17 C43 MGTHRXN1_227 227 K1

DP14_M2C_P Y18 A47 MGTHRXP2_227 227 H2

DP14_M2C_N Y19 A46 MGTHRXN2_227 227 H1

DP15_M2C_P Y22 C47 MGTHRXP3_227 227 F2

DP15_M2C_N Y23 C46 MGTHRXN3_227 227 F1

DP0_C2M_P C2 F5 MGTHTXP0_224 224 AN4

DP0_C2M_N C3 F4 MGTHTXN0_224 224 AN3

DP1_C2M_P A22 H5 MGTHTXP1_224 224 AM6

DP1_C2M_N A23 H4 MGTHTXN1_224 224 AM5

DP2_C2M_P A26 F8 MGTHTXP2_224 224 AL4

DP2_C2M_N A27 F7 MGTHTXN2_224 224 AL3

DP3_C2M_P A30 H8 MGTHTXP3_224 224 AK6

DP3_C2M_N A31 H7 MGTHTXN3_224 224 AK5

DP4_C2M_P A34 F11 MGTHTXP0_225 225 AH6

DP4_C2M_N A35 F10 MGTHTXN0_225 225 AH5

DP5_C2M_P A38 H11 MGTHTXP1_225 225 AG4

DP5_C2M_N A39 H10 MGTHTXN1_225 225 AG3

DP6_C2M_P B36 F14 MGTHTXP2_225 225 AE4

DP6_C2M_N B37 F13 MGTHTXN2_225 225 AE3

DP7_C2M_P B32 H14 MGTHTXP3_225 225 AC4

DP7_C2M_N B33 H13 MGTHTXN3_225 225 AC3


24 Rev. 1.03

DP8_C2M_P B28 F38 MGTHTXP0_226 226 AA4

DP8_C2M_N B29 F37 MGTHTXN0_226 226 AA3

DP9_C2M_P B24 H38 MGTHTXP1_226 226 W4

DP9_C2M_N B25 H37 MGTHTXN1_226 226 W3

DP10_C2M_P Z24 F41 MGTHTXP2_226 226 U4

DP10_C2M_N Z25 F40 MGTHTXN2_226 226 U3

DP11_C2M_P Y26 H41 MGTHTXP3_226 226 R4

DP11_C2M_N Y27 H40 MGTHTXN3_226 226 R3

DP12_C2M_P Z28 F44 MGTHTXP0_227 227 N4

DP12_C2M_N Z29 F43 MGTHTXN0_227 227 N3

DP13_C2M_P Y30 H44 MGTHTXP1_227 227 L4

DP13_C2M_N Y31 H43 MGTHTXN1_227 227 L3

DP14_C2M_P M18 F47 MGTHTXP2_227 227 J4

DP14_C2M_N M19 F46 MGTHTXN2_227 227 J3

DP15_C2M_P M22 H47 MGTHTXP3_227 227 G4

DP15_C2M_N M23 H46 MGTHTXN3_227 227 G3

GBTCLK0_M2C_P D4 K2 MGTREFCLK0P_224 224 AF6 AC coupled

GBTCLK0_M2C_N D5 K1 MGTREFCLK0N_224 224 AF5 AC coupled

GBTCLK1_M2C_P B20 K11 MGTREFCLK0P_225 225 AB6 AC coupled

GBTCLK1_M2C_N B21 K10 MGTREFCLK0N_225 225 AB5 AC coupled

GBTCLK2_M2C_P L12 K38 MGTREFCLK0P_226 226 V6 AC coupled

GBTCLK2_M2C_N L13 K37 MGTREFCLK0N_226 226 V5 AC coupled

GBTCLK3_M2C_P L8 K41 MGTREFCLK0P_227 227 P6 AC coupled

GBTCLK3_M2C_N L9 K40 MGTREFCLK0N_227 227 P5 AC coupled

GBTCLK4_M2C_P L4

GBTCLK4_M2C_N L5

GBTCLK5_M2C_P Z20

GBTCLK5_M2C_N Z21


25 Rev. 1.03

Table 9-2 FMC+ J18 Pinout

FMC+ Pin Name FMC

Pin

Z-ray

Pin FPGA Pin Name

Ban

k

FPGA

Pin Note

LA00_P_CC G6 M20 IO_L19P_T3L_N0_DBC_AD9P_68 68 J15 Diff signal

LA00_N_CC G7 M19 IO_L19N_T3L_N1_DBC_AD9N_68 68 J14 Diff signal

LA01_P_CC D8 O49 IO_L9P_T1L_N4_AD12P_67 67 C26

LA01_N_CC D9 O50 IO_L9N_T1L_N5_AD12N_67 67 B26

LA02_P H7 Q49 IO_L2P_T0L_N2_67 67 C27

LA02_N H8 Q50 IO_L2N_T0L_N3_67 67 B27

LA03_P G9 P48 IO_L6P_T0U_N10_AD6P_67 67 A27

LA03_N G10 P50 IO_L6N_T0U_N11_AD6N_67 67 A28

LA04_P H10 R48 IO_L4P_T0U_N6_DBC_AD7P_67 67 B29

LA04_N H11 R50 IO_L4N_T0U_N7_DBC_AD7N_67 67 A29

LA05_P D11 Q46 IO_L12P_T1U_N10_GC_67 67 D24

LA05_N D12 Q47 IO_L12N_T1U_N11_GC_67 67 C24

LA06_P C10 P45 IO_L10P_T1U_N6_QBC_AD4P_67 67 B24

LA06_N C11 P47 IO_L10N_T1U_N7_QBC_AD4N_67 67 A24

LA07_P H13 R45 IO_L8P_T1L_N2_AD5P_67 67 B25

LA07_N H14 R47 IO_L8N_T1L_N3_AD5N_67 67 A25

LA08_P G12 O43 IO_L17P_T2U_N8_AD10P_67 67 B20

LA08_N G13 O44 IO_L17N_T2U_N9_AD10N_67 67 A20

LA09_P D14 Q43 IO_L18P_T2U_N10_AD2P_67 67 D20

LA09_N D15 Q44 IO_L18N_T2U_N11_AD2N_67 67 D21

LA10_P C14 R42 IO_L16P_T2U_N6_QBC_AD3P_67 67 C21

LA10_N C15 R44 IO_L16N_T2U_N7_QBC_AD3N_67 67 C22

LA11_P H16 P42 IO_L15P_T2L_N4_AD11P_67 67 B21

LA11_N H17 P44 IO_L15N_T2L_N5_AD11N_67 67 B22

LA12_P G15 M17 IO_L21P_T3L_N4_AD8P_68 68 L15 Diff signal

LA12_N G16 M16 IO_L21N_T3L_N5_AD8N_68 68 K15 Diff signal

LA13_P D17 O40 IO_L5P_T0U_N8_AD14P_68 68 B17

LA13_N D18 O41 IO_L5N_T0U_N9_AD14N_68 68 B16

LA14_P C18 M14 IO_L23P_T3U_N8_68 68 K16 Diff signal

LA14_N C19 M13 IO_L23N_T3U_N9_68 68 J16 Diff signal

LA15_P H19 Q40 IO_L10P_T1U_N6_QBC_AD4P_68 68 D19

LA15_N H20 Q41 IO_L10N_T1U_N7_QBC_AD4N_68 68 D18

LA16_P G18 M11 IO_L20P_T3L_N2_AD1P_68 68 K18 Diff signal

LA16_N G19 M10 IO_L20N_T3L_N3_AD1N_68 68 K17 Diff signal


26 Rev. 1.03

LA17_P_CC D20 M5 IO_L22P_T3U_N6_DBC_AD0P_68 68 J19 Diff signal

LA17_N_CC D21 M4 IO_L22N_T3U_N7_DBC_AD0N_68 68 J18 Diff signal

LA18_P_CC C22 P39 IO_L2P_T0L_N2_68 68 A19

LA18_N_CC C23 P41 IO_L2N_T0L_N3_68 68 A18

LA19_P H22 R39 IO_L4P_T0U_N6_DBC_AD7P_68 68 C19

LA19_N H23 R41 IO_L4N_T0U_N7_DBC_AD7N_68 68 B19

LA20_P G21 O37 IO_L6P_T0U_N10_AD6P_68 68 C18

LA20_N G22 O38 IO_L6N_T0U_N11_AD6N_68 68 C17

LA21_P H25 Q37 IO_L12P_T1U_N10_GC_68 68 E18

LA21_N H26 Q38 IO_L12N_T1U_N11_GC_68 68 E17

LA22_P G24 R38 IO_L9P_T1L_N4_AD12P_68 68 F15

LA22_N G25 R36 IO_L9N_T1L_N5_AD12N_68 68 F14

LA23_P D23 P36 IO_L7P_T1L_N0_QBC_AD13P_68 68 D14

LA23_N D24 P38 IO_L7N_T1L_N1_QBC_AD13N_68 68 C14

LA24_P H28 Q34 IO_L8P_T1L_N2_AD5P_68 68 E15

LA24_N H29 Q35 IO_L8N_T1L_N3_AD5N_68 68 D15

LA25_P G27 O34 IO_L3P_T0L_N4_AD15P_68 68 B15

LA25_N G28 O35 IO_L3N_T0L_N5_AD15N_68 68 A15

LA26_P D26 R33 IO_L11P_T1U_N8_GC_68 68 E16

LA26_N D27 R35 IO_L11N_T1U_N9_GC_68 68 D16

LA27_P C26 M2 IO_L24P_T3U_N10_68 68 L19 Diff signal

LA27_N C27 M1 IO_L24N_T3U_N11_68 68 L18 Diff signal

LA28_P H31 P33 IO_L1P_T0L_N0_DBC_68 68 B14

LA28_N H32 P35 IO_L1N_T0L_N1_DBC_68 68 A14

LA29_P G30 W18 IO_L15P_T2L_N4_AD11P_68 68 G15

LA29_N G31 Q23 IO_L15N_T2L_N5_AD11N_68 68 G14

LA30_P H34 R20 IO_L17P_T2U_N8_AD10P_68 68 H17

LA30_N H35 R21 IO_L17N_T2U_N9_AD10N_68 68 H16

LA31_P G33 Q19 IO_L18P_T2U_N10_AD2P_68 68 H19

LA31_N G34 Q20 IO_L18N_T2U_N11_AD2N_68 68 H18

LA32_P H37 R17 IO_L16P_T2U_N6_QBC_AD3P_68 68 G19

LA32_N H38 R18 IO_L16N_T2U_N7_QBC_AD3N_68 68 F19

LA33_P G36 P18 IO_L20P_T3L_N2_AD1P_67 67 E20

LA33_N G37 P17 IO_L20N_T3L_N3_AD1N_67 67 E21

CLK0_M2C_P H4 K26 IO_L13P_T2L_N0_GC_QBC_68 68 G17 Diff signal, 100ohm term、1.8V pullup by 10k,


CLK0_M2C_N H5 K25 IO_L13N_T2L_N1_GC_QBC_68 68 G16 Diff signal, 100ohm term、1.8V pullup by 10k,


CLK1_M2C_P G2 K29 IO_L14P_T2L_N2_GC_68 68 F18 Diff signal, 100ohm term、1.8V pullup by 10k,


27 Rev. 1.03


CLK1_M2C_N G3 K28 IO_L14N_T2L_N3_GC_68 68 F17 Diff signal, 100ohm term、1.8V pullup by 10k,


CLK2_BIDIR_P K4 U14 IO_L7P_T1L_N0_QBC_AD13P_64 64 AE13 Single-ended, LVDS and LVDS_25 cannot be


CLK2_BIDIR_N K5 Q16 IO_L7N_T1L_N1_QBC_AD13N_64 64 AF13 Single-ended, LVDS and LVDS_25 cannot be


CLK3_BIDIR_P J2 S17 IO_L10P_T1U_N6_QBC_AD4P_64 64 AD11 Single-ended, LVDS and LVDS_25 cannot be


CLK3_BIDIR_N J3 U17 IO_L10N_T1U_N7_QBC_AD4N_64 64 AE11 Single-ended, LVDS and LVDS_25 cannot be


REFCLK_M2C_P L24 T13 IO_L11P_T1U_N8_GC_64 64 AG12

Single-ended, Connected to onboard ADC,

LVDS and LVDS_25 cannot be used on HR

bank with 1.8V VCCO

REFCLK_M2C_N L25 R15 IO_L11N_T1U_N9_GC_64 64 AH12 Single-ended, LVDS and LVDS_25 cannot be


REFCLK_C2M_P L20 Q14 IO_L23P_T3U_N8_64 64 AJ9 Single-ended, LVDS and LVDS_25 cannot be


REFCLK_C2M_N L21 Q13 IO_L23N_T3U_N9_64 64 AJ8 Single-ended, LVDS and LVDS_25 cannot be


SYNC_M2C_P L28 T11 IO_L18P_T2U_N10_AD2P_64 64 AH9 Single-ended, LVDS and LVDS_25 cannot be


SYNC_M2C_N L29 U10 IO_L18N_T2U_N11_AD2N_64 64 AH8 Single-ended, LVDS and LVDS_25 cannot be


SYNC_C2M_P L16 T16 IO_L9P_T1L_N4_AD12P_64 64 AE12 Single-ended, LVDS and LVDS_25 cannot be


SYNC_C2M_N L17 U15 IO_L9N_T1L_N5_AD12N_64 64 AF12 Single-ended, LVDS and LVDS_25 cannot be


SCL C30 R11 IO_L5P_T0U_N8_AD14P_64 64 AK12



to 3.3V IO voltage

SDA C31 Q8 IO_L5N_T0U_N9_AD14N_64 64 AL12



to 3.3V IO voltage

DP0_M2C_P C6 C17 MGTHRXP0_127 127 R33

DP0_M2C_N C7 C16 MGTHRXN0_127 127 R34

DP1_M2C_P A2 A17 MGTHRXP1_127 127 N33

DP1_M2C_N A3 A16 MGTHRXN1_127 127 N34

DP2_M2C_P A6 C2 MGTHRXP2_127 127 L33

DP2_M2C_N A7 C1 MGTHRXN2_127 127 L34

DP3_M2C_P A10 A2 MGTHRXP3_127 127 J33

DP3_M2C_N A11 A1 MGTHRXN3_127 127 J34

DP4_M2C_P A14 A20 MGTHRXP0_128 128 G33

DP4_M2C_N A15 A19 MGTHRXN0_128 128 G34


28 Rev. 1.03

DP5_M2C_P A18 C20 MGTHRXP1_128 128 F31

DP5_M2C_N A19 C19 MGTHRXN1_128 128 F32

DP6_M2C_P B16 C32 MGTHRXP2_128 128 E33

DP6_M2C_N B17 C31 MGTHRXN2_128 128 E34

DP7_M2C_P B12 A32 MGTHRXP3_128 128 C33

DP7_M2C_N B13 A31 MGTHRXN3_128 128 C34

DP8_M2C_P B8 A35 MGTHRXP0_228 228 E4

DP8_M2C_N B9 A34 MGTHRXN0_228 228 E3

DP9_M2C_P B4 C35 MGTHRXP1_228 228 D2

DP9_M2C_N B5 C34 MGTHRXN1_228 228 D1

DP10_M2C_P Y10 A50 MGTHRXP2_228 228 B2

DP10_M2C_N Y11 A49 MGTHRXN2_228 228 B1

DP11_M2C_P Z12 C50 MGTHRXP3_228 228 A4

DP11_M2C_N Z13 C49 MGTHRXN3_228 228 A3

DP12_M2C_P Y14

DP12_M2C_N Y15

DP13_M2C_P Z16

DP13_M2C_N Z17

DP14_M2C_P Y18

DP14_M2C_N Y19

DP15_M2C_P Y22

DP15_M2C_N Y23

DP0_C2M_P C2 H17 MGTHTXP0_127 127 T31

DP0_C2M_N C3 H16 MGTHTXN0_127 127 T32

DP1_C2M_P A22 F17 MGTHTXP1_127 127 P31

DP1_C2M_N A23 F16 MGTHTXN1_127 127 P32

DP2_C2M_P A26 H2 MGTHTXP2_127 127 M31

DP2_C2M_N A27 H1 MGTHTXN2_127 127 M32

DP3_C2M_P A30 F2 MGTHTXP3_127 127 K31

DP3_C2M_N A31 F1 MGTHTXN3_127 127 K32

DP4_C2M_P A34 F20 MGTHTXP0_128 128 H31

DP4_C2M_N A35 F19 MGTHTXN0_128 128 H32

DP5_C2M_P A38 H20 MGTHTXP1_128 128 G29

DP5_C2M_N A39 H19 MGTHTXN1_128 128 G30

DP6_C2M_P B36 H32 MGTHTXP2_128 128 D31

DP6_C2M_N B37 H31 MGTHTXN2_128 128 D32

DP7_C2M_P B32 F32 MGTHTXP3_128 128 B31

DP7_C2M_N B33 F31 MGTHTXN3_128 128 B32


29 Rev. 1.03

DP8_C2M_P B28 F35 MGTHTXP0_228 228 F6

DP8_C2M_N B29 F34 MGTHTXN0_228 228 F5

DP9_C2M_P B24 H35 MGTHTXP1_228 228 D6

DP9_C2M_N B25 H34 MGTHTXN1_228 228 D5

DP10_C2M_P Z24 F50 MGTHTXP2_228 228 C4

DP10_C2M_N Z25 F49 MGTHTXN2_228 228 C3

DP11_C2M_P Y26 H50 MGTHTXP3_228 228 B6

DP11_C2M_N Y27 H49 MGTHTXN3_228 228 B5

DP12_C2M_P Z28

DP12_C2M_N Z29

DP13_C2M_P Y30

DP13_C2M_N Y31

DP14_C2M_P M18

DP14_C2M_N M19

DP15_C2M_P M22

DP15_C2M_N M23

GBTCLK0_M2C_P D4 K17 MGTREFCLK0P_127 127 R29 AC coupled

GBTCLK0_M2C_N D5 K16 MGTREFCLK0N_127 127 R30 AC coupled

GBTCLK1_M2C_P B20 K8 MGTREFCLK0P_128 128 L29 AC coupled

GBTCLK1_M2C_N B21 K7 MGTREFCLK0N_128 128 L30 AC coupled

GBTCLK2_M2C_P L12 K50 MGTREFCLK1P_228 228 H6 AC coupled

GBTCLK2_M2C_N L13 K49 MGTREFCLK1N_228 228 H5 AC coupled

GBTCLK3_M2C_P L8

GBTCLK3_M2C_N L9

GBTCLK4_M2C_P L4

GBTCLK4_M2C_N L5

GBTCLK5_M2C_P Z20

GBTCLK5_M2C_N Z21


30 Rev. 1.03

9.6. Onboard PLL

D21 is provisioned with two AD9578 programmable clock synthesizers. Although the AD9578 supports

up to four outputs, only two are used on each device, for a total of four clocks. Three of these clocks are

connected to reference clock inputs on the Kintex UltraScale gigabit transceivers, and the fourth clock is

connected to FPGA fabric. D21 also connects clock outputs from the FPGA to reference inputs on the

AD9578’s. Please note that the AD9578 reference inputs, and the FPGA fabric output from the AD9578

are all connected to 1.8V HR banks, and thus cannot be configured to LVDS or LVDS_25 IO standards.

A suggested workaround is to set the IO standard for these clocks to SUB_LVDS, but one must

recognize that clock stability is not guaranteed. In addition, the reference clocks from the FPGA to the

synthesizers are traced as single-ended, limiting the frequency of operation.

Figure 9-5 Onboard PLLs

Dual PLL

Precision

Synthesizer

AD9578

(U317)

Dual PLL

Precision

Synthesizer

AD9578

(U17)

SCK

SDI

SDO

CS_N

SCK

Le

ve

l

co

nve

rte

r

SDI

Se

lecto

r

SDO

CS_N

Le

ve

l

co

nve

rte

r

Le

ve

l

co

nve

rte

r

FP

GA

OUT1

OUT3

XO1/248MHz Xtal

7M48072002

XO3/4

XO1/248MHz Xtal

7M48072002

XO3/4

OUT1

OUT3

Z-r

ay c

on

ne

cto

r

Clock to fabric

Ref clk

Ref clk

Ref clk

Clock from

fabric

Clock from

fabric


31 Rev. 1.03

Table 9-3 U17 pinout

Pin name Pin Z-ray


FPGA

Pin Note

XO3 46 R5 IO_L3P_T0L_N4_AD15P_64 64 AM11 Single-ended, LVDS and LVDS_25 cannot be


XO4 45 T4 IO_L3N_T0L_N5_AD15N_64 64 AN11



bank with 1.8V VCCO

OUT1 2 K5 MGTREFCLK1P_128 128 J29

OUT1_N 3 K4 MGTREFCLK1N_128 128 J30

OUT3 29 K35 MGTREFCLK1P_225 225 Y6

OUT3_N 28 K34 MGTREFCLK1N_225 225 Y5

CS_N 18 Q31 IO_T3U_N12_66 66 E12

SCK 19 P12 IO_T3U_N12_67 67 H22 Common SPI bus with U317

SDI 20 O46 IO_T2U_N12_67 67 A22 Common SPI bus with U317

SDO 17 O47 IO_T1U_N12_67 67 A23 Common SPI bus with U317

Table 9-4 U317 pinout

Pin name Pin Z-ray


FPGA

Pin Note

XO3 46 S13 IO_L12P_T1U_N10_GC_64 64 AG11



bank with 1.8V VCCO

XO4 45 U12 IO_L12N_T1U_N11_GC_64

IO_L23P_T3U_N8_I2C_SCLK_65

64

65

AH11

N21



OUT1 2 M26 IO_L13P_T2L_N0_GC_QBC_64 64 AF10

Diff signal, 100ohm term、1.8V pullup by 10k,

pulldown by 10k, LVDS and LVDS_25 cannot

be used on HR bank with 1.8V VCCO

OUT1_N 3 M25 IO_L13N_T2L_N1_GC_QBC_64 64 AG10

Diff signal, 100ohm term、1.8V pullup by 10k,

pulldown by 10k, LVDS and LVDS_25 cannot

be used on HR bank with 1.8V VCCO

OUT3 29 K47 MGTREFCLK1P_227 227 M6

OUT3_N 28 K46 MGTREFCLK1N_227 227 M5

CS_N 18 Q32 IO_T1U_N12_66 66 L9

SCK 19 P12 IO_T3U_N12_67 67 H22 Common SPI bus with U17

SDI 20 O46 IO_T2U_N12_67 67 A22 Common SPI bus with U17

SDO 17 O47 IO_T1U_N12_67 67 A23 Common SPI bus with U17


32 Rev. 1.03

9.7. Crystal Oscillator

D21 is provisioned with two fixed 156.25MHz LVDS oscillators (PN: 531BC156M250DG) intended as

reference clocks for transceivers.

Figure 9-6 Crystal Oscillator

Table 9-5 Y303 pinout

Pin name Pin Z-ray


FPGA

Pin Note

CLK+ 4 K14 MGTREFCLK1P_127 127 N29 LVDS output

CLK- 5 K13 MGTREFCLK1N_127 127 N30 LVDS output

Table 9-6 Y304 pinout

Pin name Pin Z-ray


FPGA

Pin Note

CLK+ 4 K44 MGTREFCLK1P_226 226 T6 LVDS output

CLK- 5 K43 MGTREFCLK1N_226 226 T5 LVDS output

9.8. JTAG-over-USB

The D21 provides a user-friendly JTAG-over-USB module. This enables the user to connect to JTAG

with only a USB cable (no programming pod required). The traditional 14pin-JTAG header is not

provided. The JTAG signals are connected to dedicated IO of the IM-B20 Module.


33 Rev. 1.03

9.9. UART-over-USB

The D21 provides a user-friendly UART-over-USB connection. This enables the user to connect debug

their system via UART with a common USB connection.

Table 9-7 UART-over-USB pinout

Pin name Pin Z-ray


FPGA

Pin Note

TXD 25 T3 IO_L1P_T0L_N0_DBC_64 64 AP11 FPGA to host

RXD 26 T2 IO_L1N_T0L_N1_DBC_64 64 AP10 Host to FPGA

9.10. General Purpose LEDs

D21 is provisioned with three general purpose LEDs. These LEDs can be used for debugging/status

indicators.

Figure 9-7 General Purpose LED

Table 9-8 General purpose LEDs pinout

Component Pin Z-ray


FPGA

Pin Note

D16 - Q5 IO_T3U_N12_64 64 AM9

D25 - R14 IO_T2U_N12_64 64 AJ10

D26 - Q11 IO_T0U_N12_64 64 AK11


34 Rev. 1.03

9.11. Pin Header

D21 is provisioned with a 6-pin header. Note that although the header is six pins in total, four pins are

connected to power (1.8V) and ground, and the remaining two pins are user assignable for

debugging/status. User assignable pins must be configured to an IO voltage of 1.8V.

Figure 9-8 Pin Header

Table 9-9 Pin header pinout

Component Pin Z-ray


FPGA

Pin Note

J66 1 R24 IO_T3U_N12_68 68 L17

J66 2 R23 IO_T2U_N12_68 68 H14

9.12. Push-button Switch

D21 is provisioned with a simple push-button switch.

Figure 9-9 Push-button Switch

Table 9-10 Push-button Switch pinout

Component Pin Z-ray


FPGA

Pin Note

SW3 2,4 S12 IO_T1U_N12_64

IO_L23N_T3U_N9_I2C_SDA_65

64

65

AJ11

M21


35 Rev. 1.03

9.13. DIP Switch

D21 is provisioned with a 4-position DIP switch, however, only two positions are connected (see below).

It is intended for general purpose use.

Figure 9-10 DIP Switch

Table 9-11 DIP Switch pinout

Component Pin Z-ray


FPGA

Pin Note

SW301 8 S10 IO_T3U_N12_PERSTN0_65 65 K22 BIT1

SW301 7 S9 IO_T1U_N12_PERSTN1_65 65 N23 BIT2

9.14. Test Pads

The following Test Pads are used for factory testing only. Please do not connect any signal source to

the pads.

Component Pin

Z-ra

y

Pin

FPGA Pin Name Bank FPGA

Pin Note

TP20 - U5 IO_L19P_T3L_N0_DBC_AD9P_64 64 AL10

IM-B20 peripheral

bus (SDA),

Do not use

TP21 - S5 IO_L19N_T3L_N1_DBC_AD9N_64 64 AM10

IM-B20 peripheral

bus (SCL),

Do not use

TP18 - K20 IO_L13N_T2L_N1_GC_QBC_46 46 AK30 1.2V IO Voltage,

Do not use

TP19 - K23 IO_L13N_T2L_N1_GC_QBC_45 45 AH17 1.2V IO Voltage,

Do not use


36 Rev. 1.03

10. Description of Components on IM-B20 Origami Module

10.1. General Purpose LEDs on IM-B20

The Origami Module, IM-B20, has two of its own general purpose LEDs. The LEDs are located at the

rear of the IM-B20 Module. Please note that a green “Power On” LED is located just next to the general

purpose green LEDs.

Figure 10-1 General Purpose LEDs

Table 10-1 General Purpose LEDs pinout

Component Pin FPGA Pin Name Bank FPGA

Pin Note

D1 IO_T0U_N12_VRP_67 67 C29 Green LED

D2 IO_T0U_N12_VRP_68 68 A17 Red LED


37 Rev. 1.03

10.2. 200MHz System Clock

A 200MHz LVDS System Clock (PN: SG3225VAN 200.000000M-KEGA3) is populated on the IM-B20

Module.

Figure 10-2 200MHz System Clock

Table 10-2 200MHz System Clock

Pin name Pin FPGA Pin Name Bank FPGA

Pin Note

OUT_P 4 IO_L14P_T2L_N2_GC_47 47 W25

OUT_N 5 IO_L14N_T2L_N3_GC_47 47 Y25

10.3. 300MHz System Clock

A 300MHz LVDS System Clock (PN: DSC1103CI5-300.0000) is populated on the IM-B20 Module.

Figure 10-3 300MHz System Clock

Table 10-3 300MHz System Clock


38 Rev. 1.03


Pin Note

OUT_P 4 IO_L12P_T1U_N10_GC_44 44 AH22

OUT_N 5 IO_L12N_T1U_N11_GC_44 44 AH23

10.4. EMCCLK

A External Configuration Clock (EMCCLK) is populated on the IM-B20 Module. Part number and

frequency depend on D21 revision.

TB-OK-D21(JP) Rev 2.0.00

(PN: SG5032CBN 133.000000M-TJGA3)

Figure 10-4 133MHz EMCCLK (TB-OK-D21(JP) 2.0.00)


(PN: SG5032CBN 80.000000M-TJGA3)

Figure 10-5 80MHz EMCCLK(TB-OK-D21(JP) 2.1.00)

Table 10-4 EMCCLK pinout


Pin Note

OUT 3 IO_L24P_T3U_N10_EMCCLK_65 65 K20


39 Rev. 1.03


40 Rev. 1.03

10.5. Configuration Memory

Parallel NOR Flash or Serial NOR Flash on the IM-B20 Module is used for FPGA configuration. The

Flash is connected to the dedicated configuration port on the FPGA. The part number and memory type

depend on D21 board revision. Note that the Flash part number is subject to change due to availability.

TB-OK-D21(JP) 2.0.00

(PN: PC28F00AP30BFA)

Figure 10-6 Parallel NOR Flash (TB-OK-D21(JP) 2.0.00)

TB-OK-D21(JP) 2.1.00

(PN: MT25QU512ABB8E12-0SIT)

Figure 10-7 Serial NOR Flash (TB-OK-D21(JP) 2.1.00)


41 Rev. 1.03

10.6. DDR4

Eight DDR4 devices (PN: H5AN4G6NAFR-UHC or equivalent) are populated on the IM-B20 Module.

Physically, each chip is 256Mbits x 16 bits, and is designed for speeds up to 2400MT/s. The DDR4 is

connected to the FPGA as two separate banks of x64 bits.

Note: An .xdc file for Vivado is available with purchase. Please contact Tokyo Electron Device for details.

10.7. Voltage source (onboard ADC) for V_P and V_N pin

To provide V_P and V_N flexibility, an analog multiplexer (PN: MAX4781EUE+) is populated on the

IM-B20 Module. This function is not factory tested. Input signals for MAX4781 (A-I2C_S_A0,

A-I2C_S_A1 and A-I2C_S_A2 shown below) are shared with REFCLK_M2C_P on FMC+ connector J18,

XO4 pin of clock generator U17, and XO3 pin of clock generator U317.

Figure 10-8 Voltage source for V_P and V_N


42 Rev. 1.03

10.8. Real Time Clock

Real time clock (PN: M41ST87WSS6F) is populated on the IM-B20 Module. This function is not factory

tested.

Figure 10-9 Real Time Clock

Table 10-5 Real Time Clock pinout

Pin

name Pin FPGA Pin Name Bank

FPGA

Pin Note

SCL 16 IO_L19N_T3L_N1_D

BC_AD9N_64 64 AM10

connected to FPGA, Flash

Temp sensor and test pad via

level converter

SDA 12 IO_L19P_T3L_N0_DB

C_AD9P_64 64 AL10

connected to FPGA, Flash


level converter

PFO1_N 8 IO_T1U_N12_46 46 AM31

PFO2_N 5 IO_L7N_T1L_N1_QB

C_AD13N_46 46 AP26

F32K 15 Not connected to FPGA,

Connected to Z-ray S1

IRQ_N/

OUT 20

IO_L1N_T0L_N1_DB

C_46 46 AJ26


43 Rev. 1.03

10.9. General Purpose EEPROM

Slave address for EEPROM depends on D21 board revision.


EEPROM (U13) is not populated. Reserved for future use.

Figure 10-10 General Purpose EEPROM (TB-OK-D21(JP) Rev 2.0.00 )


EEPROM (U13) is not populated. Reserved for future use

Figure 10-11 General Purpose EEPROM (TB-OK-D21(JP) Rev 2.1.00 )

Table 10-6 General Purpose EEPROM pinout

Pin


FPGA

Pin Note


BC_AD9N_64 64 AM10

Connected to FPGA, RTC, Temp

sensor and test pad via level converter


C_AD9P_64 64 AL10

Connected to FPGA, RTC, Temp

sensor and test pad via level converter


44 Rev. 1.03

10.10. Temperature Sensor

Temperature Sensor (PN: TMP103AYFFR) is populated on the IM-B20 Module. This function is not

factory tested.

Figure 10-12 Temperature Sensor

Table 10-7 Temperature sensor

Pin


FPGA

Pin Note


BC_AD9N_64 64 AM10

connected to FPGA, RTC,


level converter


C_AD9P_64 64 AL10

connected to FPGA, RTC,


level converter


45 Rev. 1.03

10.11. Resistor network

Resistor network is used for factory testing. Please set the IOs shown below as either input or floating.

For additional clarity, refer to the table and the diagram below.

Figure 10-13 Resistor networks


46 Rev. 1.03

Table 10-8 Resistor networks


Pin Note

- - IO_L17P_T2U_N8_AD10P_64 64 AD9 Do not use

- - IO_L17N_T2U_N9_AD10N_64 64 AD8 Do not use

- - IO_L16P_T2U_N6_QBC_AD3P_64 64 AD10 Do not use

- - IO_L16N_T2U_N7_QBC_AD3N_64 64 AE10 Do not use

- - IO_L15P_T2L_N4_AD11P_64 64 AE8 Do not use

- - IO_L15N_T2L_N5_AD11N_64 64 AF8 Do not use

IO_L8P_T1L_N2_AD5P_64 64 AH13 Do not use

IO_L8N_T1L_N3_AD5N_64 64 AJ13 Do not use

IO_L4P_T0U_N6_DBC_AD7P_64 64 AM12 Do not use

IO_L4N_T0U_N7_DBC_AD7N_64 64 AN12 Do not use

IO_T0U_N12_VRP_47 47 AA28 Do not use

IO_T0U_N12_VRP_48 48 AC29 Do not use

IO_T0U_N12_VRP_46 46 AG26 Do not use

IO_T0U_N12_VRP_44 44 AD24 Do not use

IO_T0U_N12_VRP_45 45 AP19 Do not use

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