Surface Micromachined Capacitive Ultrasonic Immersion Transducers

X. C. Jin, I. Ladabaum, B. T. Khuri-Yakub Edward L. Ginzton Laboratory, Stanford University, Stanford, CA 94305

ABSTRACT Major steps used in fabricating surface microma-

chined capacitive ultrasonic immersion transducers are investigated in this paper. Such steps include membrane formation and cavity sealing under vac- uum. Three transducer membrane structures are evaluated: a nitride membrane with an LTO sacrifi- cial layer; a polysilicon membrane with an LTO sac- rificial layer; and a nitride membrane with a polysil- icon sacrificial layer. The major differences in the three processes are the conductivity, dielectric con- stant and residual stress of the membrane. Three vacuum sealing mechanisms are compared, each of which requires a different degree of lithographic so- phistication, and results in a sealed cavity. Sub- micron via sealing requires sophisticated lithography, but is amenable to LPCVD nitride, LTO and other sealing procedures. Standard g-line lithography re- sults in vias which seal only with high sticking co- efficient species, such as LTO. A novel etch chan- nel structure, which results in lateral sealing and re- quires neither sophisticated lithography nor a partic- ular sealing is demonstrated. The experiments in the paper are guided by theoretical analysis and com- puter simulations when applicable. The optimized process based on a nitride membrane with a polysil- icon sacrificial layer results in devices which have a broad band 500 real part impedance in the mega- hertz range. In addition, a transducer dynamic range in excess of lOOdB is achieved with an untuned band- width of 50%. The fabrication techniques and re- sults herein reported indicate that surface microma- chined capacitive ultrasonic transducers are an al- ternative to piezoelectric transducers in immersion applications.

KEYWORDS

Surface micromachining, ultrasonic transducer, fabrication process, immersion transducer, capaci- tive transducer

I. INTRODUCTION Active research work on capacitive micromachined

ultrasonic transducers (cMUTs) has been reported in the last decade because cMUTs have certain prop- erties which their major competitors, piezoelectric transducers, do not have. In addition to the wide op- erating temperature range (piezoelectrics depole at relatively low temperatures [l]), cMUTs, especially when surface micromachined, can be integrated with

electronics to form high density transducer arrays [2]. Most of the pioneering research in cMUTs is in air

operation 131, [4], [5], [6], [7], [SI, 191, [lo]. Research of immersion cMUTs is relatively recent due to the complicated fabrication process where the capacitive cavity needs to be sealed. Preliminary work has been reported on devices with nitride membranes and ni- tride sealed 0.25um vias [ll], [12], polysilicon mem- branes and BPSG sealed 0.8um vias [13], and nitride membranes and LTO sealed 2um vias [14]. This pa- per presents a systematic study of transducer mem- brane formation and cavity sealing, and thus enables the optimization of immersion cMUT performance.

11. FABRICATION PROCESS ANALYSIS

A . Membrane Formation

There are three basic mechanisms to form the transducer membrane. The different combinations of sacrificial layers and membrane materials are sum- marized in Table I.

Table I. Comparison of fabrication processes. Membrane Sacrificial Layer Insulator

A Nitride LTO /PSG B Nitride Polysilicon Nitride n C Polysilicon LTO/PSG Nitride

Process A uses LTO as the sacrificial layer and low stress nitride as the mechanical membrane [12]. Since the etching selectivity of LTO against nitride is adequate and nitride membrane is a good insulator, no etch stop layer or insulating layer between top and bottom electrodes is required. Process B uses polysil- icon as the sacrificial layer so that an etch stop layer is needed to separate the sacrificial layer and silicon substrate [14]. Nitride is a natural choice since it is the same material as the membrane. Process C uses LTO as the sacrificial later and polysilicon as the mechanical membrane as shown in Fig. 1, which is a modified version of previous work reported in [13]. In order to increase the effective electric field across the transducer, the polysilicon membrane is doped to form the top electrode. In this case, an electrically insulating layer is needed to separate the top electrode polysilicon and bottom electrode sili- con bulk to prevent shorting in the event of mem- brane collapse. Low stress nitride is used here since it can provide adequate selectivity against LTO in BOE solution (better than 1:lOO) during sacrificial etching.

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Nitride on highly doped silicon

Item I T I tll I t n I t b

Polysilicon on pattemed LTO

Via and sacrificial etching

num

LTO sealing

LTO patterning and removal

Metalization and patterning

Silicon substrate

[II1Il Silicon nitride

Aluminum

LTO

Polysilicon

Fig. 1. cMUTs Fabrication process C.

The major differences in the three processes are the conductivity, dielectric constant and residual stress of the membrane. Minor differences include Poisson Ratio, Young's modulus, and density. Since we are interested in immersion cMUTs working in the megahertz range, we use the following design pa- rameters, according to computer simulation based on electrical equivalent circuit model reported in [12], as shown in Table I1 where T is cell radius, t , is air gap thickness, t , is membrane thickness, t b is insulator thickness, and num is cell number. The major choice is whether to use a thinner vertical dimension and a lower DC bias voltage VOC with smaller cell size, or a thicker vertical dimension and a higher DC bias volt- age with larger cell size. Generally the latter option gives higher real to imaginary impedance ratio for better transducer efficiency and intrinsic bandwidth.

Table 11. Design Parameters for Immersion cMUTs. -

In this design, we mainly target a 50a real part transducer impedance in the frequency range of in- terest so that off-the-shelf electronics can be used in the transmitter and receiver modules. Computer simulations based on the cMUT electrical equivalent circuit model [12] show that the resultant transducer design has the impedance properties of Fig. 2 and Fig. 3. The theoretical simulation shows that Pro- cess C has the best properties in impedance absolute

values and real to imaginary impedance ratio. This is mainly due to the conductive membrane which does not reduce the vertical electric field. Process A is only slightly better than Process B indicating the bottom insulator or etch stop layer does not degrade much of the transducer performance.

1.75" Device with r=15~m,ia=600A,t~F;53WA,tb=1600A.nu~2500,Vdc=35v

Fig. 2. Real part impedance comparison.

1.75" Device wnh r=l 5~m.ta=600A,tn=5300A,tb=l6WA,num=25W,Vdc-35~

0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz)

Fig. 3. Imaginary part impedance comparison.

A final decision, however, requires consideration of both theoretical and practical issues. First, let us look at etching selectivity in sacrificial etching. Since the etch is seeded from the edge of the membrane, the membrane is attacked more at the edge than in the center when it has poor selectivity against the sacrificial material. This will give a dual tapered shape of the entire membrane as shown in Fig. 4 (b) instead of the ideal case of Fig. 4 (a). In Process A, the sacrificial etching is performed in BOE 6:l solu-

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tion for two hours. The etching selectivity of nitride to PSG/LTO is about 1:100, so the membrane loses 600A more nitride at the edge than in the center. With the initial design parameters shown in Table 11, the collapse voltage VCOL drops from 35v to 1Ov. This will prohibit Process A from achieving better performance than Process B.

(a) Membrane release with high etching selectivity

(b) Membrane release with low etching selectivity

Membrane [7 Substrate

Fig. 4. Etching selectivity in membrane release.

Both Process A and B have low tensile stresses within the nitride membrane which is tight enough to restore the membrane to flat position and provide adequate VDC range to optimize the transducer per- formance. On the other hand, Process C tends to have compressive stress within the polysilicon mem- brane, at least in our processes at Stanford Univer- sity, which will limit the effective membrane displace- ment and V'C range. In addition, if the stress or the air gap thickness is not well controlled, the trans- ducer might not be operational since the membrane stays permanently in its pull-in position which is one of the two stable positions.

Considering the above practical issues, we choose to optimize Process B. Process C will be the subject of future research.

B. Vacuum Sealing

Vacuum sealing is necessary to reduce the loss caused by water hydrolization caused by the high electric field inside the cavity. In previous work, we emphasized via sizing. Sealing of sub-micron vias defined by E-beam lithography was initially demon- strated [ll] with LPCVD nitride redeposition. When the via size is smaller than the air gap thickness t , , the sealing is especially effective with conformally de- posited species such as LPCVD nitride since it builds up an almost equal amount in both lateral and ver- tical directions. The via sealing always occurs at the opening of the membrane when the edges meet with

each other. Subsequently we observed that by depositing lower

sticking coefficients species, such as, LTO, larger vias defined by 2um optical lithography were successfully sealed from the bottom [14]. This greatly reduces the fabrication process complexity and production cost of immersion cMUTs. Nevertheless, both the above methods are problematic since the vertical de- vice dimension is perturbed in sealing and the di- mension is difficult to control exactly. In this paper, we present lateral sealing with a buffered zone that translates the perturbgtion in vertical dimension to lateral one. As shown in Fig. 5, when the depositing species get into the reservoir through the via, the vertical sidewall will keep majority of them in the reservoir without much leakage into the cavity re- gion. The drawback of this kind of sealing is that it takes 7 x 5 of minimum feature size units to provide sacrificial etching access instead of 1 x 1 of minimum feature size units in direct via placement [ll], [13]. In the 2um lithography technology used in this pa- per, the via takes up 14um x lOum area. The vias are placed in the dead corner area formed by four adjacent octagons which is about the size of 14um x 10um, so no further density loss is imposed.

7d

Fig. 5. Buffered reservoir lateral sealing.

111. EXPERIMENTAL RESULTS The transducers built with the design parameters

shown in Table I1 from Process B are used to gener- ate the experimental data. The top view SEM of a portion of a device is shown in Fig. 6 with 5um spac- ing between two adjacent octagonal cavities. 2500 orthogonally shaped elements with a period of 35um yield a total device area of 1.875" x 1.875".

The immersion cMUTs are directly connected to custom designed electronics with 40dB gain and 500 input and output impedances which are flat within

65 1

Fig G SE\( of immersion cRlUT w i t h \electivr metalkation

frequency range of interest. Time domain data are captured with an 8-bit digitized oscilloscope and fre- quency domain data are captured with a network analyzer. Subsequently the data are transferred to a computer for display and analysis.

Fig. 7 and 8 show the real and imaginary parts of the transducer impedance with immersion loading together with computer simulation results based on the electrical equivalent circuit model. ta=0.6um in- stead of ta=0.9um in Table I1 is used in the computer simulation since the DC bias voltage V ~ c = 3 5 v will shift the membrane ta/3 towards the substrate for best possible efficiency without collapse. 100% par- asitic capacitor is used to take into account of inter- connect, bond pads, and fringing capacitors although the active device metalization is only 25%. The serial resistance of the device is measured at around 5f2. It is clearly seen that 50R real part impedance occurs around 5MHz in both transmitter and receiver de- vice when VDC = 35v. This 50R location is easily shifted around when DC bias voltage Voc or ele- ment number num is changed in different designs. The computer simulation agrees with experimental data to the first order.

When a pair of the devices are used in immer- sion transmission, a signal t o noise ratio of at least 48dB is obtained as shown in Fig. 9. Taking into account of the magnitude of the AC excitation sig- nal and losses from impedance mismatch and diffrac- tion, better than lOOdB dynamic range is evident for cMUTs in immersion operation. This data is the best reported to date for immersion cMUTs oper- ating at megahertz frequency ranges. The acoustic power spectrum received is shown in Fig. 10 indicat- ing better than 50% bandwidth without tuning.

The next experiment investigates the effectiveness of the new sealing mechanism named buffered lat-

1.75" Device with r=l5um,ta=600A,tn=53M1A,tb=l600A,Vdc=35v,k=l00%

- 1 . . . . . , . .. . . . 1 . . . . .., .. , . , ..; . . .

t 1 t 1

loo[ I

Frequency (MHz) 10' 0 0.2 0 4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Fig. 7 . Real part impedance with immersion loading.

1 75" Devlce with r=l5um,ta=600A tn=5300A,tb=1600A,Vdc=35v,k=100% -1 0'

E e-102 8 E %

a 2

r

;-lo3

2

-1 0' 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2

10' Frequency (MHz)

Fig. 8. Imaginary part impedance with immersion loading.

era1 sealing. When a high sticking coefficient species is used to seal the via, the majority of the deposition occurs in the reservoir resulting in virtually no depo- sition in the octagonal cavity region. Fig. 14 shows the effective sealing in via and reservoir, but with negligible filling in the channel leading to the octag- onal cavity region as shown in Fig. 12. On the other hand, when low sticking coefficient species is used to seal the via, a portion of the deposition occurs in the octagonal cavity region as well, but with very con- formal coating inside. Fig. 11 shows the sealing with nitride which has extremely low sticking coefficient. It is evident that the deposition in both the final channel leading to the octagonal cavity and the cav- ity itself are very uniform with sharp vertical walls, The via is fully sealed and the reservoir surrounding the via are filled as shown in Fig. 13.

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Single Burst Reponse for Immersion MUTs with Vac=lv Transmission

5s

Normalized Acoustic Power Recelved from Immersion Transmiasion

-"" 1 00 t 0'

Frequency (MHz)

Fig. 10. Normalized power received with immersion loading and vDC=35V.

IV. CONCLUSION This paper presents an optimum immersion cMUT

operating in the megahertz frequency range. Two important issues in fabrication process are inves- tigated, namely membrane formation and vacuum sealing. Taking into account of both theoretical ide- ality and fabrication process reality, a silicon nitride membrane with a polysilicon sacrificial layer gives the most controlled results. A polysilicon membrane with an LTO/PSG sacrificial layer gives the best the- oretical results, but needs further research to fully achieve its potential. Newly proposed buffered lat- eral sealing prevents filling of the active octagonal cavity region which gives a controlled vertical dimen- sion.

The immersion cMUTs fabricated with the process

Fig. 11. SEM of unfilled etch channel leading to cavity with nitride sealing.

Fig. 12. SEM of unfilled etch channel leading to cavity with LTO sealing.

reported herein give a broad 50R real part impedance in the megahertz frequency range. When the trans- ducer is untuned, it gives better than 50% bandwidth with dynamic range of lOOdB at 4.5MHz, which is the best result reported to date for surface micro- machined ultrasonic immersion transducers. The re- sults indicate that surface micromachined ultrasonic immersion transducers are an alternative to piezo- electric transducers in immersion applications.

ACKNOWLEDGMENTS

This work has been made possible by grants from the United States Office of Naval Research. The first author would also want to acknowledge Fellow- ship support from the National University of Sin- gapore. Special thanks are due to Dr. James P.

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Fig. 13. SEM of a sealed via with nitride and its reservoir.

Fig. 14. SEM of a sealed via with LTO and its reservoir.

McVittie, Tom Carver, Pauline Prather, and other technical staff in Ginzton Laboratory and Center for Integrated Systems of Stanford University.

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