Student Presentation

High-Speed Circuits & Systems Lab.

Joungwook Moon

2013. 04. 01

About Paper

1

Contents

1. Introduction- Channel equalization- Conventional descrete equalizer

vs. Edge equalizer

2. Proposed equalizer architecture- TX equalizer (XFIR)- RX equalizer (XDFE)

3. Adaptation algorithm

4. Measurement result

5. Conclusion2

Contents

1. Introduction- Channel equalization- Conventional discrete equalizer

and timing ISI

2. Proposed equalizer architecture- TX equalizer (XFIR)- RX equalizer (XDFE)

3. Adaptation algorithm

4. Measurement result

5. Conclusion

One of the bottlenecks of increasing I/O speed islimited channel bandwidth.

TX RXChannel

TX eye RX eye

Channel Bandwidth & ISI

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Channel Equalization

TX RXChannel

TX eye RX eye

Equalizer Equalizer

Equalization compensates ISI

4

Channel Equalization

TX RXChannel

TX eye RX eye

Equalizer Equalizer

Cancel ISI at these points only

Equalization compensates ISI Discrete-time equalizers compensates ISI at data samples

ISI is left at the transitions edge Timing ISI

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Data ISI & Timing ISI

pulse response to a lossy channel

ISI

Timing ISI

After Eq.

Before Eq.

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Impact of timing ISI

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Conventional equalizers Concern about voltage margin at the center Edge samples are used to CDR Timing ISI increase sampling Jitter

7

Contents

1. Introduction- Channel equalization- Conventional discrete equalizer

and timing ISI

2. Proposed equalizer architecture- TX equalizer (XFIR)- RX equalizer (XDFE)

3. Adaptation algorithm

4. Measurement result

5. Conclusion

Proposed equalizer architecture

Full-rate TX- 10 tap FIR (5 taps for data, 5 taps for edge)

Half-rate RX- DFE with 3 taps edge & 3 taps data

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TX : DATA & Edge Equalization

Half-symbol spaced FIR filter

∆/2∆/2 ∆/2 ∆/2

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RX : Data & Edge Equalization

Type1 is similar to transmitter XFIR Type2 consists of two separated filters for data & edge path

Add Edge Equalization

(a) Type1 XDFE (b) Type2 XDFE

Traditional DFE

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Block diagram of Type2 XDFE

gm

gm

gm

gm

LL

y[n-

1]=0

y[n-

1]=1

y[n]

y[n-2]

gm

gm

gm

gm

LL

y[n]

=0

y[n]

=1

y[n-1]

y[n-3]

0 0 180 180

Input

Out0Data

Out180Data

ConventionalHalf-Rate Look-Ahead DFE

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Block diagram of Type2 XDFE

half-rate edge DFE.half-rate data DFE. half-rate data DFE.12

Eye diagrams of Type2 XDFE

Voltage Margin

Data

EdgeEdge

Data samples (same as conventional DFE)

Type2 XDFE is better than DFE- Same voltage margin as DFE- Edge sample is cleaner

half-rate edge DFE.half-rate data DFE.

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Contents

1. Introduction- Channel equalization- Conventional discrete equalizerand timing ISI

2. Proposed equalizer architecture- TX equalizer (XFIR)- RX equalizer (XDFE)

3. Adaptation algorithm

4. Measurement result

5. Conclusion14

Adaptation Algorithm

OutputDFE

Adaptation

Input

CDR

Clock and data recovery (CDR) and edge equalizer have conflicts Both mechanisms change transition edges

Simple LMS adaptations do not guarantee convergence Additional degree of freedom Multiple lock points

Requires modified LMS algorithm Guarantee convergence Maximize voltage opening14

0 0.5-0.5Time(UI)

1 234

(a)

sampling clock

Adaptation movements

0 0.5-0.5Time(UI)

1234

(b)

sampling clock

Adaptation movements

0 0.5-0.5Time(UI)

1234

(c)

sampling clock

Adaptation movements

0 0.5-0.5Time(UI)

12 34

(d)

sampling clock

Adaptation movements

Coefficients move toward sampling clock(Coefficient Adaptation)

Clock moves toward edge average (CDR)

Adaptation & CDR movement

1 2

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1. Introduction- Channel equalization- Conventional discrete equalizer

and timing ISI

2. Proposed equalizer architecture- TX equalizer (XFIR)- RX equalizer (XDFE)

3. Adaptation algorithm

4. Measurement result

5. Conclusion

Contents

measurement result

Transmitter with XFIR in 0.13 um CMOS (left) Receiver with XDFE in 0.18 um CMOS (right)

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Measurement result : Transmitter

Operating at 3.8Gbps Equalizing 120 inch FR4 Channel XFIR power = 137mWMax output swing = +/-240mV (480mVpp)

Timing ISI: 47psVoltage open: 19.2mV

FIR XFIR

Timing ISI: 37psVoltage open: 17mV

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Measurement result : Transmitter

XFIR has an advantage in timing noise dominated system

Measured BER of XFIR at 3.8 Gb/s

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Measurement result : Receiver

(a) 40in No DFE, (b) 40in DFE, (c) 80in DFE (d) 40 in DFE (no XDFE) , (e) 40 in (XDFE)

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Measurement result : Adaptation algorithm

Before : edges are spread After : edges are move to the center

Before Adaptation After Adaptation

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1. Introduction- Channel equalization- Conventional discrete equalizer

and timing ISI

2. Proposed equalizer architecture- TX equalizer (XFIR)- RX equalizer (XDFE)

3. Adaptation algorithm

4. Measurement result

5. Conclusion

Contents

Conclusion

An edge equalizer is implemented to compensatetiming ISI

XFIR can be more effective for systems with large jitter and channel attenuation > 20dB

XDFE recovered clock jitter reduction by 10%

LMS adaptation algorithm with added constraint

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