1High-Speed Circuits and Systems Lab.

High-Speed Circuits and Systems LaboratoryB.M.Yu

Content

2High-Speed Circuits and Systems Lab.

1. Introduction

2. Pre-emphasis

1. Amplitude pre-emphasis

2. Phase pre-emphasis

3. Circuit implantation

4. Result

5. Conclusion

Introduction

3High-Speed Circuits and Systems Lab.

- Method to compensate signal distortion

- Equalization technique from Rx

- Pre-emphasis technique from Tx

- Amplitude compensation of ISI

- Phase compensation of data-dependent jitter

- Both pre-emphasis technique is used for compensating signal distortion

- Minimizing power consumption while still improving signal integrity

Pre-Emphasis

4High-Speed Circuits and Systems Lab.

Amplitude pre-emphasis

- At high frequencies, loss is generated

by skin loss and dielectric loss

- Amplitude pre-emphasis compensate

frequency dependent loss in channel

Pre-Emphasis

5High-Speed Circuits and Systems Lab.

Amplitude pre-emphasis

Block diagram for one-tap feed-forward amplitude pre-emphasis driver

- Amplitude pre-emphasis compensates

frequency-dependent loss.

- Transfer function of this stage

= ( ) = (1 − )= 1 − 1 + ( /2)(1 + )/(1 − )1 + ( /2)- Additional pole, DC gain decline (De-

emphasis)

Pre-Emphasis

6High-Speed Circuits and Systems Lab.

Phase pre-emphasis

- DDJ (data dependent jitter) is form of DJ

(deterministic jitter) that limits the timing

margins.

- DDJ is related to when the previous

transition occurred.

- Phase pre-emphasis is for timing margins

of data eyes.

Pre-Emphasis

7High-Speed Circuits and Systems Lab.

Phase pre-emphasis

- DDJ is occurred depending on previous

bit relation

- Bit sequence must be moved for reduce

DDJ

- From previous bit relation, we can

calculate magnitude of time we must

move bit sequence

Pre-Emphasis

8High-Speed Circuits and Systems Lab.

Phase pre-emphasis

Circuit Implantation

9High-Speed Circuits and Systems Lab.

- 4:1 mux that provides amplitude pre-

emphasis

- Combinational logic for phase pre-emphasis

- Delay generation cells for controlling the

clock edge

- Duty cycle control cell for each clock phase

(process variation)

- AND logic for generate 25% duty cycle clock

- Implanted in IBM COMS 9SF.(90 nm bulk

triple-well CMOS technology)

Transmitter schematic

Circuit Implantation

10High-Speed Circuits and Systems Lab.

MUX & Amplitude pre-emphasis

- One-tap amplitude pre-emphasis

- One bit period time is used for data

transmitted sequentially

- Other three additional bit periods is

available

- Amplitude pre-emphasis is added

with original data.

Circuit Implantation

11High-Speed Circuits and Systems Lab.

DDJ Compensation

- Phase pre-emphasis combinational logic

- XORs calculates a previous transition in the

data

- It results in three differential transition

detection control bits

Circuit Implantation

12High-Speed Circuits and Systems Lab.

Delay generation

- Transition control bits control clock delay

- Each delay generation block have cascade

of three 3bit programmable delay cells.

- Control bit select one of two delay cell

(Programmable delay & nominal delay)

- Each consecutive delay cell is used to

handle the timing deviation

- Band-pass Buffer to reduce low freq. noise

Result

13High-Speed Circuits and Systems Lab.

Total and DDJ as phase pre-emphasis codes for first previous transition

Result

14High-Speed Circuits and Systems Lab.

- 2 -1 PRBS @ 6 Gb/s was passed through two test channels- 1st channel: 96 inches of RG-58 channel- RMS jitter reduce from 16.15ps to 11.06ps

(first transition, DDJ code: 011) - RMS jitter reduce from 16.15ps to 10.29ps

(second transition, DDJ code: 011)

Result

15High-Speed Circuits and Systems Lab.

Phase pre-emphasis

- 2 -1 PRBS @ 6 Gb/s was passed through two test channels- 2nd channel: 16 inches of FR-4 back plane - Amplitude pre-emphasis open the eye.- Phase pre emphasis reduce jitter from 13.84ps to 10.24ps (DDJ code: 010)

Result

16High-Speed Circuits and Systems Lab.

Phase pre-emphasis

- Voltage swing tracks the power consumption for both implementations of the transmitter

- 3~4 mW/Gb/s power consumption

Conclusion

17High-Speed Circuits and Systems Lab.

- Equalization technique for amplitude and phase pre-emphasis in bandwidth limited

interconnects

- Phase pre-emphasis: to compensate data dependent jitter

- Combining amplitude and phase pre-emphasis gives flexibility to tailor the signal

integrity of data eyes

- Architecture builds upon 4:1 multiplexer that allows for efficient implantation of

amplitude pre-emphasis

- Power : 3~4 mW/Gb/s

- Transmitter operation : 96 inches of cable , 16inches backplane interconnectors

18High-Speed Circuits and Systems Lab.

Thank you for listening