Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 4: Testing, Dataflow Modeling Spring 2009

Spring 2009W. Rhett Davis NC State University ECE 406 Slide 1

ECE 406 – Design of Complex ECE 406 – Design of Complex Digital SystemsDigital Systems

Lecture 4: Lecture 4: Testing, Dataflow Modeling Testing, Dataflow Modeling

Spring 2009Spring 2009W. Rhett DavisW. Rhett Davis

NC State UniversityNC State Universitywith significant material from Paul Franzon, Bill Allen, & Xun with significant material from Paul Franzon, Bill Allen, & Xun

LiuLiu


Announcements HW#1 Due Today

HW#2 Due in 1 week» Make sure that hw2-2.v executes correctly

with the command “ncverilog hw2-2.v”» Work through first to pages of Verilog

Simulation Tutorial (on the Resources Page) to learn more

Labs Start This Week


Summary of Last Lecture What is the format of a Verilog instantiation?

Are all parts of the instantiation required?

What is the order of the port-names in a gate instantiation? A module instantiation?

Can a reg variable be connected to the input port of an instance?


Today’s Lecture

Test-Benches

Behavioral (Data-Flow) Modeling


From Last Lecture

module mux_2 (out, i0, i1, sel); input i0, i1, sel; output out; wire n_sel, x1, x2; or (out, x1, x2); and (x1, i0, n_sel); and (x2, i1, sel); not (n_sel, sel); endmodule

out2-to-1Mux

i0

i1

sel

i0

seli1

out x1n_sel

x2

2-to-1 Multiplexer

How do we test this description?


Parts of a Verilog Module Header: module <module_name> (<port_list>); Parameter, Port, & Variable declarations Functionality description» Structural

– Instantiations of basic gates (T&M 6.2)– Instantiations of lower-level modules (T&M 1.4, 5)

» Behavioral– Data-Flow (continuous assignments) (T&M 2.2, 6.3)– Procedural (initial & always blocks) (T&M 2.3,3)

Terminator: endmodule


A Typical Test-Bench

Header: module <module_name>; Variable declarations Functionality description» Instantiation of the Device Under Test (DUT)» initial block to describe the Stimulus and

display the output Terminator: endmodule


Choosing the Stimulus Job of the Stimulus is to

apply test vectors (input combinations)

If we want to be 100% certain that the module is working correctly, how many vectors must be applied by the stimulus?

out2-to-1Mux

i0

i1

sel


Choosing the Stimulus Exhaustive testing

quickly becomes impractical as the number of inputs grows.

Need to choose a reduced set of test vectors that exposes the most likely errors.» It’s up to you to figure out

what kinds of errors you’re likely to make

For this example, we’ll use the following vectors:

i0 i1 sel0 1 00 1 11 0 01 0 1


Variable Declarations All variables in the test bench basically

connect to the DUT

Variables connected to DUT outputs» Will these be declared as wire or reg? Why?

Stimulus variables (connected to DUT inputs)» Will these be declared as wire or reg? Why?


mux_2 Test BenchWrite the module header, variable declarations, and instantiation for the mux_2 test-bench:

out2-to-1Mux

i0

i1

sel


mux_2 Test BenchStimulus and terminator for the mux_2 test-bench:

initial begin in0 = 0; in1 = 1; sel = 0; // vector #1 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 0; in1 = 1; sel = 1; // vector #2 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 0; // vector #3 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 1; // vector #4 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); $finish; // not needed, but handy if you want to end earlier endendmodule


Running the SimulationYou run the simulation,and the output looks like this:

in0 = 0 in1 = 1 sel = 0 out = xin0 = 0 in1 = 1 sel = 1 out = x in0 = 1 in1 = 0 sel = 0 out = x in0 = 1 in1 = 0 sel = 1 out = x

So what happened? Why was out an x?


Annotating Time

Delays are introduced into the stimulus by inserting #nn at the beginning of a statement (where nn is the number of time units)

Write the code to assign the hex values 1234 and 5678 into A and B simultaneously and then, 10 units of time later, assign the hex value 90AB is set into C:


mux_2 Test Bench w/ TimeStimulus for the mux_2 test-bench with 10 units of time between each vector:

initial begin in0 = 0; in1 = 1; sel = 0; // vector #1 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 0; in1 = 1; sel = 1; // vector #2 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 0; // vector #3 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 1; // vector #4 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); $finish; // not needed, but handy if you want to end earlier end


Re-running the Simulation

Having made these revisions, the simulation is rerunand the simulation output is:

in0 = 0 in1 = 1 sel = 0 out = 0in0 = 0 in1 = 1 sel = 1 out = 1in0 = 1 in1 = 0 sel = 0 out = 1in0 = 1 in1 = 0 sel = 1 out = 0

Which is what we would expect from the 2-to-1 mux.


Using $display and $monitor The $display task outputs the specified data whenever

a $display statement is encountered in the sequential execution of the stimulus.

The $monitor task watches the variables listed in the $monitor command and produces an output whenever any one of them changes.

A single $monitor statement may suffice in a test fixture instead of a series of identical $display statements.

Only one $monitor statement can be in effect during a simulation (the last one always takes effect).

It’s common to use single $monitor statement and multiple $display statements.


Simplified mux_2 Stimulus

initial begin $monitor($time, “in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 0; in1 = 1; sel = 0; // vector #1 #10 in0 = 0; in1 = 1; sel = 1; // vector #2 #10 in0 = 1; in1 = 0; sel = 0; // vector #3 #10 in0 = 1; in1 = 0; sel = 1; // vector #4 #10 $finish; end

Use $time here to print out current simulation time


Waveform Files Another way to display the output is to create

waveform files» .vcd files» .trn files

Use waveform viewers like SimVision to display these files

Explained in the Verilog Simulation Tutorial

Data

here

2 A 7

1 2 3 4 5time


ExerciseWrite a complete 4-vector test-bench for mux_4bit:


Today’s Lecture

Test-Benches

Behavioral (Data-Flow) Modeling


Describing Logic with Operators

Recall that the following expression is legal in Verilog:

sel ? B : A

“? :” is a ternary operator» (sel ? B : A) evaluates to B if sel is true and A if sel is

false

If sel is one bit, and A,B are 4-bit vectors, then isn’t there an easier way to describe the 4-bit MUX?


Continuous Assignments The next level of design abstraction above gate-

level design is dataflow, which is a kind of behavioral description.

Dataflow descriptions are created with the use of continuous assignment statements.

The format of a continuous assignment statement is:

assign <variable_name> = <expression>;

for example: assign Out = sel ? B : A;


How assign Works, Conceptually

What does continuous assignment mean for the purposes of port-connection rules, multiple assignments, etc.?

The statementassign Out = f(a,b,c,...);

is the same as instantiating a complex gate

Out

abc . . .

f(a,b,c,...){{

}Left-HandSide

Signal

Right-HandSide

Signals

Complex Gate


Port Connection Rules Is Out of type reg, wire or either?

Are sel, A, and B of type reg, wire or either?

What will happen if a continuous assignment is done twice to the same signal?


Four-Bit 2-to-1 MUXSo the code for the 4-bit mux from the last lecture becomes:

// Four-bit 2-to-1 multiplexermodule mux_4bit (Out, A, B, sel);input [3:0] A, B;input sel;output [3:0] Out;assign Out = sel ? B : A;endmodule

Note that we don’t need to incorporate the mux_2 module into this module.


Summary How many test vectors are in an exhaustive

stimulus?

How do you annotate time in a stimulus?

What is the most convenient system task to print the output during a simulation?

What keyword do you use when creating a dataflow behavioral description?

Documents

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 4: Testing, Dataflow Modeling Spring 2009