Spring 2007W. Rhett Davis with slight modification by Dean Brock UNCA ECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 11: Memories,

Spring 2007W. Rhett Davis with slight modification by Dean Brock UNCA ECE 406 Slide 1

ECE 406 – Design of Complex ECE 406 – Design of Complex Digital SystemsDigital Systems

Lecture 11: Lecture 11: Memories, LC-3 Instruction Set Memories, LC-3 Instruction Set

Spring 2007Spring 2007W. Rhett DavisW. Rhett Davis

NC State UniversityNC State Universitywith significant material from Paul Franzon, Bill Allen, & Xun with significant material from Paul Franzon, Bill Allen, & Xun

LiuLiu


Today’s Lecture

Using Memories

Review of the LC3 Instruction Set


Memories

Modules of even modest complexity usually contain memories. Applications of memories include register files, RAM & ROM.

Memories are simply arrays of identical registers!

In a memory, the “registers” are called “words”.

So a memory is conventionally referred to as “n word by m bit memory”. Here, n is the number of words (array elements) and m is the size of each word.

(This often shortened to “n x m”.)


Declaring Memories

reg bitmem [0:1023] // 1K x 1 (bit) memoryreg [7:0] MEM [0:16383] // 16K x 8 or 16K bytes

Note that the addressing range is usually specified as [<low_address> : <high_address>] and for physical reasons, the address range starts at 0.

Memories are defined by the syntax: <bit_range> <name> [<addressing_range>]


Verilog Language Structure

To read a single bit (or bit group), a memory word is brought out (read) and then dissected by additional logic.

More importantly, on a write, the entire memory word must be written. Therefore to change only part of a memory word’s data, a read, modify, write must be done.

Final comment: The syntax of Verilog (and physical structure of a memory) does not allow a portion of a memory word to be accessed.


Model for a ROM

module ROM(addr, dout);

input [13:0] addr;

output [7:0] dout;

reg [7:0] MEM [0:16383] // 16K x 8 or 16K bytes

always @(addr)

dout <= MEM[addr];

endmodule


Loading Memories

Verilog provides two system functions (commands) which will read a data file and place the file’s data into memory. Note that these commands do not imply any hardware but is simply an artifice used for simulation.

The commands are $readmemb (binary data) and $readmemh (hex data). The command syntax is:

$readmem* (“<file_name>”, <memory_name>);{* =“b” or “h”}

The $readmem* command can be inserted in the logic of any module in the design hierarchy. The preferred placement of this command is in the Test Fixture.


Loading Memories

The structure of <memory name> used in the $readmem* command depends on the hierarchical relationship of the modules in which the command and the memory reside.

If the target memory is located in the same module as the $readmem* command, <memory_name> is simply the name of the memory array.

Access to a memory in a module in the hierarchy falling below the test fixture is achieved by prefixing the memory name with the instantiation labels specifying the path to that module.


Loading Memories

Examples:

1. A test fixture contains a memory named MEM and the hex data file is named mem.dat. The $readmem* command would be:

$readmemh (“mem.dat”, MEM);

2. If instance dut contains a memory called MEM, it can be referenced as:

$readmemh (“mem.dat”, dut.MEM);


Loading Memories

The memory data file is a free format text file. Values read from the file are loaded sequentially into the memory (subject to addressing commands in the file).

The file must contain only the binary or hexadecimal data values, address specifications, white space and comments (both // and /* */ are recognized),. Each value must be separated with white space, comment, or new-line.

Data values are loaded starting at the beginning of memory unless a starting-address is specified. Load addresses can be specified with the “@” symbol followed by an address specification.


Loading Memories

Example: Contents of a typical memory data file (in hex):

// mem.dat -- initial data for memory (assumed to be 8 bits wide)@00 aa bb cc dd ee ff //loads locations 00h - 05h@10 11 22 33 44 55 66 //load locations 10h - 15h77 //load location 16h with 77h88 //load location 17h with 88h99 //load location 18h with 99h@04 ab //load location 04h with ab (replacing ee)

What would happen if this file were loaded into a memory with 16-bit words?


Today’s Lecture

Using Memories

Review of the LC3 Instruction Set


ISA of LC3: General Info

16-bit wide» Each word is 2-bytes wide» The memory space has 216 words

8 general purpose registers Data type: 2-complement integers 15 instructions Status registers: updated w/ registers

» NZP


Instruction Format

Opcode» IR[15:12]

Addressing mode» Immediate (sign extension)» Register» Memory: PC relative » Memory: indirect » Memory: base+offset


ALU Operation Instructions

AND» AND DR, SR1, SR2 (DR ← SR1 & SR2)» AND DR, SR1, Imm (DR ← SR1 & Imm)

ADD» ADD DR, SR1, SR2 (DR ← SR1 + SR2)» ADD DR, SR1, Imm (DR ← SR1 + Imm)

NOT» NOT DR, SR1 (DR ← ~SR1)


ALU Operation Instructions

ADD

AND

NOT

15 12 11 9 8 6 5 4 3 2 0

0 0 0 1 DR SR1 0 0 0 SR2

0 1 0 1 DR SR1 0 0 0 SR2

0 0 0 1 DR SR1 1 imm5

0 1 0 1 DR SR1 1 imm5

1 0 0 1 DR SR1 111111


Control Instructions Branch» BRx Offset

(PC ← PC+Offset)if any one of the specified flags is true

» …where “x” is one or more Flags: (set based on the result of the last operation)

– N - Negative– Z - Zero– P - Positive

» Variations:» ==0 (BRZ)» !=0 (BRNP)» >0 (BRP)» >=0 (BRZP)» <0 (BRN)» <=0 (BRNZ)» Unconditional jump

(BRNZP or simply BR)» Unconditional NOT

jump (BRNONE)


Control Instructions

Jump» JMP BaseR (PC ← BaseR)» RET (PC ← R7)

Jump to Subroutine» JSR Offset (R7 ← PC, PC ←

PC+Offset)» JSRR BaseR (R7 ← PC, PC ← BaseR)

Ignore the other instructions for now» RTI, TRAP


Control Instructions

BR JMP JSR JSRR RET RTI TRAP

0 0 0 0 NZP PCoffset9

15 12 11 9 8 6 5 4 3 2 0

1 1 0 0 000 BaseR 000000

0 1 0 0 000 BaseR 000000

0 1 0 0 1 PCoffset11

1 1 0 0 000 111 000000

1 0 0 0 000 000 000000

1 1 1 1 0000 Trapvect8


Data Movement Instructions

Load/Store (PC relative addressing mode)» LD DR, Offset (DR ← MEM[PC+Offset])» ST SR, Offset (MEM[PC+Offset] ← SR)

Load/Store Register (Base+Offset addressing mode)» LDR DR, BaseR, Offset

(DR ← MEM[BaseR+Offset])» STR SR, BaseR, Offset

(MEM[BaseR+Offset] ← SR)



Load/Store Indirect (indirect addressing mode)» LDI DR, Offset

(DR ← MEM[MEM[PC+Offset]])» STI SR, Offset

(MEM[MEM[PC+Offset]] ← SR)

Load Effective Address» LEA DR, Offset (DR ← PC+Offset)



LD: LDR: LDI: LEA: ST: STR: STI:

0 1 1 0 DR BaseR Offset6

15 12 11 9 8 6 5 4 3 2 0

0 0 1 0 DR PCoffset9



0 0 1 1 SR PCoffset9

1 0 1 1 SR PCoffset9

0 1 1 1 SR BaseR Offset6


Compile & Execute This Code

16’h3000 and r0, r0, #0; 16’h3001 add r0, r0, #7; 16’h3002 and r1, r1, #0; 16’h3003 add r1, r1, #5; 16’h3004 add r0, r0,#-1; 16’h3005 brp #-3 ; 16’h3006 st r1, #2 ; 16’h3007 lea r6, #4 ; 16’h3008 jmp r6 ; 16’h3009 var1: ; (0000)16’h300A var2: ; (0000)16’h300B var3: ; (0000)16’h300C …


Finish Executing the Code

16’h3009 var1: ; (0000)16’h300A var2: ; (0000)16’h300B var3: ; (0000)16’h300C ld r2, #-4 ; (25FC) 16’h300D add r2, r2, #1; (14A1)16’h300E str r2, r6, #-2 ; (75BE)

16’h300F str r6, r6, #-1 ; (7DBF)16’h3010 ldi r3, #-6 ; (A7FA)

16’h3011 jsr #1 ; (4801)16’h3012 brnzp #-1 ; (0FFF)16’h3013 ret ; (C1C0)

Documents

Spring 2007W. Rhett Davis with slight modification by Dean Brock UNCA ECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 11: Memories,