SPIE Proceedings [SPIE Microelectronics, MEMS, and Nanotechnology - Canberra, ACT, Australia (Wednesday 5 December 2007)] Microelectronics: Design, Technology, and Packaging III -

A New Total Static Leakage Estimation Model For UDSM-based Transistor Stacks

Hussam Al-Hertani, Dhamin Al-Khalili and Côme Rozon

Electrical and Computer Engineering Royal Military College of Canada

Kingston, ON, Canada

ABSTRACT

This paper introduces a new input pattern dependent model for total static leakage estimation in ultra deep submicron processes. The model integrates gate tunnelling leakage, gate induced drain leakage (GIDL) and subthreshold leakage into a single leakage estimation framework.

Subthreshold estimation is facilitated through the analytical estimation of nodal voltages between OFF transistors, while gate tunnelling leakage and GIDL are calculated based on simplified versions of their respective BSIM4 equations. The framework deals with all input patterns and accommodates scenarios where the various leakage currents interact.

Similar approaches in the literature are either based on a look up table approach, and do not accommodate transistor stacks with varying widths, or are highly experimental and require a detailed knowledge of the transistor device physics. Several approaches also exist for modeling either subthreshold leakage or gate tunnelling leakage separately. Even those approaches use a lookup table approach, fix all widths in a transistor stack and/or limit the stack size to 2-3 transistors. The model proposed in this paper is tractable and almost completely analytical. It is capable of accommodating stacks with up to 4 transistors with varying transistor widths.

A stack estimator function based on this model was coded in MatLab for the 65nm, 45nm and 32nm PTM process technologies. Compared with SPICE simulations the model exhibited an average error of 1.29%, 2.79%, 7.57% and 11.42% for stack sizes of 1, 2, 3 and 4 respectively across all three technologies. The model also exhibits significant runtime savings when compared with SPICE.

Keywords: static leakage estimation, subthreshold current, gate tunneling, GIDL, transistor stacks

1. INTRODUCTION

This paper outlines a simple model for the estimation of static leakage current in transistor stacks. The four leakage mechanisms addressed are subthreshold leakage, forward and reverse gate-tunneling and gate induced drain leakage (GIDL). The model is technology dependent and requires some device model parameters from the BSIM4 technology model files. Many static leakage current models exist ([1-4]); but almost all of them involve only one or two leakage current mechanisms at the most. They also tend to be strongly based on the pre-extraction of leakage current per unit transistor width for various scenarios (i.e. operating regions). Other models such as those presented in [3] tend to be purely deterministic with strong emphasis on the physical transistor structure. The static leakage estimation model proposed in this paper incorporates both the deterministic and pre-extraction approaches and models all four leakage current mechanisms accurately. The proposed model is very accurate and offers significant computational savings when compared with SPICE.

The work presented in this paper is divided into three sections. In the second section, an estimation models for each of the three major leakage components is developed. A framework for combining these models to provide an accurate estimate of total leakage in NMOS transistor stacks is then introduced in the third section. In the fourth section, MatLab simulations are carried out for all possible input vectors of one, two, three and four transistor stacks and their outcomes are compared with the results from SPICE simulations using the 32nm, 45nm and 65nm process PTM[5] model files.

2. LEAKAGE CURRENT MECHANISMS

2.1 Subthreshold current estimation

Consider the BSIM equation for subthreshold leakage [6]:

Microelectronics: Design, Technology, and Packaging III, edited by Alex J. Hariz, Vijay K. Varadan Proc. of SPIE Vol. 6798, 67980M, (2007) · 0277-786X/07/$18 · doi: 10.1117/12.758952

Proc. of SPIE Vol. 6798 67980M-1

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 10/11/2012 Terms of Use: http://spiedl.org/terms

( ) ( ) ( )( )tDSt

DSoffthGSt

effoxSUB vV

nvVVVV

WvL

CI /exp1exp8.1exp1 2'0 −−⎟⎟

⎠

⎞⎜⎜⎝

⎛ +−−⎟⎟⎠

⎞⎜⎜⎝

⎛=

ηµ (1)

Where VGS is the gate to source voltage, VDS is the drain to source voltage, vt = kT/q is the thermal equivalent voltage, Vth is the threshold voltage, Voff is a BSIM fitting coefficient, η is the DIBL coefficient, Cox

’ is the gate oxide capacitance, µ0 is the zero bias mobility and n is the subthreshold swing coefficient. Furthermore, the threshold voltage maybe approximated with minimal error as:

SBthth VVV ⋅+= ''0 γ (2)

where '0thV and 'γ are ‘linearized’ versions of the zero bias threshold voltage and the body effect coefficients

respectively.

In order to derive a simplified model, the last exponent term in the equation (1), is manipulated such that the 1-exp(-x) term is equated to exp(y) where x= VDS/vt . Note that when 0,4/ ≈≥= yvVx tDS . Now consider the equation:

⎪⎭

⎪⎬

⎫

⎪⎩

⎪⎨

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<≤+=−−<≤+=−−≥

=4.001.0,))exp(1ln(46.0,))exp(1ln(

4,0

xcxmxxcxmx

xy

BB

AA (3)

This shows that function y can be approximated by a piecewise linear function as seen in Fig 1. This linear interpolation provides an optimal fit w.r.t to the transition point between them. The optimal transition point was found using an exhaustive search that would provide the best overall fit using two subsequent linear functions. This point was determined to be x = 0.6. Taking the exponent of both sides of equation (3) yields the following approximation:

⎪⎭

⎪⎬

⎫

⎪⎩

⎪⎨

⎧

<≤+=−−<≤+=−−≥=

=6.001.0)exp()exp(146.0)exp()exp(1

41)0exp()exp(

xcxmxxcxmx

xy

BB

AA (4)

Using this result, the subthreshold current can be rewritten as follows:

( )

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=

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)(4/6.0),5385.0)/(1568.0exp(exp

)(4/,exp

cvVvVnv

VVVVAI

bvVvVnv

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avVnv

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I

tdstdst

dsoffthgsSUB

tdstdst

dsoffthgsSUB

tdst

dsoffthgsSUB

SUB

η

η

η

(5)

where Vth is calculated according to equation (2). The simplification shown in equation (4) allows us to approximate the BSIM subthreshold leakage expression using a single exponential term. Note how the piecewise linear function approximation presented above approximates the mathematical expression in equation (4) and is not process dependent. The set of equations (5) provide a simplified and comprehensive estimate of subthreshold leakage for a single transistor in all relevant VDS/vt regions.



Linearized pproximatiorsI I I I

y =5.0648x - 3.0511 y = 0.1 568*x0.5385

[ncPvd

x= VNt

Figure 1. Linearized approximation of the ln (1-exp(-x)) term

Consider the two-transistor NMOS stack shown in Fig.2. Assume that both inputs are OFF. To estimate subthreshold leakage, it is necessary to estimate a single nodal voltage VX between both transistors in the stack. This value is then substituted into the subthreshold equation (8) (defined later) to accurately estimate the subthreshold leakage. Determining VX involves equating the subthreshold equations for the top and bottom transistors. From simulation, VDS1 is typically close to VDD for any stack size (VDS1 = VDD-VX >> 4vt ) hence no piecewise linear approximation is required for the top transistor. Equation (5a) will ALWAYS be used to model the subthreshold leakage in the top transistor of any stack regardless of the transistor widths and the stack size.

For the bottom transistor we will use a generic form found in equations (5b) and (5c) with undefined constants m2 and c2. These constants provide the piecewise linear approximation required for the second transistor in the stack. Equating the subthreshold current in the top transistor with that of the bottom transistor, and defining all voltages (VGS, VDS and VS) in terms of VX yields:

))(exp())(exp( 22'0

2

''0

1t

txOFFth

t

xDDxOFFthx

vncvnmnVVVWA

vnVVVVVVWA

⋅⋅⋅+⋅+⋅+−−

⋅⋅=⋅

−⋅+⋅−−−−⋅⋅

ηηγ (6)

)21(

)ln(

2'

22

1

mn

cWW

vnVV

tDD

x ⋅+⋅++

⎥⎦

⎤⎢⎣

⎡−⋅⋅+⋅

=ηγ

η(7)

Equation (7) illustrates the mathematical expression for VX. From simulations it was also found that VDS2/Vt=VX/Vt is generally between 0.6 and 4. This implies that equation (5b) can be used to estimate subthreshold leakage in the bottom transistor in a two transistor stack. Hence m2 and c2 are typically 0.1568 and –0.5385 respectively. Once VX is calculated, the subthreshold current across the top transistor can then be easily calculated as shown in equation (8):

))(exp(''

011

t

xDDxOFFthxSUB vn

VVVVVVWAI⋅

−⋅+⋅−−−−⋅⋅=

ηγ (8)

Note that A, n, and η can be calculated based on their BSIM equations or via fitting. The linearized body coefficient γ’ can also be derived through fitting.



VUD

VDSI VDD-VX

= Vx

S2 VXI-VX2

= VX2

Fig 2. Two and three transistor stacks

For the three transistor stack shown in Fig. 2, there are two unknown inter-nodal voltages VX1 and VX2 (between first and second and second and third transistors respectively). We can solve for these two unknowns by generating two equations in terms of these unknown voltages. These equations can be derived by equating the subthreshold equations of the first and second transistor as well as the first and third transistor. The derivation is similar to the one shown above and results in the linear system of equations that shown in equation(9).

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)ln(

)()1(

)1()21( (9)

Similarly, a linear system of equations for solving the three nodal voltages VX1, VX2 and VX3 maybe used for estimating subthreshold leakage in the four transistor stack as shown in equation (10).

( )⎥⎥⎥⎥⎥⎥⎥⎥

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)ln(

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0)1()21((10)

Determining the variables mn,cn for the 3 and 4 transistor stacks will ultimately depend on the VDS/vt ratio of nth transistor in each stack. This paper proposes to accomplish this using a Bayesian classification approach. Consider the three transistor stack. For this scenario as mentioned earlier, the top transistor is always in the VDS / vt ≥ 4, and from simulations, it was observed that the middle transistor is always in the 0.6 ≤ VDS / vt < 4 region. So our goal is to determine the region in which the VDS / vt ratio of the bottom transistor exists. The VDS / vt ratio of the bottom transistor can be in either the 0.6 ≤ VDS / vt < 4, or the 0.01≤ VDS / vt < 0.6 range. Lets define these regions as classes (output variables) A and B respectively.

The next step is to determine the key features or input variables. Using the widths of the three transistors (W1, W2 and W3) as input features, a dataset needs to be created. This involves simulating a three transistor stack in SPICE with randomly chosen transistor widths at a given VDD and recording the VDS/vt ratio of each one of these entries. The output variable/ class for the dataset is then determined by assigning each entry to the class representing the VDS / vt range in which it lies. Through simulations, it was found that 100 data points per class was adequate. As an example the first five entries are shown in Fig.3. In order to acquire accurate statistics about each class, the entries in the table are divided into

N smaller tables where all entries in each of these smaller tables correspond to one class. The sample mean vector im



Input VariAbles Output VariableClass

7.68EOO 1 .92EOO 4.82EOO B6.1 4EOO 8.O4EOO 2.29EOO A9.53EOO 3.51 EOO 8.1 7EOO B1 .92EOO 9.52EOO 4.58EOO A5.55EOO 6.33EOO 5.1 8EOO A

Input Variables. Output yWi W2 W3 Class6.15E+OO 8.04E+OO 2.29E+OO A1.92E+OO 9.52E+OO 4.58E+OO A5.55E+OO 6.33E+OO 5.18E+OO A

Input Var! ables Output Var\V1 \V2 \V3 Class7.68E+OO 1.92E+OO 4.82E+OO B9.53E+OO 3.5 IE+OO 8. 17E+OO B

and the sample covariance matrix iΣ for each class ‘i’ are then calculated. The steps described so far are those required for training or pre-extraction and need to happen only once before the classification/estimation process is initiated. They are based on a fixed technology.

Figure 3. Training Process for Bayesian Inference

Once the pre-extraction process is complete, the classification process may begin. Assume that we design a three transistor stack with normalized widths W1 = 9.84 W2 = 7.11 and W3 = 7.98. This can be considered as a feature (input)

vector x = {9.84 7.11 7.98}. To determine whether the following input vector belongs to either class A or B we evaluate

the feature vector with the conditional density distribution ( )iWxp | of each class as shown in equations (11) and (12), given their mean vectors and covariance matrices.

( ) ( )( )

( ) ( )⎥⎦⎤

⎢⎣⎡ −Σ−−

Σ=Σ= −

AA

TA

AnAAA mxmxmxNwxp 1

2/12/ 21exp

21,,|

π (11)

( ) ( )( )

( ) ( )⎥⎦⎤

⎢⎣⎡ −Σ−−

Σ=Σ= −

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TB

BnBBB mxmxmxNwxp 1

2/12/ 21exp

21,,|

π(12)

Feature (input) vector x then belongs to the class whose conditional density distribution ( )iWxp | is largest. This approach for determining the VDS / vt region was also used for the 4 transistor stack.

2.2 Forward and Reverse Gate Tunneling Currents

The combination of gate voltage and reduction of gate oxide thickness in UDSM processes, results in an increase of electric field across the gate oxide. This electric field is large enough to cause electron tunneling through the gate oxide. This phenomenon is called gate tunneling. Gate tunneling leakage current can be very large for thin oxide layers. This is very significant for UDSM processes where the effective gate oxide thickness (TOXE) is scaled significantly. In fact TOXE is 18.5, 17.5 and 16.5 Å for the PTM 65nm, 45nm and 32nm processes respectively resulting in gate leakage current magnitudes as high as several nano-amperes (nA) for unit width transistors in these processes.

For NMOS transistors, forward gate tunneling is most significant when the device is ON and is in strong inversion. Backward gate tunneling exhibits slightly smaller leakage currents (but within the same order of magnitude) than forward gate tunneling currents. It generally takes place when the NMOS transistor is OFF and the drain is at VDD. The BSIM4 equation for forward and reverse gate tunneling is too complicated and not practical for use in our estimation model . A simpler equation was used to model both forward and reverse gate tunneling. This equation was fitted to gate tunneling data curves (IGC vs VGS) extracted from SPICE simulations. The goodness of fit (R) coefficient of the model to SPICE data for forward gate tunneling (against VGS) was recorded at 0.979, 0.964 and 0.997 for 32nm, 45nm and 65nm



respectively. And for reverse gate tunneling data (fitting against VDG), R was 0.9984, 0.9936 and 0.9961. The model used for fitting is:

)exp()( GSFC

GSFFFGC VDVBWAI F ⋅−⋅⋅+⋅= (13)

)exp()( DGRC

DGRRRGC VDVBWAI R ⋅−⋅⋅+⋅= (14)

where IFGC is forward and IRGC reverse gate tunneling currents. VGS is the gate source voltage, VDG is the drain to gate voltage, W is the normalized (with respect to unit width) width and A,B,C and D are all technology dependent fitting parameters. Fitting against normalized width was perfect ( R = 1) in all three processes since gate tunneling current scales linearly with normalized width and this relationship was easily fitted with the linear portion of the model

)( BWA +⋅ .

2.3 Gate Induced Drain Leakage

GIDL is caused by the existence of a high electric field at the drain junction of MOS transistors. In NMOS transistors, GIDL takes place when the drain is at a higher potential than the body of the transistor. This causes significant band bending in the drain, allowing electron-hole pair generation through avalanche multiplication and band-to-band tunneling. Because of the intractability of the BSIM4 equation for GIDL a simpler equation was used to model GIDL in 32, 45 and 65nm PTM processes.

⎟⎟⎠

⎞⎜⎜⎝

⎛ −⋅⋅=

DBDBGIDL V

BVAI exp (15)

Where IGIDL is the GIDL current, VDB is the drain to body voltage and A and B are fitting parameters determined through fitting the model to SPICE derived GIDL vs VDB curves. Fitting in this case was perfect (R=1) across all PTM processes considered.

3. LEAKAGE ESTIMATION FRAMEWORK

The estimation framework starts with applying the input vector and supply voltage to the stack. The VGS and VDG voltages for each transistor are then determined. The derived VGS and VDG voltages for each transistor are then applied to equations (13) and (14) respectively to determine the forward and reverse gate-tunneling leakage currents. If one or more transistors in the stack is OFF, subthreshold leakage is also estimated across the sub-stack of OFF transistors within the stack. Finally GIDL is also calculated whenever the drain is at a significantly high voltage i.e. (VDD or VDD − Vth). All these leakage sources are then superposed to give the total leakage unless the input vector is an exception vector. These exception vectors include all vectors that have one or more ON transistors placed in between two OFF transistors in the stack. For the three transistor stack, ‘010’ is the only exception vector . In this case, the large OFF resistance of the top and bottom OFF transistors reduces the forward gate-leakage current exhibited by the middle ON transistor, this in turn causes the voltages at the internal nodes VX1 and VX2 to rise to a small but significant voltage. These voltages at the internal nodes are equivalent and will be labeled as an exception voltage Vex. For the three-transistor stack, and in the PTM 45nm process, Vex = 0.32V (assuming VDD = 0.9). The exception voltage is process dependent; in fact Vex = 0.18V for the 65nm process. This voltage causes the VGS of the top transistor in the stack to become negative i.e. VGS = −0.32V/ − 0.18V and in turn the subthreshold leakage becomes negligible. Gate tunneling leakage is also reduced because VGS = VDD − Vex for the middle (ON) transistor. IRGC leakage takes place in the top transistor and some GIDL occurs at the top and middle transistors as well. Input vector ‘010’ is the only exception vector available in three transistor stacks.



Stack 0

1j1HQ\ Io:32V

Figure 4. Diagram illustrating the ‘inheritance’ pattern of exception voltages between exception input vectors of different stack sizes.(BPTM 45nm)

For the four transistor stack, ‘1010’,‘0101’,‘0010’,‘0100’ and ‘0110’ are all exception vectors. The first three can be viewed as the ‘children’ of the ‘010’ exception vector in a three transistor stack (See Fig. 4.) and share the same Vex. The Vex voltages for the last two however must be pre-determined separately (Vex2= 0.393V and Vex3= 0.394V @45nm and VDD = 0.9). This is because certain input vectors of the ith transistor stack inherit the exception voltages from other input vectors of the (i − 1)th transistor stack.. This inheritance concept reduces the number of exception vectors that need to be pre-determined to estimate gate leakage accurately. Furthermore, the exception voltages for different input vectors can sometimes be very close, e.g. the exception voltage for ’0110’ and ’0100’ are 0.393V and 0.394V respectively. Since these two exception voltages are nearly equal, only one voltage Vex2=0.39V needs to be pre-extracted, further reducing the number of exception voltages requiring pre-extraction. Using this approach, only 2 exception voltages need to be pre-extracted per technology for accurate static leakage estimation in the transistor stacks of up to four transistors.

4. SIMULATION RESULTS

Scripts for the two, three and four transistor stacks based on models and framework described in this paper were coded in MatLab. The results of these models were then compared to that of SPICE simulations using the 65nm, 45nm and 32nm BSIM4-based PTM processes. For each stack size, 1000 different scenarios with randomly chosen transistor widths (chosen within a range of normalized widths W=2 to 10) were applied to the proposed model and to SPICE simulations. The supply voltage was fixed at 0.9V for all three technologies. The results are tabulated in Table 1.

Table 1. Average percentage error exhibited by model w.r.t SPICE.

The runtime required by the model was also measured and compared to that of SPICE. The runtime values recorded in Table 2 are for a single stack estimation. It can be seen from the results that the proposed model is at least 54 times faster than SPICE (for the four transistor stack). For the two transistor stack the proposed model is 1230 times faster than SPICE. Note that the model runtime increases significantly from the 2 transistor stack to 3 transistor stack. This is primarily because of increased processing requirements of the Bayesian classification approach utilized in the subthreshold leakage estimation.

Average Percentage Error of total leakage

Standard deviation exhibited in average %

error

Stack size

32nm 45nm 65nm 32nm 45nm 65nm

1 0.984 1.279 1.796 0.983 1.380 1.053

2 2.731 2.159 2.791 4.714 3.555 2.574

3 7.854 7.566 7.844 9.142 10.43 9.299

4 11.77 10.52 11.71 12.24 12.15 12.80



5. CONCLUSIONS

This paper outlines a novel, fast analytical model for estimating total leakage current in transistor stacks with varying widths. The model can accommodate any stack size. Results demonstrate that the model is robust with respect to SPICE simulations in 3 UDSM technologies. The two transistor stack exhibits an average error of 2.8% with respect to SPICE simulations, while the 3 and 4 transistor stacks exhibit average errors of approximately 7.7% and 11.2% respectively. The model also exhibits significantly faster runtimes than SPICE.

Table 2. Runtime of proposed Model vs SPICE

REFERENCES

1. D. S. Dongwoo Lee, David Blaauw. Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Transactions on Very large Scale Integration (VLSI) Systems, 12:155–166, 2004.

2. R. S. Guindi and F. N. Najm. A gate-level leakage power reduction method for ultra-low-power CMOS circuits. Proc. of IEEE Custom Integrated Circuits Conference, March 2003.

3. K. R. S. Mukhopadhyay, A. Raychowdhury. Accurate estimation of total leakage current in scaled cmos logic circuits based on compact current modeling. 40th Design Automation Conference (DAC’03), June 2003.

4. S. Narendra et al, Scaling of stack effect and its application for leakage reduction, in ACM/IEEE International Symposium

on low Power Electronics and Design,6-7 Aug. 2001, pp.195 – 200.

5. Zhao, W., and Cao. Y.: New generation of Predictive Technology Model for sub-45nm design exploration, pp. 585-590, ISQED, 2006. http://www.eas.asu.edu/~ptm.

6. BSIM3.3 MOSFET Model - User’s Manual, 2001.

Runtime (ms) Stack

Size Model SPICE

2 0.0314 38.64

3 0.5533 47.06

4 0.9026 49.01



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SPIE Proceedings [SPIE Microelectronics, MEMS, and Nanotechnology - Canberra, ACT, Australia (Wednesday 5 December 2007)] Microelectronics: Design, Technology, and Packaging III -