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North Bridge. GPIO. SPI. I 2 C. UART. Analog. AFE. SMA. Analog. GPIO. Clock. USB. Micro-B. RGMII. JTAG. RJ45. FTSH. I 2 C. GPIO. SPI. South Bridge. North Bridge. AFE. VSUP - 3.6V ~ 5V. D3V3 - Digital 3.3V. D1V5 - Digital 1.5V. A1V5 - Analog 1.5V. A3V3 – Analog 3.3V. - PowerPoint PPT Presentation
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South Bridge
North Bridge
I2C
SPI
GPIO
I2C
SPI
GPIO
FTSH
Micro-B
SMA
JTAG
USB
Clock
RJ45
GPIO
RGMII
AFE
Analog
Analo
g
UA
RT
ETH PHY
South Bridge
North Bridge
VSU
P -
3.6
V ~
5V
D3V
3 -
Dig
ital 3.3
V
D1V
5 -
Dig
ital 1.5
V
A1V
5 -
Analo
g 1
.5V
A3V
3 –
Analo
g 3
.3V
AFE
SmartFusion
FPGAfabric
MSS CCC
CCCUSB CLKLP XTAL
MAIN CLK IN
EXT CLK IN
REF CLK OUT
EXT CLK OUT
RMII CLK
AFE 1 CLK
AFE 2 CLK
MSS32 kHzOSC
GLC
GLB
GLA0
PLL
20 MHzfrom SMA
20 MHzfrom TCXO
32 kHzfrom XTAL
50 MHzfrom ETH OSC
60 MHzfrom USB chip
max. 20 MHzto AFEs (DDR)
20 MHz (differential)to mezzanine
20 MHzto SMA
100 MHz RC OSC
SmartFusion
FPGAfabric
MSS CCC
CCCUSB CLKLP XTAL
MAIN CLK IN
EXT CLK IN
REF CLK OUT
EXT CLK OUT
RMII CLK
AFE 1 CLK
AFE 2 CLK
MSS32 kHzOSC
GLC
GLB
GLA0
PLL
GLC
20 MHzfrom SMA
20 MHzfrom TCXO
32 kHzfrom XTAL
50 MHzfrom ETH OSC
60 MHzfrom USB chip
max. 20 MHzto AFEs (DDR)
20 MHz (differential)to mezzanine
20 MHzto SMA
SmartFusion
FPGAfabric
MSS CCC
CCCUSB CLKLP XTAL
MAIN CLK IN
EXT CLK IN
REF CLK OUT
EXT CLK OUT
RMII CLK
AFE 1 CLK
AFE 2 CLK
MSS32 kHzOSC
GLC
GLB
GLA0
PLLG
LC
20 MHzfrom SMA
20 MHzfrom TCXO
32 kHzfrom XTAL
50 MHzfrom ETH OSC
60 MHzfrom USB chip
max. 20 MHzto AFEs (DDR)
20 MHz (differential)to mezzanine
20 MHzto SMA
SMA
AFE 1
AFE 2
Mezzanine
SMA
XTAL
XTAL
OSC
USBchip
ETH PHY
TCXO
EXT CLK IN
MAIN CLK IN
20 MHz
20 MHz
LP XTAL
32 kHz
RMII CLK
50 MHz
USB XTAL
12 MHz
USB CLK
60 MHz
EXT CLK OUT
20 MHz
AFE 1 CLK
max. 20 MHz
AFE 2 CLK
REF CLK OUT20 MHz
(differential)
ETH PHY
South Bridge
North Bridge
VSU
P
D3V
3
D1V
5
A1V
5
A3V
3
ADC, DAC
SRAM
South Bridge
North Bridge
I2C
SPI
GPIO
I2C
SPI
GPIO
FTSH
SMA
Jack/BNC
Analo
gJT
AG
JTAG
Clock I/O
Analog
LED
GPIO
EMI
SmartFusion
FPGAfabric
MSS CCC
CCCUSB CLKLP XTAL
MAIN CLK IN
EXT CLK IN
REF CLK OUT
EXT CLK OUT
RMII CLK
AFE1 CLK
AFE2 CLK
MSS
ETH PHY
32 kHzOSC
GLC
GLB
GLA0
PLLC
LKC
SmartFusion
Fabric
CCC
MSS CCCCCC
CCCCCC
CCCUSB CLK
LP XTAL
MAIN CLK IN
EXT CLK IN REF CLK OUT
EXT CLK OUT
RMII CLK
AFE1 CLK
AFE2 CLK
MSS
ETH PHY
32 kHzOSC
GLC
GLB
GLA
0
PLLC
LKC
SmartFusion
FPGA FabricCCC
MSS CCC
CCC
CCCCCC
CCCUSB CLK
LP XTAL
MAIN CLK IN
EXT CLK IN
REF CLK OUT
EXT CLK OUT
RMII CLK
AFE1 CLK
AFE2 CLK
MSS
ETH PHY
32 kHzOSC
DUT
GLC
GLB
GLA
0
PLL
CLK
C
FPGA FabricCCC
MSS CCC
CCC
CCCCCC
CCCUSB CLK
LP XTAL
MAIN CLK IN
EXT CLK IN
REF CLK OUT
EXT CLK OUT
RMII CLK
AFE1 CLK
AFE2 CLK
MSSETH PHY
32 kHzOSC
DUTGLC
GLBG
LA
0
PLL
FPGA FabricCCC
MSS CCC
CCC
CCCCCC
CCCUSB CLK
LP XTAL
MAIN CLK IN
EXT CLK IN
REF CLK OUT
EXT CLK OUT
RMII CLK
AFE1 CLK
AFE2 CLK
MSSETH PHY
32 kHzOSC
DUTGLC
GLBG
LA
0
PLL
CCC
MSS CCC
CCC
CCCCCC
CCCUSB CLKLP XTAL
MAIN CLK IN
EXT CLK IN
REF CLK OUT
EXT CLK OUT
ETH CLK AFE1 CLK
AFE2 CLK
MSS
ETH PHY
CCC CCC
CCCCCC
CCCUSB CLKLP XTAL
MAIN CLK IN
EXT CLK IN
REF CLK OUT
EXT CLK OUT
ETH CLK
