Slides for Beyond CMOS Computing 2017: Energy efficient

Beyond CMOS Computing 2017:

Energy efficient, high bandwidth digital data links between 4 and 300K

Dr Deborah Van VechtenOffice of Naval Research code 312

Superconducting Electronics Program Officer703 696 4219

[email protected]

Distribution A: Approved for Public Release: distribution unlimited. DCN#43-3448-17

Reducing full spectrum of signals to actionable information in close to real time is deployed DoD’s primary need for computing

• Complete spectrum is where ever there are signals we need to understand, ~0 to >100GHz

• Time critical tasks begin with identifying and separating signals by their functionality (friend or foe?) and routing to appropriate back-end systems

• Today done by up to 400 separate narrow band systems and many blade servers –complex, cumbersome, hard to fuse information

• Unified, multi-application system using common data seems desirable (MISD, common flowing memory)

Spectral Power Density

0-6 GHz has hundreds of simultaneous signals up all the time

050

100150200250300350400450

0 100 200 300 400

Watts of Wall Power

Temperature in Kelvin

Wall Power Cost of 1 W Lift (T)

2Distribution A: Approved for Public Release: distribution unlimited. DCN#43-3448-17

Progress toward ideal Digital-RF receiver with

superconducting ADC

early

~(2007)present

72 in.

Tall

Rack

Dual HF ADC

D. Gupta, D. E. Kirichenko, V. V. Dotsenko, R. Miller, S. Sarwana, A. Talalaevskii, J. Delmas, R. J. Webber, S. Govorkov, A. F. Kirichenko, I. V. Vernik,

and J. Tang, “Modular Multi-function Digital-RF Receiver Systems,” IEEE Trans. Appl. Supercond., vol. 21, no. 3, pp. 883-890, June 2011.

Dual Ka ADC

Allcoldhere

A second rack houses room temperature parts,

especially digital processors for DSP

Most development effort to date focused on Analog to

Digital Converters, especially increasing their

dynamic range and sampling rate

Recent focus has been on data link because ADC

threaten to need to output at >300 Gbps to bring

out all the information captured

10

mm Dual ADC chip


Cognitive receivers that adapt to changing tactical environments are needed and REQUIRE:

• Ultra-wideband Analog to Digital Converters– SCE has several candidates with different sensitivities and dynamic ranges

– Produce raw data at aggregate data rates from 20 Gbps to >320 Gbps from each ADC

– Many systems want multiple ADC in each instantiation

• Robust, adaptive, real-time Digital Signal Processing– Streaming processing very desirable

– Doing this in SCE domain is definitely desirable long term

– But largely waiting on IARPA Super Tools program to deliver modern CAD tools

• Data links that – Allow all the data to be reported if user desires

– Are energy efficient enough that data IO doesn’t dominate total energy budget

– Don’t frequently corrupt the data with errors, especially not due to failure of channel bonding/ time synchrony

– Can be monitored for accuracy in real time so to minimize duration of halts of the data flow for data retransmission or recalculation or acceptance that entire time segments of dropped results will occur

– Channel bonding and forward error correction added need to have low fractional data thruputimpact (low overhead)

• All SCE systems will benefit from improved data links


Detailed Steps in Electrical Digital Data Flow Today

INPUT

Data

Prep format for

transport to 4K

Coax

to 4K

Receive at 4K

& prep for use

(de-skew and buffer)

Process

Prep format for

Transport to 300KAmplify

Coax to 300K

Prep format for

entry into COTS

300K processor &

Insure data integrity

300K 4K


Currently fielded 2 Gbps Data Link

2nd Stage

T = 4K

1st Stage

T = 40-50

K

Ambient

T = 300K

ADCChip

Custom Stripline 4-300K Cable

Vacuum Feedthrough

Thermal Links

FPGA

DSP, e.g. COTS FPGADigital Polyphase Channelizers

Multi-channel Interface Amplifier + Discriminator +

Optional Deserializer

Cooled by COTS Cryocooler

Bank of Output

drivers

4-K Chip Module


Ongoing all electrical link improvements

Xilinx

FPGA Board

Drivers on superconductor IC

➢ Converts SFQ pulses to voltage

➢ 3 - 5mV output amplitude

Flexible transmission line

➢ Transfer signal from 4K to 300K

➢ Replace with superconducting

version to lower heat transfer

Compacted, multi-channel signal

capture amplifier at 300K

Custom Interface adapter

High-speed FPGA transceivers

➢ Using Xilinx GT transceiver family

➢ Enables single links up to 32 Gbps

➢ >100 GT available per FPGA chip

Cryogenic semiconductor amplifiers

12 Gbps Eye

Diagram


All electrical approach is non-ideal for large scale processors

• As data rate rises, so does the number of wires required – 1Tbit/ps per wire not realistic

– Each wire represents non-trivial parasitic heat load and adds assembly complexity

• Photonic digital data transport at 300K well developed and continues to improve in energy efficiency– By the time SCE computer is done, all connection at RT likely to be photonic

– DWDM offers many carriers per fiber, reducing complexity of connector management

– Each fiber is thermal insulator – low static parasitic heat load on 4K

– Many fibers are entirely suitable for spanning 300K to 4K without shattering, fatiguing upon thermal cycles, or drastically changing photonic transport properties

• Not all trends in RT photonic links will be optimal for 4K egress– Need to evaluate each after actually measuring parameters

– In-chip waveguide materials– does index of refraction shift?

– RT move to complex QAM data encoding built on basis of “zero” cost Si complexity for encoders/decoders – not true of JJ– and desire to install no more fiber cables, yet increase long haul traffic – unneeded in local server


One Imagination of Cryogenic Photonic Data Flow

INPUT

Data

Prep format for

transport to 4K

Amplify

and EOMLaser Fiber to 4K

Receive at 4K

& prep for use

(de-skew and buffer)

Process

Prep format for

Transport to 300KAmplify

EOM

Fiber to 300K

Prep format for

entry into COTS

300K processor &

Insure data integrity

OEM

OEM

300K 4K

Coupling

Modulation

enhancement


Photonic data links

Most difficult component is the low T EO part that is optimized to work cold and with SCE RZ logic.

Ideal Super Cables program outcome would be that running EO cold provides inherent advantages over operation at room temperature sufficient to compensate for the cooler inefficiency.

3 broad categories possible:

• Resonator structures: arrival of electrical signal changes the resonate frequency causing modulation of the amplitude of coupled optical carrier

• Lasing structures:

– VSCELS

– Various geometry, in plane emission semiconductor lasers

– Superconducting lasers

• Improvements of conventional bulk modulators


4 port MZ Interferometer

Illustrations of photonic parts

master

laser

Whistle-geometry

injection-locked ring laser

DCRF

Electrical Bias (V)0.3 0.4 0.5

Tra

nsm

issio

n

0

0.2

0.4

0.6

0.8

1


Sensitiv

ity (

V-1

)

0

50

100

150

200


V: (

dB

V)

-15

-10

-5

0

Optical pump power (dBm)-20 -10 0

V: (

Volts)

10-2

10-1

100

Bistable

Regime

Increasing

pump power

200mV

18mV

Testing Photonic IC

Ring resonators, Ala DWDM

Some with “enhancers” added

15 dB shift

in T with

10V bias

Traveling wave & photonic crystal structures

Solid State optical cooling

Is there a clocked impulsive photoniclogic that matches to SFQ?


Other difficult issues for photonic data links

• Optical beam coupling on/off chip needs to approach 99.99% efficiency, >> than available today

• Fibers and chip holders will likely experience different shifts in position thanks to different coefficients of thermal expansion. How will aim of fibers be accomplished?

• How severely will in-chip waveguide modes and confinement change with T?

• How can resonances be trimmed at 4K?

• How fast can the photonic parts respond and especially reset?

• Will data dependent temperature swings of active components require active temperature compensation?

• What mechanism for initial channel bonding at data rates of up to 100 Gbpsexists, can be invented?

• Can the signal to noise ratio be improved within the photonic link?

• Using photons of lower energy than telecom at 4K would assist the initial SFQ to photonic signal issues, but is there a way to do frequency upconversion at RT in energy efficient manner?

• Proper electrical hand-off at the SCE to photonic interface and cryopackaging


Conclusions

• High bit rate, energy efficient data links are essential if cryogenic forms of computing are to succeed in the Beyond CMOS world

• Electrical approaches are proven and in use, but will likely fail to scale well to large systems

• Photonic approaches are unexplored below 300K, but do multiplex well and fiber has low heat load and cross talk issues

• Work on EO components is justified to see if materials and or devices properties can enable operation in highly energy efficient manner at 4K


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Slides for Beyond CMOS Computing 2017: Energy efficient